coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in coreboot[master]: mb/google/drallion: Update SD Card pci device
by Selma Bensaid (Code Review) 08 Oct '19

08 Oct '19

Hello Selma Bensaid, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35655 to review the following change. Change subject: mb/google/drallion: Update SD Card pci device ...................................................................... mb/google/drallion: Update SD Card pci device Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.corp-partner.google.com> Change-Id: Icb96fe433014c905ebf896bdcb7d43cb57563313 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/35655/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d824a55..42310f5 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -399,9 +399,7 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" - end # PCI Express Port 9 + device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 on end # PCI Express Port 12 -- To view, visit https://review.coreboot.org/c/coreboot/+/35655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb96fe433014c905ebf896bdcb7d43cb57563313 Gerrit-Change-Number: 35655 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK
by Aaron Durbin (Code Review) 08 Oct '19

08 Oct '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35896 ) Change subject: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG@8 PS1, Line 8: Could you please provide the reasoning here as to why this is needed? https://review.coreboot.org/c/coreboot/+/35896/1/src/security/vboot/verstag… File src/security/vboot/verstage.c: https://review.coreboot.org/c/coreboot/+/35896/1/src/security/vboot/verstag… PS1, Line 28: memset(_bss, 0, (_ebss-_bss)); This is the wrong place for this hack. -- To view, visit https://review.coreboot.org/c/coreboot/+/35896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe0ccfb776b8150f547cb691e082c206f80a8fc Gerrit-Change-Number: 35896 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 08 Oct 2019 16:16:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK trogdor: SoC makefile BLOB support HACK
by mturney mturney (Code Review) 08 Oct '19

08 Oct '19

Hello ashk(a)codeaurora.org, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35508 to look at the new patch set (#7). Change subject: HACK trogdor: SoC makefile BLOB support HACK ...................................................................... HACK trogdor: SoC makefile BLOB support HACK Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Signed-off-by: Ashwin Kumar <ashk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc 1 file changed, 114 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35508/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 7 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Arthur Heymans (Code Review) 08 Oct '19

08 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 23: (3 comments) https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/devicetree.cb: https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… PS23, Line 120: remove tab and fix alignment of things below. https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… PS23, Line 28: : /* Seems copied from Lenovo Thinkpad x201, might be wrong */ fix? https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/smihandler.c: https://review.coreboot.org/c/coreboot/+/11791/23/src/mainboard/lenovo/t410… PS23, Line 32: mainboard_io_trap_handler There are no ACPI calls for IO trap, so please rename this and reduce the scope. I have a local version fixing this on x201... -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 23 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Oct 2019 15:11:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 08 Oct '19

08 Oct '19

Patrick Rudolph has uploaded a new patch set (#23) to the change originally created by Nicolas Reinecke. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT Testing in progress. Untested: * VGA * Displayport Bugs: * AC adapter can't be read from ACPI Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t410.md A Documentation/mainboard/lenovo/t410_chip_location.jpg A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/data.vbt A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/gma-mainboard.ads A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smi.h A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h A src/mainboard/lenovo/t410/vboot-rwa.fmd 29 files changed, 1,548 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/11791/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 23 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 08 Oct '19

08 Oct '19

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 08 Oct '19

08 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 21: (19 comments) Rebased on master, removed 90% of boilerplate code. Still boots to Linux. https://review.coreboot.org/c/coreboot/+/11791/21/Documentation/mainboard/i… File Documentation/mainboard/index.md: https://review.coreboot.org/c/coreboot/+/11791/21/Documentation/mainboard/i… PS21, Line 91: ## Portwell > Spurious? no it was messing up the lenovo section https://review.coreboot.org/c/coreboot/+/11791/21/Documentation/mainboard/l… File Documentation/mainboard/lenovo/t410_chip_location.jpg: PS21: > I think a closer image would be more helpful. […] no, it's assembled again https://review.coreboot.org/c/coreboot/+/11791/17/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/Kconfig: https://review.coreboot.org/c/coreboot/+/11791/17/src/mainboard/lenovo/t410… PS17, Line 34: MMCONF_BASE_ADDRESS > Care to send a separate patch to move this to nb/nehalem/kconfig? removed as it's the default value https://review.coreboot.org/c/coreboot/+/11791/17/src/mainboard/lenovo/t410… PS17, Line 42: config MAX_CPUS : int : default 4 : : config CPU_ADDR_BITS : int : default 36 > To me it makes more sense to put these in cpu/intel/model_2056x. removed as it's the default https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/Kconfig: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 63: default 4 > Clarckfield CPU's (quadcore) are supported by the current code. […] done https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/acpi_tables.c: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 21: static void acpi_update_thermal_table(global_nvs_t *gnvs) : { : gnvs->tcrt = CRITICAL_TEMPERATURE; : gnvs->tpsv = PASSIVE_TEMPERATURE; : } > Do we really need a function just for that? Done https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/devicetree.cb: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 32: # > Maybe remove the empty comments Done https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 122: end > Maybe move to the previous line, and remove the "dummy" comment? Done https://review.coreboot.org/c/coreboot/+/11791/18/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/mainboard.c: https://review.coreboot.org/c/coreboot/+/11791/18/src/mainboard/lenovo/t410… PS18, Line 20: #include <device/pci_ops.h> > remove? Done https://review.coreboot.org/c/coreboot/+/11791/18/src/mainboard/lenovo/t410… PS18, Line 22: #include <northbridge/intel/nehalem/nehalem.h> : #include <southbridge/intel/bd82x6x/pch.h> > remove? Done https://review.coreboot.org/c/coreboot/+/11791/19/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/19/src/mainboard/lenovo/t410… PS19, Line 22: #include <string.h> > remove? Done https://review.coreboot.org/c/coreboot/+/11791/19/src/mainboard/lenovo/t410… PS19, Line 23: #include <arch/io.h> > remove Done https://review.coreboot.org/c/coreboot/+/11791/19/src/mainboard/lenovo/t410… PS19, Line 25: #include <device/pci_def.h> > unused? Done https://review.coreboot.org/c/coreboot/+/11791/19/src/mainboard/lenovo/t410… PS19, Line 26: #include <device/pnp_def.h> > unused Done https://review.coreboot.org/c/coreboot/+/11791/19/src/mainboard/lenovo/t410… PS19, Line 36: #include <arch/early_variables.h> > remove Done https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 51: pci_write_config16(PCH_LPC_DEV, LPC_EN, : CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | : COMA_LPC_EN | GAMEL_LPC_EN); > Maybe reflow this so that it fits in two lines. […] removed https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 54: : pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); : pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); : pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); : pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); > Any idea if you need those during romstage as there is ramstage code to set those up based on dt (co […] rebased and remove the code https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/vboot-rwa.fmd: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 10: 0x16ffc0 > I think you can drop this. It should fill the remaining space. Done https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 27: 0xff000 > same Done -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 21 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Oct 2019 14:58:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 08 Oct '19

08 Oct '19

Patrick Rudolph has uploaded a new patch set (#22) to the change originally created by Nicolas Reinecke. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT Testing in progress. Untested: * VGA * Displayport Bugs: * AC adapter can't be read from ACPI Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t410.md A Documentation/mainboard/lenovo/t410_chip_location.jpg A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/data.vbt A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/gma-mainboard.ads A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smi.h A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h A src/mainboard/lenovo/t410/vboot-rwa.fmd 29 files changed, 1,550 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/11791/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 22 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Tim Wawrzynczak (Code Review) 08 Oct '19

08 Oct '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 08 Oct 2019 14:26:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device: Use scan_static_bus() over scan_lpc_bus()
by Nico Huber (Code Review) 08 Oct '19

08 Oct '19

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/29474 ) Change subject: device: Use scan_static_bus() over scan_lpc_bus() ...................................................................... device: Use scan_static_bus() over scan_lpc_bus() Devices behind LPC can expose more buses (e.g. I2C on a super-i/o). So we should scan buses on LPC devices, too. Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/root_device.c M src/include/device/device.h M src/northbridge/via/vx900/lpc.c M src/northbridge/via/vx900/traf_ctrl.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/fsp_broadwell_de/southcluster.c M src/soc/intel/quark/lpc.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/amd8111/lpc.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb900/late.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/amd/sb800/lpc.c M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/i82371eb/isa.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/nvidia/ck804/lpc.c M src/southbridge/nvidia/mcp55/lpc.c 33 files changed, 31 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Aaron Durbin: Looks good to me, approved Felix Held: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/src/device/root_device.c b/src/device/root_device.c index 84d3ba6..6801b41 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -56,15 +56,6 @@ } } -void scan_lpc_bus(struct device *bus) -{ - printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - - enable_static_devices(bus); - - printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); -} - void scan_generic_bus(struct device *bus) { struct device *child; diff --git a/src/include/device/device.h b/src/include/device/device.h index a7ba5a9..405d816e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -330,7 +330,6 @@ void enable_static_devices(struct device *bus); void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); -void scan_lpc_bus(struct device *bus); void scan_static_bus(struct device *bus); #endif /* !defined(__ROMCC__) */ diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index cab783e..fd4d5ad 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -235,7 +235,7 @@ .set_resources = vx900_lpc_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index 8f3f602..2ef542a 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -132,7 +132,7 @@ .init = vx900_traf_ctr_init, /* Need this here, or the IOAPIC driver won't be called. * FIXME: Technically not a LPC bus. */ - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, }; static const struct pci_driver traf_ctrl_driver __pci_driver = { diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index c794601..628273d 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -330,7 +330,7 @@ .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 8f65433..3c0c07f 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -530,7 +530,7 @@ .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 67e941c..9118f00 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -598,7 +598,7 @@ .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b385d6b..2bebcb8 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -634,7 +634,7 @@ .acpi_inject_dsdt_generator = southcluster_inject_dsdt, .write_acpi_tables = broadwell_write_acpi_tables, .init = &lpc_init, - .scan_bus = &scan_lpc_bus, + .scan_bus = &scan_static_bus, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 46dfd7f..eb7de08 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -115,7 +115,7 @@ .write_acpi_tables = southbridge_write_acpi_tables, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = lpc_soc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index f6f0983..2b148f2 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -119,7 +119,7 @@ .enable_resources = pci_dev_enable_resources, .init = pmc_soc_init, .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 5af0781..123fb24 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -317,7 +317,7 @@ .enable_resources = lpc_enable_resources, .init = lpc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 356b855..a042bb5 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -605,7 +605,7 @@ .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index 31dcc25..d1981fd 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -294,7 +294,7 @@ .write_acpi_tables = southcluster_write_acpi_tables, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_acpi_name, diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c index 19f7ceb..df5bdca 100644 --- a/src/soc/intel/quark/lpc.c +++ b/src/soc/intel/quark/lpc.c @@ -53,7 +53,7 @@ .read_resources = pmc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, }; static const struct pci_driver pmc __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 9b18315..4cfbb64 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -347,7 +347,7 @@ .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, }; diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index c4a7896..b4a92a0 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -164,7 +164,7 @@ .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .enable = amd8111_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 1e1cfe0..4233a6f 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -167,7 +167,7 @@ .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, }; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index fc321f8..3a65e33 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -116,7 +116,7 @@ #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 02123a1..1e080a0 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -363,7 +363,7 @@ .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, .acpi_name = lpc_acpi_name, }; diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index eb171e6..5d6d1cd 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -282,7 +282,7 @@ .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 580138a..0ca50cc 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -251,7 +251,7 @@ .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index 17bc8bc..5ac15e0 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -124,7 +124,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = bcm5785_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, // .enable = bcm5785_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index b8df7aa..f67d1e4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -918,7 +918,7 @@ .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index be7913c..d12c379 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -446,7 +446,7 @@ .write_acpi_tables = acpi_write_hpet, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .enable = soc_lpc_enable, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 00b3866..bb88f7d 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -142,7 +142,7 @@ .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = isa_init, - .scan_bus = scan_lpc_bus, /* TODO: Needed? */ + .scan_bus = scan_static_bus, .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 2daed4a..031a01a 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -339,7 +339,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 62576c1..670c2f8 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -695,7 +695,7 @@ .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .enable = i82801gx_enable, .ops_pci = &pci_ops, .final = lpc_final, diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index cb964de..a79ade7 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -543,7 +543,7 @@ .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 6c63186..a395069 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -701,7 +701,7 @@ .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_name = lpc_acpi_name, .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a457722..3657656 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -784,7 +784,7 @@ .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 28e3544..4b44759 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -981,7 +981,7 @@ .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 8caa8ed..63e0de5 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -314,7 +314,7 @@ .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &ck804_pci_ops, }; diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 6416dd3..de2de5c 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -247,7 +247,7 @@ .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_lpc_bus, + .scan_bus = scan_static_bus, .ops_pci = &mcp55_pci_ops, }; static const unsigned short lpc_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/29474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Gerrit-Change-Number: 29474 Gerrit-PatchSet: 11 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit October 2019