coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Tim Wawrzynczak (Code Review) 08 Oct '19

08 Oct '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 08 Oct 2019 18:18:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: superio/it8772f: use pnp_ops.h for pnp register access
by Felix Held (Code Review) 08 Oct '19

08 Oct '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35860 ) Change subject: superio/it8772f: use pnp_ops.h for pnp register access ...................................................................... superio/it8772f: use pnp_ops.h for pnp register access Change-Id: I983249fb54b6fbccc4339c955cb5041848b21cf8 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/ite/it8772f/early_init.c 1 file changed, 17 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/35860/1 diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c index 95be01c..d605fb1 100644 --- a/src/superio/ite/it8772f/early_init.c +++ b/src/superio/ite/it8772f/early_init.c @@ -21,26 +21,6 @@ /* NOTICE: This file is deprecated, use ite/common instead */ -/* RAMstage equiv */ -/* u8 pnp_read_config(pnp_devfn_t dev, u8 reg) */ -u8 it8772f_sio_read(pnp_devfn_t dev, u8 reg) -{ - u16 port = dev >> 8; - - outb(reg, port); - return inb(port + 1); -} - -/* RAMstage equiv */ -/* void pnp_write_config(pnp_devfn_t dev, u8 reg, u8 value) */ -void it8772f_sio_write(pnp_devfn_t dev, u8 reg, u8 value) -{ - u16 port = dev >> 8; - - outb(reg, port); - outb(value, port + 1); -} - void it8772f_enter_conf(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -53,15 +33,15 @@ void it8772f_exit_conf(pnp_devfn_t dev) { - it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02); + pnp_write_config(dev, IT8772F_CONFIG_REG_CC, 0x02); } /* Set AC resume to be up to the Southbridge */ void it8772f_ac_resume_southbridge(pnp_devfn_t dev) { it8772f_enter_conf(dev); - it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); - it8772f_sio_write(dev, 0xf4, 0x60); + pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); + pnp_write_config(dev, 0xf4, 0x60); it8772f_exit_conf(dev); } @@ -71,14 +51,14 @@ { set--; /* Set 1 is offset 0 */ it8772f_enter_conf(dev); - it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); if (set < 5) { - it8772f_sio_write(dev, GPIO_REG_SELECT(set), select); - it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable); - it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity); + pnp_write_config(dev, GPIO_REG_SELECT(set), select); + pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); + pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity); } - it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output); - it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup); + pnp_write_config(dev, GPIO_REG_OUTPUT(set), output); + pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup); it8772f_exit_conf(dev); } @@ -88,15 +68,15 @@ { set--; /* Set 1 is offset 0 */ it8772f_enter_conf(dev); - it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + pnp_write_config(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); if (set < 5) { - it8772f_sio_write(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map); - it8772f_sio_write(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq); - it8772f_sio_write(dev, GPIO_REG_SELECT(set), select); - it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable); - it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity); + pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_PINMAP, led_pin_map); + pnp_write_config(dev, IT8772F_GPIO_LED_BLINK1_CONTROL, led_freq); + pnp_write_config(dev, GPIO_REG_SELECT(set), select); + pnp_write_config(dev, GPIO_REG_ENABLE(set), enable); + pnp_write_config(dev, GPIO_REG_POLARITY(set), polarity); } - it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output); - it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup); + pnp_write_config(dev, GPIO_REG_OUTPUT(set), output); + pnp_write_config(dev, GPIO_REG_PULLUP(set), pullup); it8772f_exit_conf(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I983249fb54b6fbccc4339c955cb5041848b21cf8 Gerrit-Change-Number: 35860 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK
by Aaron Durbin (Code Review) 08 Oct '19

08 Oct '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35896 ) Change subject: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG@8 PS1, Line 8: > As indicated this is a HACK patch and not expected to be reviewed. […] Got it. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/35896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe0ccfb776b8150f547cb691e082c206f80a8fc Gerrit-Change-Number: 35896 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 08 Oct 2019 18:09:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: superio/winbond/w83627*: use hwm5_conf.h for HWM setup
by Felix Held (Code Review) 08 Oct '19

08 Oct '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35862 ) Change subject: superio/winbond/w83627*: use hwm5_conf.h for HWM setup ...................................................................... superio/winbond/w83627*: use hwm5_conf.h for HWM setup Change-Id: Id78042606f02e02035dc917d162d0c98c9de38a4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/35862/1 diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 88fbc31..85e3250 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> +#include <superio/hwm5_conf.h> #include <console/console.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> @@ -65,12 +66,12 @@ for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { reg = hwm_reg_values[i]; - value = pnp_read_index(base, reg); + value = pnp_read_hwm5_index(base, reg); value &= 0xff & (~(hwm_reg_values[i + 1])); value |= 0xff & hwm_reg_values[i + 2]; printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, " "value = 0x%02x\n", base, reg, value); - pnp_write_index(base, reg, value); + pnp_write_hwm5_index(base, reg, value); } } @@ -87,8 +88,7 @@ break; case W83627EHG_HWM: res0 = find_resource(dev, PNP_IDX_IO0); -#define HWM_INDEX_PORT 5 - init_hwm(res0->base + HWM_INDEX_PORT); + init_hwm(res0->base); break; case W83627EHG_ACPI: init_acpi(dev); diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 318eaa4..54120fb 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> +#include <superio/hwm5_conf.h> #include <console/console.h> #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> @@ -72,12 +73,12 @@ for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { reg = hwm_reg_values[i]; - value = pnp_read_index(base, reg); + value = pnp_read_hwm5_index(base, reg); value &= 0xff & hwm_reg_values[i + 1]; value |= 0xff & hwm_reg_values[i + 2]; printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, " "value = 0x%02x\n", base, reg, value); - pnp_write_index(base, reg, value); + pnp_write_hwm5_index(base, reg, value); } } @@ -94,8 +95,7 @@ break; case W83627HF_HWM: res0 = find_resource(dev, PNP_IDX_IO0); -#define HWM_INDEX_PORT 5 - init_hwm(res0->base + HWM_INDEX_PORT); + init_hwm(res0->base); break; case W83627HF_ACPI: init_acpi(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/35862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id78042606f02e02035dc917d162d0c98c9de38a4 Gerrit-Change-Number: 35862 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: intel/dcp847ske: use functions from hwm5_conf.h for HWM setup
by Felix Held (Code Review) 08 Oct '19

08 Oct '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35861 ) Change subject: intel/dcp847ske: use functions from hwm5_conf.h for HWM setup ...................................................................... intel/dcp847ske: use functions from hwm5_conf.h for HWM setup Change-Id: I67de5260a756fc7b1cf0ec1903bee0058a2dcb06 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/intel/dcp847ske/superio.h 1 file changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35861/1 diff --git a/src/mainboard/intel/dcp847ske/superio.h b/src/mainboard/intel/dcp847ske/superio.h index 56938e7..6f74d3e 100644 --- a/src/mainboard/intel/dcp847ske/superio.h +++ b/src/mainboard/intel/dcp847ske/superio.h @@ -18,6 +18,7 @@ #define DCP847SKE_SUPERIO_H #include <arch/io.h> +#include <superio/hwm5_conf.h> #define NUVOTON_PORT 0x4e #define HWM_PORT 0x0a30 @@ -44,11 +45,6 @@ #define SUPERIO_WRITE_INITVAL(val) SUPERIO_WRITE((val) >> 8, (val) & 0xff) -#define HWM_WRITE(reg, data) do { \ - outb((reg), HWM_PORT + 5); \ - outb((data), HWM_PORT + 6); \ -} while (0) - -#define HWM_WRITE_INITVAL(val) HWM_WRITE((val) >> 8, (val) & 0xff) +#define HWM_WRITE_INITVAL(val) pnp_write_hwm5_index(HWM_PORT, (val) >> 8, (val) & 0xff) #endif /* DCP847SKE_SUPERIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67de5260a756fc7b1cf0ec1903bee0058a2dcb06 Gerrit-Change-Number: 35861 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: superio/it8772f: use HWM access functionality from hwm5_conf.h
by Felix Held (Code Review) 08 Oct '19

08 Oct '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35859 ) Change subject: superio/it8772f: use HWM access functionality from hwm5_conf.h ...................................................................... superio/it8772f: use HWM access functionality from hwm5_conf.h Change-Id: I12ac8dd0503f3c46fdb50e49df60c01387128b55 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/ite/it8772f/superio.c 1 file changed, 26 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/35859/1 diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index ed46e73..4d9ea71 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -22,21 +22,12 @@ #include <delay.h> #include <stdlib.h> #include <superio/conf_mode.h> +#include <superio/hwm5_conf.h> #include "chip.h" /* FIXME */ #include "it8772f.h" -static inline u8 it8772f_envc_read(struct resource *res, u8 addr) -{ - outb(addr, res->base + 5); - return inb(res->base + 6); -} - -static inline void it8772f_envc_write(struct resource *res, u8 addr, u8 value) -{ - outb(addr, res->base + 5); - outb(value, res->base + 6); -} +/* FIXME: see if the common ITE environment controller code can be used here */ static void it8772f_extemp_force_idle_status(struct resource *res) { @@ -45,7 +36,7 @@ /* Wait up to 10ms for non-busy state. */ while (retries > 0) { - reg = it8772f_envc_read(res, IT8772F_EXTEMP_STATUS); + reg = pnp_read_hwm5_index(res->base, IT8772F_EXTEMP_STATUS); if ((reg & IT8772F_EXTEMP_STATUS_HOST_BUSY) == 0x0) break; @@ -60,7 +51,7 @@ * SIO is busy due to unfinished peci transaction. * Re-configure Register 0x8E to terminate processes. */ - it8772f_envc_write(res, IT8772F_EXTEMP_CONTROL, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_CONTROL, IT8772F_EXTEMP_CONTROL_AUTO_4HZ | IT8772F_EXTEMP_CONTROL_AUTO_START); } @@ -75,25 +66,25 @@ return; /* Enable PECI interface */ - it8772f_envc_write(res, IT8772F_INTERFACE_SELECT, + pnp_write_hwm5_index(res->base, IT8772F_INTERFACE_SELECT, IT8772F_INTERFACE_SEL_PECI | IT8772F_INTERFACE_SPEED_TOLERANCE); /* Setup External Temperature using PECI GetTemp */ - it8772f_envc_write(res, IT8772F_EXTEMP_ADDRESS, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_ADDRESS, PECI_CLIENT_ADDRESS); - it8772f_envc_write(res, IT8772F_EXTEMP_COMMAND, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_COMMAND, PECI_GETTEMP_COMMAND); - it8772f_envc_write(res, IT8772F_EXTEMP_WRITE_LENGTH, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_WRITE_LENGTH, PECI_GETTEMP_WRITE_LENGTH); - it8772f_envc_write(res, IT8772F_EXTEMP_READ_LENGTH, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_READ_LENGTH, PECI_GETTEMP_READ_LENGTH); - it8772f_envc_write(res, IT8772F_EXTEMP_CONTROL, + pnp_write_hwm5_index(res->base, IT8772F_EXTEMP_CONTROL, IT8772F_EXTEMP_CONTROL_AUTO_4HZ | IT8772F_EXTEMP_CONTROL_AUTO_START); /* External Temperature reported in TMPINx register */ - it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, (tmpin & 3) << 6); } @@ -109,17 +100,17 @@ if (tmpin != 1 && tmpin != 2) return; - reg = it8772f_envc_read(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE); + reg = pnp_read_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE); switch (mode) { case THERMAL_DIODE: /* Thermal Diode Mode */ - it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, reg | tmpin); break; case THERMAL_RESISTOR: /* Thermal Resistor Mode */ - it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + pnp_write_hwm5_index(res->base, IT8772F_ADC_TEMP_CHANNEL_ENABLE, reg | (tmpin << 3)); break; default: @@ -128,10 +119,10 @@ return; } - reg = it8772f_envc_read(res, IT8772F_CONFIGURATION); + reg = pnp_read_hwm5_index(res->base, IT8772F_CONFIGURATION); /* Enable the startup of monitoring operation */ - it8772f_envc_write(res, IT8772F_CONFIGURATION, reg | 0x01); + pnp_write_hwm5_index(res->base, IT8772F_CONFIGURATION, reg | 0x01); } /* @@ -145,41 +136,41 @@ return; /* Enable 6MHz (23.43kHz PWM) active high output */ - reg = it8772f_envc_read(res, IT8772F_FAN_CTL_MODE); + reg = pnp_read_hwm5_index(res->base, IT8772F_FAN_CTL_MODE); reg |= IT8772F_FAN_CTL_ON(fan) | IT8772F_FAN_PWM_CLOCK_6MHZ | IT8772F_FAN_CTL_POLARITY_HIGH; - it8772f_envc_write(res, IT8772F_FAN_CTL_MODE, reg); + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL_MODE, reg); /* Enable output in smart mode */ - reg = it8772f_envc_read(res, IT8772F_FAN_MAIN_CTL); + reg = pnp_read_hwm5_index(res->base, IT8772F_FAN_MAIN_CTL); reg |= IT8772F_FAN_MAIN_CTL_TAC_SMART(fan); reg |= IT8772F_FAN_MAIN_CTL_TAC_EN(fan); - it8772f_envc_write(res, IT8772F_FAN_MAIN_CTL, reg); + pnp_write_hwm5_index(res->base, IT8772F_FAN_MAIN_CTL, reg); switch (fan) { case 2: /* Enable software operation */ - it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_MODE, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_PWM_MODE, IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); /* Disable Smoothing */ - it8772f_envc_write(res, IT8772F_FAN_CTL2_AUTO_MODE, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_AUTO_MODE, IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); /* Set a default fan speed */ if (fan_speed) - it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_START, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL2_PWM_START, fan_speed); break; case 3: /* Enable software operation */ - it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_MODE, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_PWM_MODE, IT8772F_FAN_CTL_PWM_MODE_SOFTWARE); /* Disable Smoothing */ - it8772f_envc_write(res, IT8772F_FAN_CTL3_AUTO_MODE, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_AUTO_MODE, IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); /* Set a default fan speed */ if (fan_speed) - it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_START, + pnp_write_hwm5_index(res->base, IT8772F_FAN_CTL3_PWM_START, fan_speed); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12ac8dd0503f3c46fdb50e49df60c01387128b55 Gerrit-Change-Number: 35859 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: superio/hwm5_conf: factor out HWM access from ITE env_ctrl
by Felix Held (Code Review) 08 Oct '19

08 Oct '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35858 ) Change subject: superio/hwm5_conf: factor out HWM access from ITE env_ctrl ...................................................................... superio/hwm5_conf: factor out HWM access from ITE env_ctrl Nuvoton and Winbond use the same off-by-5 indirect address space to access their hardware monitor/environment controller in the SIO chip, so move this to a common location and replace the inb/outb calls with the corresponding inline functions from device/pnp.h Change-Id: I20606313d0cc9cf74be7dca30bc4550059125fe1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/include/superio/hwm5_conf.h M src/superio/ite/common/env_ctrl.c 2 files changed, 109 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/35858/1 diff --git a/src/include/superio/hwm5_conf.h b/src/include/superio/hwm5_conf.h new file mode 100644 index 0000000..bfec0fd --- /dev/null +++ b/src/include/superio/hwm5_conf.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DEVICE_PNP_HWM5_CONF_H +#define DEVICE_PNP_HWM5_CONF_H + +#include <device/pnp.h> + +/* The address/data register pair for the indirect/indexed IO space of the + * hardware monitor (HWM) that does temperature and voltage sensing and fan + * control in ITE, Nuvoton and Winbond super IO chips aren't at offset 0 and 1 + * of the corresponding IO address region, but at offset 5 and 6. */ + +/* + * u8 pnp_read_hwm5_index(u16 port, u8 reg) + * Description: + * This routine reads indexed I/O registers. The reg byte is written + * to the index register at I/O address = port + 5. The result is then + * read from the data register at I/O address = port + 6. + * + * Parameters: + * @param[in] u16 base = The I/O address of the port index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[out] u8 result = The value read back from the data register. + */ +static inline u8 pnp_read_hwm5_index(u16 base, u8 reg) +{ + return pnp_read_index(base + 5, reg); +} + +/* + * void pnp_write_hwm5_index(u16 port, u8 reg, u8 value) + * Description: + * This routine writes indexed I/O registers. The reg byte is written + * to the index register at I/O address = port + 5. The value byte is then + * written to the data register at I/O address = port + 6. + * + * Parameters: + * @param[in] u16 base = The address of the port index register. + * @param[in] u8 reg = The offset within the indexed space. + * @param[in] u8 value = The value to be written to the data register. + */ +static inline void pnp_write_hwm5_index(u16 base, u8 reg, u8 value) +{ + pnp_write_index(base + 5, reg, value); +} + +#endif /* DEVICE_PNP_HWM5_CONF_H */ diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1b93036..2f2942b 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -21,22 +21,11 @@ #include <arch/io.h> #include <console/console.h> #include <delay.h> +#include <superio/hwm5_conf.h> #include "env_ctrl.h" #include "env_ctrl_chip.h" -static inline u8 ite_ec_read(const u16 base, const u8 addr) -{ - outb(addr, base + 5); - return inb(base + 6); -} - -static inline void ite_ec_write(const u16 base, const u8 addr, const u8 value) -{ - outb(addr, base + 5); - outb(value, base + 6); -} - static void extemp_force_idle_status(const u16 base) { u8 reg; @@ -44,7 +33,7 @@ /* Wait up to 10ms for non-busy state. */ while (retries > 0) { - reg = ite_ec_read(base, ITE_EC_EXTEMP_STATUS); + reg = pnp_read_hwm5_index(base, ITE_EC_EXTEMP_STATUS); if ((reg & ITE_EC_EXTEMP_STATUS_HOST_BUSY) == 0x0) break; @@ -59,9 +48,8 @@ * SIO is busy due to unfinished peci transaction. * Re-configure Register 0x8E to terminate processes. */ - ite_ec_write(base, ITE_EC_EXTEMP_CONTROL, - ITE_EC_EXTEMP_CTRL_AUTO_4HZ | - ITE_EC_EXTEMP_CTRL_AUTO_START); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_CONTROL, + ITE_EC_EXTEMP_CTRL_AUTO_4HZ | ITE_EC_EXTEMP_CTRL_AUTO_START); } } @@ -71,22 +59,16 @@ static void enable_peci(const u16 base) { /* Enable PECI interface */ - ite_ec_write(base, ITE_EC_INTERFACE_SELECT, - ITE_EC_INTERFACE_SEL_PECI | - ITE_EC_INTERFACE_SPEED_TOLERANCE); + pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, + ITE_EC_INTERFACE_SEL_PECI | ITE_EC_INTERFACE_SPEED_TOLERANCE); /* Setup External Temperature using PECI GetTemp */ - ite_ec_write(base, ITE_EC_EXTEMP_ADDRESS, - PECI_CLIENT_ADDRESS); - ite_ec_write(base, ITE_EC_EXTEMP_COMMAND, - PECI_GETTEMP_COMMAND); - ite_ec_write(base, ITE_EC_EXTEMP_WRITE_LENGTH, - PECI_GETTEMP_WRITE_LENGTH); - ite_ec_write(base, ITE_EC_EXTEMP_READ_LENGTH, - PECI_GETTEMP_READ_LENGTH); - ite_ec_write(base, ITE_EC_EXTEMP_CONTROL, - ITE_EC_EXTEMP_CTRL_AUTO_4HZ | - ITE_EC_EXTEMP_CTRL_AUTO_START); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_ADDRESS, PECI_CLIENT_ADDRESS); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_COMMAND, PECI_GETTEMP_COMMAND); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_WRITE_LENGTH, PECI_GETTEMP_WRITE_LENGTH); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_READ_LENGTH, PECI_GETTEMP_READ_LENGTH); + pnp_write_hwm5_index(base, ITE_EC_EXTEMP_CONTROL, + ITE_EC_EXTEMP_CTRL_AUTO_4HZ | ITE_EC_EXTEMP_CTRL_AUTO_START); } /* @@ -98,7 +80,7 @@ { u8 reg; - reg = ite_ec_read(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE); + reg = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE); switch (conf->mode) { case THERMAL_PECI: @@ -122,26 +104,25 @@ return; } - ite_ec_write(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg); /* Set temperature offsets */ if (conf->mode != THERMAL_RESISTOR) { - reg = ite_ec_read(base, ITE_EC_BEEP_ENABLE); + reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; - ite_ec_write(base, ITE_EC_BEEP_ENABLE, reg); - ite_ec_write(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); + pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); } /* Set temperature limits */ u8 max = conf->max; - ite_ec_write(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), - max ? max : 127); - ite_ec_write(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min); + pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), max ? max : 127); + pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min); /* Enable the startup of monitoring operation */ - reg = ite_ec_read(base, ITE_EC_CONFIGURATION); + reg = pnp_read_hwm5_index(base, ITE_EC_CONFIGURATION); reg |= ITE_EC_CONFIGURATION_START; - ite_ec_write(base, ITE_EC_CONFIGURATION, reg); + pnp_write_hwm5_index(base, ITE_EC_CONFIGURATION, reg); } static void fan_smartconfig(const u16 base, const u8 fan, @@ -177,20 +158,19 @@ if (conf->smoothing) pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN; - ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(fan), - conf->tmp_off); - ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_START(fan), - conf->tmp_start); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(fan), conf->tmp_off); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_START(fan), + conf->tmp_start); /* Full speed above 127°C by default */ - ite_ec_write(base, ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(fan), - conf->tmp_full ? conf->tmp_full : 127); - ite_ec_write(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan), - ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta)); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(fan), + conf->tmp_full ? conf->tmp_full : 127); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan), + ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta)); } - ite_ec_write(base, ITE_EC_FAN_CTL_PWM_CONTROL(fan), pwm_ctrl); - ite_ec_write(base, ITE_EC_FAN_CTL_PWM_START(fan), pwm_start); - ite_ec_write(base, ITE_EC_FAN_CTL_PWM_AUTO(fan), pwm_auto); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_CONTROL(fan), pwm_ctrl); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_START(fan), pwm_start); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_AUTO(fan), pwm_auto); } static void enable_fan(const u16 base, const u8 fan, @@ -205,39 +185,39 @@ /* FAN_CTL2 might have its own frequency setting */ if (CONFIG(SUPERIO_ITE_ENV_CTRL_PWM_FREQ2) && fan == 2) { - reg = ite_ec_read(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE); + reg = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE); reg &= ~ITE_EC_FAN_PWM_CLOCK_MASK; reg |= ITE_EC_FAN_PWM_DEFAULT_CLOCK; - ite_ec_write(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE, reg); } if (conf->mode >= FAN_SMART_SOFTWARE) { fan_smartconfig(base, fan, conf->mode, &conf->smart); } else { - reg = ite_ec_read(base, ITE_EC_FAN_CTL_MODE); + reg = pnp_read_hwm5_index(base, ITE_EC_FAN_CTL_MODE); if (conf->mode == FAN_MODE_ON) reg |= ITE_EC_FAN_CTL_ON(fan); else reg &= ~ITE_EC_FAN_CTL_ON(fan); - ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, reg); } if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) { - reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); + reg = pnp_read_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); - ite_ec_write(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg); } if (CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) && fan > 3) { - reg = ite_ec_read(base, ITE_EC_FAN_SEC_CTL); + reg = pnp_read_hwm5_index(base, ITE_EC_FAN_SEC_CTL); if (conf->mode >= FAN_MODE_ON) reg |= ITE_EC_FAN_SEC_CTL_TAC_EN(fan); else reg &= ~ITE_EC_FAN_SEC_CTL_TAC_EN(fan); - ite_ec_write(base, ITE_EC_FAN_SEC_CTL, reg); + pnp_write_hwm5_index(base, ITE_EC_FAN_SEC_CTL, reg); } else { - reg = ite_ec_read(base, ITE_EC_FAN_MAIN_CTL); + reg = pnp_read_hwm5_index(base, ITE_EC_FAN_MAIN_CTL); if (conf->mode >= FAN_MODE_ON) reg |= ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); else @@ -250,7 +230,7 @@ else reg &= ~ITE_EC_FAN_MAIN_CTL_SMART(fan); } - ite_ec_write(base, ITE_EC_FAN_MAIN_CTL, reg); + pnp_write_hwm5_index(base, ITE_EC_FAN_MAIN_CTL, reg); } } @@ -261,20 +241,20 @@ if (conf->tmpin_beep) { reg |= ITE_EC_BEEP_ON_TMP_LIMIT; - ite_ec_write(base, ITE_EC_BEEP_FREQ_DIV_OF_TMPIN, freq); + pnp_write_hwm5_index(base, ITE_EC_BEEP_FREQ_DIV_OF_TMPIN, freq); } if (conf->fan_beep) { reg |= ITE_EC_BEEP_ON_FAN_LIMIT; - ite_ec_write(base, ITE_EC_BEEP_FREQ_DIV_OF_FAN, freq); + pnp_write_hwm5_index(base, ITE_EC_BEEP_FREQ_DIV_OF_FAN, freq); } if (conf->vin_beep) { reg |= ITE_EC_BEEP_ON_VIN_LIMIT; - ite_ec_write(base, ITE_EC_BEEP_FREQ_DIV_OF_VIN, freq); + pnp_write_hwm5_index(base, ITE_EC_BEEP_FREQ_DIV_OF_VIN, freq); } if (reg) { - reg |= ite_ec_read(base, ITE_EC_BEEP_ENABLE); - ite_ec_write(base, ITE_EC_BEEP_ENABLE, reg); + reg |= pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); + pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); } } @@ -283,11 +263,11 @@ size_t i; /* Configure 23.43kHz PWM active high output */ - u8 fan_ctl = ite_ec_read(base, ITE_EC_FAN_CTL_MODE); + u8 fan_ctl = pnp_read_hwm5_index(base, ITE_EC_FAN_CTL_MODE); fan_ctl &= ~ITE_EC_FAN_PWM_CLOCK_MASK; fan_ctl |= ITE_EC_FAN_PWM_DEFAULT_CLOCK; fan_ctl |= ITE_EC_FAN_CTL_POLARITY_HIGH; - ite_ec_write(base, ITE_EC_FAN_CTL_MODE, fan_ctl); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, fan_ctl); /* Enable HWM if configured */ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) @@ -295,13 +275,13 @@ /* Enable External Sensor SMBus Host if configured */ if (conf->smbus_en) { - ite_ec_write(base, ITE_EC_INTERFACE_SELECT, - ite_ec_read(base, ITE_EC_INTERFACE_SELECT) | + pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, + pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) | ITE_EC_INTERFACE_SMB_ENABLE); } /* Enable reading of voltage pins */ - ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); + pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); /* Enable FANx if configured */ for (i = 0; i < ITE_EC_FAN_CNT; ++i) -- To view, visit https://review.coreboot.org/c/coreboot/+/35858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20606313d0cc9cf74be7dca30bc4550059125fe1 Gerrit-Change-Number: 35858 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Philip Chen (Code Review) 08 Oct '19

08 Oct '19

Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 2: Code-Review+1 > Patch Set 2: > > > Patch Set 2: > > > > (1 comment) > > Set 0 means set null . It will make passive setting disabled by filled value 0 . OK, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 08 Oct 2019 17:28:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK
by mturney mturney (Code Review) 08 Oct '19

08 Oct '19

1 0

Change in coreboot[master]: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK
by mturney mturney (Code Review) 08 Oct '19

08 Oct '19

mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35896 ) Change subject: HACK sc7180: bootblock/verstage/romstage need to zero bss HACK ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35896/1//COMMIT_MSG@8 PS1, Line 8: > Could you please provide the reasoning here as to why this is needed? As indicated this is a HACK patch and not expected to be reviewed. To your question, I have been trying to get the chroot build environment working for Trogdor and it behaves differently than the standalone environment we have been working with. In this context, standalone refers to the "normal" coreboot build environment and chroot refers to the chromium chroot build environment. To get a headstart on trogdor development we have been building/testing code using standalone build environment. Same patch-train builds in chroot environment but doesn't get out of bootblock. Symptom is bss sections are not initialized to 0, hence these patches. The changes were introduced one at a time, the bootblock.c change allowed code to reach verstage and go no further. The verstage.c change allowed code to reach romstage. Even with these HACK workarounds we can't get out of qclib, which is started by romstage, so the test stops here. Even with these workarounds, there are other subtle issues, e.g. the console log messages in verstage and romstage are truncated, from what is seen with the standalone build. I intend to create a buganizer ticket and attach console log output, etc. This patch was pushed upstream to share with Julius and other googlers who may have some insight into why the chroot build appears broken while the standalone build allows boot to kernel login prompt. -- To view, visit https://review.coreboot.org/c/coreboot/+/35896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafe0ccfb776b8150f547cb691e082c206f80a8fc Gerrit-Change-Number: 35896 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 08 Oct 2019 17:09:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2019