coreboot-gerrit October 2019

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Change in ...coreboot[master]: device/root_device: Consolidate common _scan_bus() functions
by Nico Huber (Code Review) 08 Oct '19

08 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31901 Change subject: device/root_device: Consolidate common _scan_bus() functions ...................................................................... device/root_device: Consolidate common _scan_bus() functions scan_usb_bus() and root_dev_scan_bus() had the very same implementation. So rename the latter to scan_static_bus() and use that for both cases. Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/root_device.c M src/drivers/usb/acpi/usb_acpi.c M src/include/device/device.h M src/soc/amd/stoneyridge/usb.c M src/soc/intel/common/block/xhci/xhci.c 5 files changed, 6 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31901/1 diff --git a/src/device/root_device.c b/src/device/root_device.c index 8f2d446..2fae5c3 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -72,21 +72,6 @@ printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); } -void scan_usb_bus(struct device *bus) -{ - struct bus *link; - - printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - - enable_static_devices(bus); - - /* Scan bridges in case this device is a hub */ - for (link = bus->link_list; link; link = link->next) - scan_bridges(link); - - printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); -} - void scan_generic_bus(struct device *bus) { struct device *child; @@ -123,14 +108,7 @@ scan_generic_bus(bus); } -/** - * Scan root bus for generic systems. - * - * This function is the default scan_bus() method of the root device. - * - * @param root The root device structure. - */ -static void root_dev_scan_bus(struct device *bus) +void scan_static_bus(struct device *bus) { struct bus *link; @@ -169,7 +147,7 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = root_dev_scan_bus, + .scan_bus = scan_static_bus, .reset_bus = root_dev_reset, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = root_dev_acpi_name, diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 8c63d2a..e026eeb 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -86,7 +86,7 @@ .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .scan_bus = scan_usb_bus, + .scan_bus = scan_static_bus, .acpi_fill_ssdt_generator = usb_acpi_fill_ssdt_generator, }; diff --git a/src/include/device/device.h b/src/include/device/device.h index cbee197..02fb072 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -282,7 +282,7 @@ void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); void scan_lpc_bus(struct device *bus); -void scan_usb_bus(struct device *bus); +void scan_static_bus(struct device *bus); #endif /* !defined(__ROMCC__) */ diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index f2fa3ba..2eedd97 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -63,7 +63,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = set_usb_over_current, - .scan_bus = scan_usb_bus, + .scan_bus = scan_static_bus, .acpi_name = soc_acpi_name, .ops_pci = &lops_pci, }; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index c429e7d..95315b2 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -28,7 +28,7 @@ .enable_resources = pci_dev_enable_resources, .init = soc_xhci_init, .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_usb_bus, + .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679 Gerrit-Change-Number: 31901 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell_de: Define and use MMCONF_BUS_NUMBER
by build bot (Jenkins) (Code Review) 08 Oct '19

08 Oct '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35878 ) Change subject: soc/intel/broadwell_de: Define and use MMCONF_BUS_NUMBER ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/35878/4/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/acpi.c: https://review.coreboot.org/c/coreboot/+/35878/4/src/soc/intel/fsp_broadwel… PS4, Line 150: MCFG_BASE_ADDRESS, 0, 0, code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/35878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f08f3ecb97793b5ee150ca246b80f3503f4cfa Gerrit-Change-Number: 35878 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 08 Oct 2019 12:33:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Use common Kconfig symbols for PCIE config space size
by Arthur Heymans (Code Review) 08 Oct '19

08 Oct '19

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35877 to look at the new patch set (#4). Change subject: soc/intel: Use common Kconfig symbols for PCIE config space size ...................................................................... soc/intel: Use common Kconfig symbols for PCIE config space size PCIe mmconf is not INTEL_SA specific, therefore use the common CONFIG_MMCONF_BUS_NUMBER. Change-Id: I179e6c4e84664c7a7581e6103cfc079eb5c449f5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/systemagent.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/systemagent.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/systemagent.c 12 files changed, 32 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35877/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/35877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I179e6c4e84664c7a7581e6103cfc079eb5c449f5 Gerrit-Change-Number: 35877 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device: Use scan_static_bus() over scan_lpc_bus()
by Felix Held (Code Review) 08 Oct '19

08 Oct '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29474 ) Change subject: device: Use scan_static_bus() over scan_lpc_bus() ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Gerrit-Change-Number: 29474 Gerrit-PatchSet: 10 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 08 Oct 2019 11:41:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Don't allow separate verstage to boot from romcc bootblock
by Arthur Heymans (Code Review) 08 Oct '19

08 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35824 ) Change subject: arch/x86: Don't allow separate verstage to boot from romcc bootblock ...................................................................... arch/x86: Don't allow separate verstage to boot from romcc bootblock This is currently unused. Change-Id: I8f963a27f9023fd4c6ebc418059d57e00e4dfb4c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/bootblock_simple.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35824/1 diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c index fc041c8..d161435 100644 --- a/src/arch/x86/bootblock_simple.c +++ b/src/arch/x86/bootblock_simple.c @@ -27,12 +27,7 @@ #endif } -#if CONFIG(VBOOT_SEPARATE_VERSTAGE) - const char *target1 = "fallback/verstage"; -#else const char *target1 = "fallback/romstage"; -#endif - unsigned long entry; entry = findstage(target1); if (entry) -- To view, visit https://review.coreboot.org/c/coreboot/+/35824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f963a27f9023fd4c6ebc418059d57e00e4dfb4c Gerrit-Change-Number: 35824 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC]arch/x86: Only allow normal and fallback prefix
by Arthur Heymans (Code Review) 08 Oct '19

08 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35822 ) Change subject: [RFC]arch/x86: Only allow normal and fallback prefix ...................................................................... [RFC]arch/x86: Only allow normal and fallback prefix Remove the functionality to use other prefixes which requires a coreboot-stages cbfs file. Specifying the stage prefix in Kconfig and making a properly formatted coreboot-stages cbfs file is errorprone, so get rid of the functionality assuming it's mostly unused. Change-Id: I04222120bd1241c3b0996afa27dcc35ac42fbbc8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig M src/arch/x86/bootblock_normal.c 2 files changed, 20 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35822/1 diff --git a/src/Kconfig b/src/Kconfig index 8fcb3ae..baf406f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -37,12 +37,26 @@ help Select this to prompt to use to configure the prefix for cbfs files. +choice + prompt "CBFS prefix to use" + depends on CONFIGURABLE_CBFS_PREFIX + default CBFS_PREFIX_FALLBACK + +config CBFS_PREFIX_FALLBACK + bool "fallback" + +config CBFS_PREFIX_NORMAL + bool "normal" + +endchoice + config CBFS_PREFIX - string "CBFS prefix to use" if CONFIGURABLE_CBFS_PREFIX - default "fallback" + string + default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK + default "normal" if CBFS_PREFIX_NORMAL help Select the prefix to all files put into the image. It's "fallback" - by default, "normal" is a common alternative. + by default, "normal" is the alternative. choice prompt "Compiler to use" diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index 905ecb2..9cc99f7 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -26,7 +26,7 @@ static void main(unsigned long bist) { u8 boot_mode; - const char *default_filenames = + const char *romstage_filenames = "normal/romstage\0fallback/romstage"; if (boot_cpu()) { @@ -44,20 +44,15 @@ boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); } - char *normal_candidate = (char *)walkcbfs("coreboot-stages"); - - if (!normal_candidate) - normal_candidate = default_filenames; - unsigned long entry; if (boot_mode) { - entry = findstage(normal_candidate); + entry = findstage(romstage_filenames); if (entry) call(entry, bist); } - entry = findstage(get_fallback(normal_candidate)); + entry = findstage(get_fallback(romstage_filenames)); if (entry) call(entry, bist); -- To view, visit https://review.coreboot.org/c/coreboot/+/35822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04222120bd1241c3b0996afa27dcc35ac42fbbc8 Gerrit-Change-Number: 35822 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Use common Kconfig symbols for PCIE config space size
by Arthur Heymans (Code Review) 08 Oct '19

08 Oct '19

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35877 to look at the new patch set (#3). Change subject: soc/intel: Use common Kconfig symbols for PCIE config space size ...................................................................... soc/intel: Use common Kconfig symbols for PCIE config space size PCIe mmconf is not INTEL_SA specific, therefore use the common CONFIG_MMCONF_BUS_NUMBER. Change-Id: I179e6c4e84664c7a7581e6103cfc079eb5c449f5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/systemagent.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/systemagent.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/systemagent.c 12 files changed, 32 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35877/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/35877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I179e6c4e84664c7a7581e6103cfc079eb5c449f5 Gerrit-Change-Number: 35877 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/device/dram/ddr4: Fix "Dead assignment"
by HAOUAS Elyes (Code Review) 08 Oct '19

08 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35558 ) Change subject: src/device/dram/ddr4: Fix "Dead assignment" ...................................................................... src/device/dram/ddr4: Fix "Dead assignment" The value stored to 'spd_bytes_total' is never read, so let use it to check if 'SPD Bytes Total' and/or 'SPD Bytes Used' are reserved. Change-Id: I426a7e64cc4c0bcced91d03387e02c8d965a21dc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr4.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/35558/1 diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 4f99ecc..472a771 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -120,6 +120,13 @@ } spd_bytes_total = 256 << (spd_bytes_total - 1); + + if (spd_bytes_total > 512) + printk(BIOS_WARNING, "SPD Bytes Total value is reserved\n"); + + if (spd_bytes_used > 4) + printk(BIOS_WARNING, "SPD Bytes Used value is reserved\n"); + spd_bytes_used = spd_bytes_used_table[spd_bytes_used]; /* Verify CRC of blocks that have them, do not step over 'used' length */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I426a7e64cc4c0bcced91d03387e02c8d965a21dc Gerrit-Change-Number: 35558 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/spi: unify and refine VSCC handling
by Arthur Heymans (Code Review) 08 Oct '19

08 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28346 ) Change subject: sb/intel/spi: unify and refine VSCC handling ...................................................................... Patch Set 23: (1 comment) I'd like to get this merged. Still working on this, Stefan? https://review.coreboot.org/c/coreboot/+/28346/23//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/28346/23//COMMIT_MSG@23 PS23, Line 23: ICH9 also calls the function but has the SPI driver : not enabled yet so "only" gains the possibility to set it in the DT. This is now the case. -- To view, visit https://review.coreboot.org/c/coreboot/+/28346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27a9373f2402837682194e7097c6764851f1e5bd Gerrit-Change-Number: 28346 Gerrit-PatchSet: 23 Gerrit-Owner: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Oct 2019 10:58:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/spi: export a function to switch CS between flash chips
by Arthur Heymans (Code Review) 08 Oct '19

08 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28360 ) Change subject: sb/intel/spi: export a function to switch CS between flash chips ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/28360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e22aaee72f3e66c2a78d124287e1b225ec733aa Gerrit-Change-Number: 28360 Gerrit-PatchSet: 3 Gerrit-Owner: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Oct 2019 10:54:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2019