coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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1921 discussions

Change in ...coreboot[master]: device: Rename scan_static_bus() -> enable_static_devices()
by Nico Huber (Code Review) 07 Oct '19

07 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31900 Change subject: device: Rename scan_static_bus() -> enable_static_devices() ...................................................................... device: Rename scan_static_bus() -> enable_static_devices() The new name should reflect better what this function does, as that is only one specific step of the scanning. Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/root_device.c M src/include/device/device.h M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/hda/hda.c 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31900/1 diff --git a/src/device/root_device.c b/src/device/root_device.c index f8e2907..8f2d446 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -26,7 +26,7 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER; /** - * Scan devices on static buses. + * Enable devices on static buses. * * The enumeration of certain buses is purely static. The existence of * devices on those buses can be completely determined at compile time @@ -43,7 +43,7 @@ * @param bus Pointer to the device to which the static buses are attached to. */ -void scan_static_bus(struct device *bus) +void enable_static_devices(struct device *bus) { struct device *child; struct bus *link; @@ -67,7 +67,7 @@ { printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus); + enable_static_devices(bus); printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); } @@ -78,7 +78,7 @@ printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus); + enable_static_devices(bus); /* Scan bridges in case this device is a hub */ for (link = bus->link_list; link; link = link->next) @@ -136,7 +136,7 @@ printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - scan_static_bus(bus); + enable_static_devices(bus); for (link = bus->link_list; link; link = link->next) scan_bridges(link); diff --git a/src/include/device/device.h b/src/include/device/device.h index 2e2cda9..cbee197 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -278,9 +278,9 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); +void enable_static_devices(struct device *bus); void scan_smbus(struct device *bus); void scan_generic_bus(struct device *bus); -void scan_static_bus(struct device *bus); void scan_lpc_bus(struct device *bus); void scan_usb_bus(struct device *bus); diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 2bd6599..7f7eb90 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -23,7 +23,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_static_bus, + .scan_bus = enable_static_devices, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 8ab835e..c1426e0 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -69,7 +69,7 @@ .init = hda_init, #endif .ops_pci = &pci_dev_ops_pci, - .scan_bus = scan_static_bus, + .scan_bus = enable_static_devices, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/31900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5 Gerrit-Change-Number: 31900 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant board of T60
by Maciej Matuszczyk (Code Review) 07 Oct '19

07 Oct '19

Maciej Matuszczyk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35863 ) Change subject: mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant board of T60 ...................................................................... mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant board of T60 Add ThinkPad R60 support, only tested on unit with Intel GPU, now as variant board of ThinkPad T60. - It can be 100 % Open Source. - Untested on boards with external Radeon graphics adapter. - Some columns on the left-most side of display are completely black on 1400x1050 IPS display[1]. Display works fine on Linux. I don't why it appears like that. - Only GRUB2 and SeaBIOS payloads tested for now. - 2504 docking station USB doesn't work under Linux. Can detect pendrive in GRUB2 payload. - Sometimes it takes 20s of "pretending it's powered off" to run coreboot code. Issue is payload agnostic. Might be fact that my unit is missing one of power line filtering capacitors. Image of issue with the screen: [1] https://imgur.com/a/0wpMGsm Change-Id: I1eb0b2647beeb21362d494b106c6c6a3c5fafa9e Signed-off-by: Maciej Matuszczuk <maccraft123mc(a)gmail.com> --- M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/t60/Kconfig.name M src/mainboard/lenovo/t60/board_info.txt A src/mainboard/lenovo/t60/variants/r60/board_info.txt A src/mainboard/lenovo/t60/variants/r60/gpio.c A src/mainboard/lenovo/t60/variants/t60/board_info.txt A src/mainboard/lenovo/t60/variants/t60/gpio.c 7 files changed, 368 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/35863/1 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index e4e87c9..81c2e1f 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_T60 +if BOARD_LENOVO_T60 || BOARD_LENOVO_R60 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -24,13 +24,23 @@ select I945_LVDS select INTEL_GMA_HAVE_VBT +config VARIANT_DIR + string + default "t60" if BOARD_LENOVO_T60 + default "r60" if BOARD_LENOVO_R60 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + config MAINBOARD_DIR string default lenovo/t60 config MAINBOARD_PART_NUMBER string - default "ThinkPad T60" + default "ThinkPad T60" if BOARD_LENOVO_T60 + default "ThinkPad R60" if BOARD_LENOVO_R60 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t60/Kconfig.name b/src/mainboard/lenovo/t60/Kconfig.name index f02fc3d..408c693 100644 --- a/src/mainboard/lenovo/t60/Kconfig.name +++ b/src/mainboard/lenovo/t60/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_T60 bool "ThinkPad T60 / T60p" + +config BOARD_LENOVO_R60 + bool "ThinkPad R60" diff --git a/src/mainboard/lenovo/t60/board_info.txt b/src/mainboard/lenovo/t60/board_info.txt index 59ec88c..0318ee4 100644 --- a/src/mainboard/lenovo/t60/board_info.txt +++ b/src/mainboard/lenovo/t60/board_info.txt @@ -1,4 +1,5 @@ -Board name: T60/T60p +Vendor name: Lenovo +Board name: T60/T60p/R60 baseboard Category: laptop ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/t60/variants/r60/board_info.txt b/src/mainboard/lenovo/t60/variants/r60/board_info.txt new file mode 100644 index 0000000..59ec88c --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/r60/board_info.txt @@ -0,0 +1,7 @@ +Board name: T60/T60p +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2006 diff --git a/src/mainboard/lenovo/t60/variants/r60/gpio.c b/src/mainboard/lenovo/t60/variants/r60/gpio.c new file mode 100644 index 0000000..f220b2b --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/r60/gpio.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, /* LEGACYIO# */ + .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */ + .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */ + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, /* MDI_DETECT */ + .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */ + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, /* CPUSB# */ + .gpio15 = GPIO_MODE_GPIO, /* CPPE# */ + .gpio19 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */ + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, /* EXC_PWR_CTRL */ + .gpio28 = GPIO_MODE_GPIO, /* EXC_AUX_CTRL */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio19 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /*PLANARID0 */ + .gpio37 = GPIO_MODE_GPIO, /*PLANARID1 */ + .gpio38 = GPIO_MODE_GPIO, /*PLANARID2 */ + .gpio39 = GPIO_MODE_GPIO, /*PLANARID3 */ + .gpio48 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio48 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/lenovo/t60/variants/t60/board_info.txt b/src/mainboard/lenovo/t60/variants/t60/board_info.txt new file mode 100644 index 0000000..b34244b --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/board_info.txt @@ -0,0 +1,7 @@ +Board name: R60 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2006 diff --git a/src/mainboard/lenovo/t60/variants/t60/gpio.c b/src/mainboard/lenovo/t60/variants/t60/gpio.c new file mode 100644 index 0000000..1f527b7 --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/gpio.c @@ -0,0 +1,225 @@ +/* + + * This file is part of the coreboot project. + + * + + * Copyright (C) 2019 Maciej Matuszczyk <maccraft123mc(a)gmail.com>. + + * + + * This program is free software; you can redistribute it and/or modify + + * it under the terms of the GNU General Public License as published by + + * the Free Software Foundation; version 2 of the License. + + * + + * This program is distributed in the hope that it will be useful, + + * but WITHOUT ANY WARRANTY; without even the implied warranty of + + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + + * GNU General Public License for more details. + + */ + + +#include <southbridge/intel/common/gpio.h> + + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + + .gpio1 = GPIO_MODE_GPIO, /* HDD_DTCT */ + + .gpio6 = GPIO_MODE_GPIO, /* LEGACYIO# */ + + .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */ + + .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */ + + .gpio9 = GPIO_MODE_GPIO, + + .gpio10 = GPIO_MODE_GPIO, /* MDI_DETECT */ + + .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */ + + .gpio13 = GPIO_MODE_GPIO, + + .gpio14 = GPIO_MODE_GPIO, /* CPUSB# */ + + .gpio15 = GPIO_MODE_GPIO, /* CPPE# */ + + .gpio19 = GPIO_MODE_GPIO, /* GBE_RST# */ + + .gpio21 = GPIO_MODE_GPIO, /* LCD_PRESENCE */ + + .gpio22 = GPIO_MODE_GPIO, /* FWH_WP */ + + .gpio24 = GPIO_MODE_GPIO, + + .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */ + + .gpio26 = GPIO_MODE_GPIO, + + .gpio27 = GPIO_MODE_GPIO, /* EXC_PWR_CTRL */ + + .gpio28 = GPIO_MODE_GPIO, /* EXC_AUX_CTRL */ + +}; + + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + + .gpio1 = GPIO_DIR_INPUT, + + .gpio6 = GPIO_DIR_INPUT, + + .gpio7 = GPIO_DIR_INPUT, + + .gpio8 = GPIO_DIR_INPUT, + + .gpio9 = GPIO_DIR_INPUT, + + .gpio10 = GPIO_DIR_INPUT, + + .gpio12 = GPIO_DIR_INPUT, + + .gpio13 = GPIO_DIR_INPUT, + + .gpio14 = GPIO_DIR_INPUT, + + .gpio15 = GPIO_DIR_INPUT, + + .gpio19 = GPIO_DIR_OUTPUT, + + .gpio21 = GPIO_DIR_INPUT, + + .gpio22 = GPIO_DIR_OUTPUT, + + .gpio24 = GPIO_DIR_OUTPUT, + + .gpio25 = GPIO_DIR_OUTPUT, + + .gpio26 = GPIO_DIR_OUTPUT, + + .gpio27 = GPIO_DIR_OUTPUT, + + .gpio28 = GPIO_DIR_OUTPUT, + +}; + + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + + .gpio19 = GPIO_LEVEL_HIGH, + + .gpio24 = GPIO_LEVEL_HIGH, + + .gpio25 = GPIO_LEVEL_HIGH, + + .gpio26 = GPIO_LEVEL_LOW, + + .gpio27 = GPIO_LEVEL_HIGH, + + .gpio28 = GPIO_LEVEL_HIGH, + +}; + + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + + .gpio1 = GPIO_INVERT, + + .gpio6 = GPIO_INVERT, + + .gpio7 = GPIO_INVERT, + + .gpio8 = GPIO_INVERT, + + .gpio12 = GPIO_INVERT, + + .gpio13 = GPIO_INVERT, + +}; + + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + +}; + + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + + .gpio34 = GPIO_MODE_GPIO, /* SMB_3B_EN */ + + .gpio36 = GPIO_MODE_GPIO, /*PLANARID0 */ + + .gpio37 = GPIO_MODE_GPIO, /*PLANARID1 */ + + .gpio38 = GPIO_MODE_GPIO, /*PLANARID2 */ + + .gpio39 = GPIO_MODE_GPIO, /*PLANARID3 */ + + .gpio48 = GPIO_MODE_GPIO, /* FWH_TBL */ + + +}; + + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + + .gpio34 = GPIO_DIR_INPUT, + + .gpio36 = GPIO_DIR_INPUT, + + .gpio37 = GPIO_DIR_INPUT, + + .gpio38 = GPIO_DIR_INPUT, + + .gpio39 = GPIO_DIR_INPUT, + + .gpio48 = GPIO_DIR_OUTPUT, + + +}; + + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + + .gpio33 = GPIO_LEVEL_LOW, + + .gpio35 = GPIO_LEVEL_HIGH, + + .gpio48 = GPIO_LEVEL_HIGH, + +}; + + +const struct pch_gpio_map mainboard_gpio_map = { + + .set1 = { + + .mode = &pch_gpio_set1_mode, + + .direction = &pch_gpio_set1_direction, + + .level = &pch_gpio_set1_level, + + .invert = &pch_gpio_set1_invert, + + }, + + .set2 = { + + .mode = &pch_gpio_set2_mode, + + .direction = &pch_gpio_set2_direction, + + .level = &pch_gpio_set2_level, + + }, + +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/35863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1eb0b2647beeb21362d494b106c6c6a3c5fafa9e Gerrit-Change-Number: 35863 Gerrit-PatchSet: 1 Gerrit-Owner: Maciej Matuszczyk <maccraft123mc(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: Use scan_static_bus() over scan_lpc_bus()
by Aaron Durbin (Code Review) 07 Oct '19

07 Oct '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29474 ) Change subject: device: Use scan_static_bus() over scan_lpc_bus() ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Gerrit-Change-Number: 29474 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 07 Oct 2019 15:31:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/qemu-x86: Add x86_64 bootblock support
by Name of user not set (Code Review) 07 Oct '19

07 Oct '19

Name of user not set #1002476 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35680 ) Change subject: cpu/qemu-x86: Add x86_64 bootblock support ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/x86/64bit/entry64.… File src/cpu/x86/64bit/entry64.inc: https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/x86/64bit/entry64.… PS6, Line 22: Clobers Clobbers -- To view, visit https://review.coreboot.org/c/coreboot/+/35680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Gerrit-Change-Number: 35680 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Name of user not set #1002476 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 07 Oct 2019 15:11:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/facebook/fbg1701: Enable display of logo
by Frans Hendriks (Code Review) 07 Oct '19

07 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34402 ) Change subject: mainboard/facebook/fbg1701: Enable display of logo ...................................................................... mainboard/facebook/fbg1701: Enable display of logo Specify FSP1_1_LOGO_FILE_NAME and enable display of logo. BUG=N/A TEST=Display is displayed on Facebook FBG1701 Change-Id: I24c6fcd829aa45c1b194f6ae273a20526aa89943 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/34402/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 95d8f6c..ada5f2a 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -76,7 +76,13 @@ config FSP1_1_DISPLAY_LOGO bool - default n + default y + +config FSP1_1_LOGO_FILE_NAME + string + depends on FSP1_1_DISPLAY_LOGO + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/logo.bmp" + config SPI_FLASH_INCLUDE_ALL_DRIVERS bool -- To view, visit https://review.coreboot.org/c/coreboot/+/34402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24c6fcd829aa45c1b194f6ae273a20526aa89943 Gerrit-Change-Number: 34402 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: 3rdparty/blobs: Upgrade to version with Facebook FBG101 logo
by Frans Hendriks (Code Review) 07 Oct '19

07 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34401 ) Change subject: 3rdparty/blobs: Upgrade to version with Facebook FBG101 logo ...................................................................... 3rdparty/blobs: Upgrade to version with Facebook FBG101 logo Use blobs version with logo file BUG=N/A TEST=booting Facebook FBG1701 Change-Id: I926e998745556de9ae913b4b7a6cde8b3ddb4bcf Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34401/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index d7600dd..ab91bf0 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit d7600dd8718a076f0f9a89e53968b484254624dc +Subproject commit ab91bf059215318373f5a2d29f28a603b4139359 -- To view, visit https://review.coreboot.org/c/coreboot/+/34401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926e998745556de9ae913b4b7a6cde8b3ddb4bcf Gerrit-Change-Number: 34401 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1394
by Ronak Kanabar (Code Review) 07 Oct '19

07 Oct '19

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35851 ) Change subject: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1394 ...................................................................... src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1394 Change-Id: I19a931d9aecead1e81937db69436abf67f293d35 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h 3 files changed, 91 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/35851/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h index 962463e..aee01c8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h @@ -37,19 +37,19 @@ #pragma pack(1) - -#include <MemInfoHob.h> - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - + +#include <MemInfoHob.h> + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + /** Fsp M Configuration **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h index 0df3063..a92b0ae 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h @@ -37,49 +37,49 @@ #pragma pack(1) - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + /** Fsp S Configuration **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h index 508705c..ee3405d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h @@ -129,31 +129,47 @@ **/ UINT8 PcdSerialIoUartAutoFlow; -/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT - Select RX pin muxing for SerialIo UART used for debug +/** Offset 0x0058 - PcdSerialIoUartPinMux - FSPT + Applies only to UART0 muxed with CNVI <b> 0 = GPIO C8 to C11 </b> 1 = GPIO F5 - + F7 (PCH LP) J5 - J7 (PCH H) + 0: GPIO C8 to C11, 1: GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H) **/ - UINT32 PcdSerialIoUartRxPinMux; + UINT8 PcdSerialIoUartPinMux; -/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT - Select TX pin muxing for SerialIo UART used for debug +/** Offset 0x0059 - PcdLpcUartDebugEnable + Enable to initialize LPC Uart device in FSP. + 0:Disable, 1:Enable **/ - UINT32 PcdSerialIoUartTxPinMux; + UINT8 PcdLpcUartDebugEnable; -/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT - Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* - for possible values. +/** Offset 0x005A - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. **/ - UINT32 PcdSerialIoUartRtsPinMux; + UINT8 PcdDebugInterfaceFlags; -/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT - Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* - for possible values. +/** Offset 0x005B - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info, 5:Load Error Warnings Info and Verbose **/ - UINT32 PcdSerialIoUartCtsPinMux; + UINT8 PcdSerialDebugLevel; -/** Offset 0x0068 +/** Offset 0x005C - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 **/ - UINT8 ReservedFsptUpd1[24]; + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x005D +**/ + UINT8 UnusedUpdSpace1[7]; + +/** Offset 0x0064 +**/ + UINT8 ReservedFsptUpd1[20]; } FSP_T_CONFIG; /** Fsp T UPD Configuration @@ -172,11 +188,11 @@ **/ FSP_T_CONFIG FsptConfig; -/** Offset 0x0080 +/** Offset 0x0078 **/ - UINT8 UnusedUpdSpace1[6]; + UINT8 UnusedUpdSpace2[6]; -/** Offset 0x0086 +/** Offset 0x007E **/ UINT16 UpdTerminator; } FSPT_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/35851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19a931d9aecead1e81937db69436abf67f293d35 Gerrit-Change-Number: 35851 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Yu-Ping Wu (Code Review) 07 Oct '19

07 Oct '19

Hello Julius Werner, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35775 to look at the new patch set (#9). Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... soc/mediatek/mt8183: Add the shared 'dramc_param' module The dramc_param module simplifies the communication between coreboot and MTK DRAM full calibration blob, and is shared by both implementations to ensure the same format of parameters. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_param.c A src/soc/mediatek/mt8183/include/soc/dramc_param.h 3 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35775/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 9 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/monolake: Add GPIO table and initialize
by Jingle Hsu (Code Review) 07 Oct '19

07 Oct '19

Jingle Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35367 ) Change subject: mb/ocp/monolake: Add GPIO table and initialize ...................................................................... mb/ocp/monolake: Add GPIO table and initialize Add GPIO table for Monolake to initialize GPIOs. Tested on Monolake Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> --- A src/mainboard/ocp/monolake/gpio.h M src/mainboard/ocp/monolake/romstage.c 2 files changed, 106 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35367/1 diff --git a/src/mainboard/ocp/monolake/gpio.h b/src/mainboard/ocp/monolake/gpio.h new file mode 100644 index 0000000..982daa4 --- /dev/null +++ b/src/mainboard/ocp/monolake/gpio.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#ifndef MONOLAKE_GPIO_H +#define MONOLAKE_GPIO_H + +static const struct gpio_config gpio_tables[] = { + {0, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {1, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {2, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {3, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {4, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {5, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {6, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {7, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {8, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {10, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {11, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {12, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {13, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {15, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {16, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {17, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {18, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {19, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {20, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {21, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {22, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {23, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {24, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {25, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {26, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {27, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {28, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {30, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {32, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {35, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {36, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {37, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {38, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {39, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {40, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {41, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {42, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {44, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {45, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {48, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {49, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {50, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {51, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {52, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {53, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {54, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {55, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {57, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {58, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {59, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {60, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {61, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {62, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {63, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {65, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {67, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {68, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {69, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {70, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {71, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {72, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {74, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {75, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {0xff, GPIO_LIST_END, 0, 0, 0, 0}, +}; + +#endif diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index 8625868..d7f2c3a 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -24,6 +24,8 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> +#include <soc/gpio.h> +#include "gpio.h" /* Define the strings for UPD variables that could be customized */ #define FSP_VAR_HYPERTHREADING "HyperThreading" @@ -59,6 +61,9 @@ // IPMI through BIC pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, 0x0c0ca1); + + // Initialize GPIOs + init_gpios(gpio_tables); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/35367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Gerrit-Change-Number: 35367 Gerrit-PatchSet: 1 Gerrit-Owner: Jingle Hsu Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Ken Lu (Code Review) 07 Oct '19

07 Oct '19

Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 2: > Patch Set 2: > > (1 comment) Set 0 means set null . It will make passive setting disabled by filled value 0 . -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 07 Oct 2019 02:39:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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