coreboot-gerrit October 2019

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Change in coreboot[master]: [TESTME]sb/intel/nm10: Fix enabling HPET
by Arthur Heymans (Code Review) 07 Oct '19

07 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35758 ) Change subject: [TESTME]sb/intel/nm10: Fix enabling HPET ...................................................................... [TESTME]sb/intel/nm10: Fix enabling HPET RCBA_HPTC needs to be read back to consistently enable HPET. This ought to fix raminit failing sometimes and SeaBIOS endlessly waiting for user input. TODO untested Change-Id: I20a25fd97cd09fedb70469262c64d8d3828bb684 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/raminit.c M src/southbridge/intel/i82801gx/lpc.c 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/35758/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 5cece41..7f59d91 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -552,10 +552,12 @@ static void enable_hpet(void) { u32 reg32; - reg32 = RCBA32(0x3404); + reg32 = RCBA32(HPTC); reg32 &= ~0x3; reg32 |= (1 << 7); - RCBA32(0x3404) = reg32; + RCBA32(HPTC) = reg32; + /* On NM10 this only works if read back */ + RCBA32(HPTC); HPET32(0x10) = HPET32(0x10) | 1; } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 4e2f9f9..62576c1 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -310,6 +310,10 @@ reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; + /* On NM10 this only works if read back */ + RCBA32(HPTC); + + write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); } static void enable_clock_gating(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/35758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20a25fd97cd09fedb70469262c64d8d3828bb684 Gerrit-Change-Number: 35758 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/{lenovo/x201,packardbell/ms2290}/acpi/platform: We don't have PDC[...
by Peter Lemenkov (Code Review) 06 Oct '19

06 Oct '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35449 ) Change subject: mb/{lenovo/x201,packardbell/ms2290}/acpi/platform: We don't have PDC[01] variables ...................................................................... mb/{lenovo/x201,packardbell/ms2290}/acpi/platform: We don't have PDC[01] variables Change-Id: I330e5b5ff352668a8847d1e4646f4ef5be6a806f Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x201/acpi/platform.asl M src/mainboard/packardbell/ms2290/acpi/platform.asl 2 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/35449/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 7d7013b..167fe03 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -14,10 +14,6 @@ * GNU General Public License for more details. */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - /* The APM port can be used for generating software SMIs */ OperationRegion (APMP, SystemIO, 0xb2, 2) diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 9812d14..21d8115 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -14,10 +14,6 @@ * GNU General Public License for more details. */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - /* The APM port can be used for generating software SMIs */ OperationRegion (APMP, SystemIO, 0xb2, 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/35449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I330e5b5ff352668a8847d1e4646f4ef5be6a806f Gerrit-Change-Number: 35449 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: Use scan_static_bus() over scan_lpc_bus()
by Nico Huber (Code Review) 06 Oct '19

06 Oct '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29474 ) Change subject: device: Use scan_static_bus() over scan_lpc_bus() ...................................................................... Patch Set 9: (4 comments) https://review.coreboot.org/c/coreboot/+/29474/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/29474/1//COMMIT_MSG@7 PS1, Line 7: device/root_device: Scan bridges on LPC bus too > Could you please provide a reasoning in the commit description as well as what sort of bridges exist […] Done https://review.coreboot.org/c/coreboot/+/29474/5/src/device/root_device.c File src/device/root_device.c: https://review.coreboot.org/c/coreboot/+/29474/5/src/device/root_device.c@66 PS5, Line 66: void scan_lpc_bus(struct device *bus) > Yep (the former sneaked into a rebase). I'll try to consolidate this. Done https://review.coreboot.org/c/coreboot/+/29474/5/src/device/root_device.c@1… PS5, Line 105: link->secondary = ++bus_max; > Should be needed for dev_find_slot_on_smbus() only? Rename to smbus_idx and set conditionally on pat […] Unrelated (will hopefully vanish after the next code removal). https://review.coreboot.org/c/coreboot/+/29474/5/src/device/root_device.c@1… PS5, Line 126: void scan_smbus(struct device *bus) > I kind of like that we assign . […] Won't do, see reasoning in parent change. -- To view, visit https://review.coreboot.org/c/coreboot/+/29474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Gerrit-Change-Number: 29474 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Oct 2019 16:16:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] Give `lenovo_serial` EEPROMs a name in dt
by Nico Huber (Code Review) 06 Oct '19

06 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35457 ) Change subject: [WIP] Give `lenovo_serial` EEPROMs a name in dt ...................................................................... [WIP] Give `lenovo_serial` EEPROMs a name in dt Change-Id: I99edb7a8428ac7efa275fa09a10ec051b0f9abd3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/mainboard/lenovo/x200/devicetree.cb 2 files changed, 13 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35457/1 diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 0a6b343..3464e4a 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -20,17 +20,22 @@ #include <smbios.h> #include <console/console.h> #include <version.h> +#include <static.h> #include "lenovo.h" #define ERROR_STRING "*INVALID*" static struct device *at24rf08c_find_bank(u8 bank) { - struct device *dev; - dev = dev_find_slot_on_smbus(1, 0x54 | bank); - if (!dev) - printk(BIOS_WARNING, "EEPROM not found\n"); - return dev; + switch (bank) { + case 0: + return &__static_lenovo_serial0; + case 2: + return &__static_lenovo_serial2; + default: + die("%s: Unknown EEPROM bank number.\n", __func__); + return NULL; + } } static int at24rf08c_read_byte(struct device *dev, u8 addr) @@ -134,14 +139,7 @@ memset(result, 0, sizeof (result)); - dev = dev_find_slot_on_smbus(1, 0x56); - if (dev == NULL) { - printk(BIOS_WARNING, "EEPROM not found\n"); - already_read = 1; - memset(uuid, 0, 16); - return; - } - + dev = at24rf08c_find_bank(2); for (i = 0; i < 16; i++) { int t; int j; diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 2ed4308..5ff5d52 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -215,9 +215,9 @@ ioapic_irq 2 INTC 0x12 # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c - device i2c 54 on end + device i2c 54 as lenovo_serial0 on end device i2c 55 on end - device i2c 56 on end + device i2c 56 as lenovo_serial2 on end device i2c 57 on end device i2c 5c on end device i2c 5d on end -- To view, visit https://review.coreboot.org/c/coreboot/+/35457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99edb7a8428ac7efa275fa09a10ec051b0f9abd3 Gerrit-Change-Number: 35457 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NOTFORMERGE] soc/intel exit_car.S
by Kyösti Mälkki (Code Review) 06 Oct '19

06 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35187 ) Change subject: [NOTFORMERGE] soc/intel exit_car.S ...................................................................... [NOTFORMERGE] soc/intel exit_car.S Change-Id: Icd369029d9bbf0aa72923513952e1aacf88c0f40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/exit_car.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/common/block/cpu/car/exit_car.S M src/soc/intel/common/block/cpu/car/exit_car.S 6 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/35187/1 diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 769a758..8ae7a66 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -34,6 +34,7 @@ call gdt_init /* chipset_teardown_car() is expected to disable cache-as-ram. */ + /* ..... */ call chipset_teardown_car /* Enable caching if not already enabled. */ @@ -42,6 +43,7 @@ mov %eax, %cr0 /* Ensure cache is clean. */ + /* ..... */ invd /* Set up new stack. */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 8adc5f6..ee71d81 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -29,6 +29,7 @@ post_code(0x30) /* Disable cache. */ + /* ..... */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 3b99128..ba57546 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -27,6 +27,7 @@ post_code(0x30) /* Disable cache. */ + /* ..... */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 4f0bb3f..37dfd3f 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -131,6 +131,7 @@ #endif /* Disable cache */ + /* ..... */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S index f9d056e..9a36df0 100644 --- a/src/soc/amd/common/block/cpu/car/exit_car.S +++ b/src/soc/amd/common/block/cpu/car/exit_car.S @@ -23,6 +23,7 @@ pop %esp /* Disable cache */ + /* ..... */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index ab7886c..8aa8bfb 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -44,6 +44,10 @@ */ pop %ebx + + /* Disable cache ??? */ + + /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx rdmsr @@ -55,6 +59,7 @@ car_nem_teardown: /* invalidate cache contents. */ + /* maybe redundant ? */ invd /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ @@ -69,6 +74,8 @@ .global car_cqos_teardown car_cqos_teardown: + /* inconsistent, no invd here */ + /* Go back to all-evicting mode, set both masks to all-1s */ mov $MSR_L2_QOS_MASK(0), %ecx rdmsr @@ -91,6 +98,7 @@ car_nem_enhanced_teardown: /* invalidate cache contents. */ + /* maybe redundant ? */ invd /* Knock down bit 1 then bit 0 of NEM control not combining steps. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd369029d9bbf0aa72923513952e1aacf88c0f40 Gerrit-Change-Number: 35187 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: gma ilk hdmi: Add workaround for enable-bit quirk
by Nico Huber (Code Review) 06 Oct '19

06 Oct '19

Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/35784 to review the following change. Change subject: gma ilk hdmi: Add workaround for enable-bit quirk ...................................................................... gma ilk hdmi: Add workaround for enable-bit quirk The HDMI-enable bit is quirky, too. We are supposed to always set it twice. Change-Id: I9d093ff9a3178e01638f65b0607bc8d08c009978 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/ironlake/hw-gfx-gma-pch-hdmi.adb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/84/35784/1 diff --git a/common/ironlake/hw-gfx-gma-pch-hdmi.adb b/common/ironlake/hw-gfx-gma-pch-hdmi.adb index 4ca9ecd..7210a95 100644 --- a/common/ironlake/hw-gfx-gma-pch-hdmi.adb +++ b/common/ironlake/hw-gfx-gma-pch-hdmi.adb @@ -66,6 +66,10 @@ PCH_TRANSCODER_SELECT (FDI_Port) or PCH_HDMI_SDVO_ENCODING_HDMI or Polarity); + Registers.Posting_Read (PCH_HDMI (Port_Cfg.PCH_Port)); + -- Set enable a second time, hardware may miss the first. + Registers.Set_Mask (PCH_HDMI (Port_Cfg.PCH_Port), PCH_HDMI_ENABLE); + Registers.Posting_Read (PCH_HDMI (Port_Cfg.PCH_Port)); end On; ---------------------------------------------------------------------------- @@ -97,6 +101,9 @@ -- Reenable with transcoder A selected to switch. Registers.Set_Mask (PCH_HDMI (Port), PCH_HDMI_ENABLE); Registers.Posting_Read (PCH_HDMI (Port)); + -- Set enable a second time, hardware may miss the first. + Registers.Set_Mask (PCH_HDMI (Port), PCH_HDMI_ENABLE); + Registers.Posting_Read (PCH_HDMI (Port)); Registers.Unset_Mask (PCH_HDMI (Port), PCH_HDMI_ENABLE); Registers.Posting_Read (PCH_HDMI (Port)); end if; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I9d093ff9a3178e01638f65b0607bc8d08c009978 Gerrit-Change-Number: 35784 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: [WIP] gma irl: Handle Ibex Peak DP correctly
by Nico Huber (Code Review) 06 Oct '19

06 Oct '19

Hello Arthur Heymans, Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/35740 to review the following change. Change subject: [WIP] gma irl: Handle Ibex Peak DP correctly ...................................................................... [WIP] gma irl: Handle Ibex Peak DP correctly Change-Id: I0c1fafc2ba113aeeaf4ace750b333cc270bca37c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/ironlake/hw-gfx-gma-connectors.adb M common/ironlake/hw-gfx-gma-pch-dp.adb M common/ironlake/hw-gfx-gma-pch-dp.ads M common/ironlake/hw-gfx-gma-pch-hdmi.adb 4 files changed, 68 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/40/35740/1 diff --git a/common/ironlake/hw-gfx-gma-connectors.adb b/common/ironlake/hw-gfx-gma-connectors.adb index 9bb0b68..21eca97 100644 --- a/common/ironlake/hw-gfx-gma-connectors.adb +++ b/common/ironlake/hw-gfx-gma-connectors.adb @@ -88,7 +88,7 @@ elsif Port_Cfg.PCH_Port in PCH_HDMI_Port then PCH.HDMI.On (Port_Cfg, FDI_Port); elsif Port_Cfg.PCH_Port in PCH_DP_Port then - PCH.DP.On (Port_Cfg, Success); + PCH.DP.On (Port_Cfg, FDI_Port, Success); end if; end if; end; diff --git a/common/ironlake/hw-gfx-gma-pch-dp.adb b/common/ironlake/hw-gfx-gma-pch-dp.adb index 15d3720..95209d7 100644 --- a/common/ironlake/hw-gfx-gma-pch-dp.adb +++ b/common/ironlake/hw-gfx-gma-pch-dp.adb @@ -34,15 +34,25 @@ DP_CTL_PREEMPH_LEVEL_SET_SHIFT : constant := 22; DP_CTL_PREEMPH_LEVEL_SET_MASK : constant := 7 * 2 ** 22; DP_CTL_PORT_WIDTH_SHIFT : constant := 19; + DP_CTL_ENHANCED_FRAMING_ENABLE : constant := 1 * 2 ** 18; DP_CTL_PORT_REVERSAL : constant := 1 * 2 ** 15; - DP_CTL_LINK_TRAIN_MASK : constant := 7 * 2 ** 8; - DP_CTL_LINK_TRAIN_PAT1 : constant := 0 * 2 ** 8; - DP_CTL_LINK_TRAIN_PAT2 : constant := 1 * 2 ** 8; - DP_CTL_LINK_TRAIN_IDLE : constant := 2 * 2 ** 8; - DP_CTL_LINK_TRAIN_NORMAL : constant := 3 * 2 ** 8; DP_CTL_AUDIO_OUTPUT_ENABLE : constant := 1 * 2 ** 6; DP_CTL_PORT_DETECT : constant := 1 * 2 ** 2; + function DP_CTL_LINK_TRAIN_SHIFT return Natural is + (if Config.Has_Trans_DP_Ctl then 8 else 28); + + function DP_CTL_LINK_TRAIN_MASK return Word32 is + (if Config.Has_Trans_DP_Ctl then 7 * 2 ** 8 else 3 * 2 ** 28); + + function DP_CTL_LINK_TRAIN (Pat : DP_Info.Training_Pattern) return Word32 is + (case Pat is + when DP_Info.TP_1 => Shift_Left (0, DP_CTL_LINK_TRAIN_SHIFT), + when DP_Info.TP_2 => Shift_Left (1, DP_CTL_LINK_TRAIN_SHIFT), + when DP_Info.TP_3 => Shift_Left (1, DP_CTL_LINK_TRAIN_SHIFT), + when DP_Info.TP_Idle => Shift_Left (2, DP_CTL_LINK_TRAIN_SHIFT), + when DP_Info.TP_None => Shift_Left (3, DP_CTL_LINK_TRAIN_SHIFT)); + function DP_CTL_VSWING_LEVEL_SET (VS : DP_Info.DP_Voltage_Swing) return Word32 @@ -68,14 +78,6 @@ DP_CTL_PORT_WIDTH_SHIFT); end DP_CTL_PORT_WIDTH; - type DP_CTL_LINK_TRAIN_Array is array (DP_Info.Training_Pattern) of Word32; - DP_CTL_LINK_TRAIN : constant DP_CTL_LINK_TRAIN_Array := - (DP_Info.TP_1 => DP_CTL_LINK_TRAIN_PAT1, - DP_Info.TP_2 => DP_CTL_LINK_TRAIN_PAT2, - DP_Info.TP_3 => DP_CTL_LINK_TRAIN_PAT2, - DP_Info.TP_Idle => DP_CTL_LINK_TRAIN_IDLE, - DP_Info.TP_None => DP_CTL_LINK_TRAIN_NORMAL); - ---------------------------------------------------------------------------- pragma Warnings (GNATprove, Off, "unused variable ""Port""", @@ -134,17 +136,37 @@ procedure Off (Port : PCH_DP_Port) is + With_Transcoder_B_Enabled : Boolean; begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + if not Config.Has_Trans_DP_Ctl then + -- Ensure transcoder select isn't set to B, + -- disabled DP may block HDMI otherwise. + Registers.Is_Set_Mask + (Register => DP_CTL (Port), + Mask => DP_CTL_DISPLAY_PORT_ENABLE or + PCH_TRANSCODER_SELECT (FDI_B), + Result => With_Transcoder_B_Enabled); + end if; + Registers.Unset_And_Set_Mask (Register => DP_CTL (Port), Mask_Unset => DP_CTL_LINK_TRAIN_MASK, - Mask_Set => DP_CTL_LINK_TRAIN_IDLE); + Mask_Set => DP_CTL_LINK_TRAIN (DP_Info.TP_Idle)); Registers.Posting_Read (DP_CTL (Port)); Registers.Write (DP_CTL (Port), 0); Registers.Posting_Read (DP_CTL (Port)); + + if not Config.Has_Trans_DP_Ctl and then With_Transcoder_B_Enabled then + -- Reenable with transcoder A selected to switch. + Registers.Write (DP_CTL (Port), DP_CTL_DISPLAY_PORT_ENABLE); + Registers.Posting_Read (DP_CTL (Port)); + Registers.Write (DP_CTL (Port), 0); + Registers.Posting_Read (DP_CTL (Port)); + end if; + end Off; pragma Warnings (GNATprove, On, "unused variable ""Port"""); pragma Warnings (GNATprove, On, "unused variable ""Link"""); @@ -153,6 +175,7 @@ procedure On (Port_Cfg : in Port_Config; + FDI_Port : in FDI_Port_Type; Success : out Boolean) is function To_DP (Port : PCH_DP_Port) return DP_Port @@ -176,14 +199,23 @@ Set_Pattern => Set_Training_Pattern, Set_Signal_Levels => Set_Signal_Levels, Off => Off); + + DP_CTL_Transcoder_Select : constant Word32 := + (if Config.Has_Trans_DP_Ctl + then 0 else PCH_TRANSCODER_SELECT (FDI_Port)); + DP_CTL_Enhanced_Framing : constant Word32 := + (if Config.Has_Trans_DP_Ctl + then 0 else DP_CTL_ENHANCED_FRAMING_ENABLE); begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); Registers.Write (Register => DP_CTL (Port_Cfg.PCH_Port), Value => DP_CTL_DISPLAY_PORT_ENABLE or + DP_CTL_Transcoder_Select or DP_CTL_PORT_WIDTH (Port_Cfg.DP.Lane_Count) or - DP_CTL_LINK_TRAIN_PAT1); + DP_CTL_Enhanced_Framing or + DP_CTL_LINK_TRAIN (DP_Info.TP_1)); Training.Train_DP (Port => Port_Cfg.PCH_Port, diff --git a/common/ironlake/hw-gfx-gma-pch-dp.ads b/common/ironlake/hw-gfx-gma-pch-dp.ads index c2ab299..83c546d 100644 --- a/common/ironlake/hw-gfx-gma-pch-dp.ads +++ b/common/ironlake/hw-gfx-gma-pch-dp.ads @@ -17,6 +17,7 @@ procedure On (Port_Cfg : in Port_Config; + FDI_Port : in FDI_Port_Type; Success : out Boolean) with Pre => Port_Cfg.PCH_Port in PCH_DP_Port; diff --git a/common/ironlake/hw-gfx-gma-pch-hdmi.adb b/common/ironlake/hw-gfx-gma-pch-hdmi.adb index aaf7951..7417caa 100644 --- a/common/ironlake/hw-gfx-gma-pch-hdmi.adb +++ b/common/ironlake/hw-gfx-gma-pch-hdmi.adb @@ -72,14 +72,33 @@ procedure Off (Port : PCH_HDMI_Port) is + With_Transcoder_B_Enabled : Boolean; begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + if not Config.Has_Trans_DP_Ctl then + -- Ensure transcoder select isn't set to B, + -- disabled HDMI may block DP otherwise. + Registers.Is_Set_Mask + (Register => PCH_HDMI (Port), + Mask => PCH_HDMI_ENABLE or + PCH_TRANSCODER_SELECT (FDI_B), + Result => With_Transcoder_B_Enabled); + end if; + Registers.Unset_And_Set_Mask (Register => PCH_HDMI (Port), Mask_Unset => PCH_HDMI_MASK, Mask_Set => PCH_HDMI_HSYNC_ACTIVE_HIGH or PCH_HDMI_VSYNC_ACTIVE_HIGH); + + if not Config.Has_Trans_DP_Ctl and then With_Transcoder_B_Enabled then + -- Reenable with transcoder A selected to switch. + Registers.Set_Mask (PCH_HDMI (Port), PCH_HDMI_ENABLE); + Registers.Posting_Read (PCH_HDMI (Port)); + Registers.Unset_Mask (PCH_HDMI (Port), PCH_HDMI_ENABLE); + end if; + end Off; procedure All_Off -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I0c1fafc2ba113aeeaf4ace750b333cc270bca37c Gerrit-Change-Number: 35740 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

3 10

Change in libgfxinit[master]: Increase range of our main Frequency_Type
by Nico Huber (Code Review) 06 Oct '19

06 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/35750 ) Change subject: Increase range of our main Frequency_Type ...................................................................... Increase range of our main Frequency_Type Increase `Frequency_Type` to 1MHz .. 2.5Ghz. We used to adapt it whenever necessary, e.g. when a new generation supported higher frequencies. But that got a little annoying. So let's choose a broader range that will hopefully lower the noise for some time. 1MHz is low enough for VGA resolution at 24p, and 2.5GHz is high enough for 8K at 60p. That should give us some margin. Some corner cases required refactoring of some calculations and proofs. And, admittedly, the calculation in `HW.GFX.GMA.PCH.VGA` can in theory overflow, indeed. But our PLL calculations should ensure that this never happens. Change-Id: I3a159bc11ccadcaba8ad04e126e6feadfd46008e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-dp_info.adb M common/hw-gfx-gma-pch-vga.adb M common/hw-gfx.ads 3 files changed, 8 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/50/35750/1 diff --git a/common/hw-gfx-dp_info.adb b/common/hw-gfx-dp_info.adb index 7ac4556..d45826d 100644 --- a/common/hw-gfx-dp_info.adb +++ b/common/hw-gfx-dp_info.adb @@ -93,28 +93,11 @@ with Depends => ((Link, Success) => (Link, Mode)) is - function Link_Pixel_Per_Second - (Link_Rate : DP_Bandwidth) - return Positive - with - Post => Pos64 (Link_Pixel_Per_Second'Result) <= - ((DP_Symbol_Rate_Type'Last * 8) / 3) / BPC_Type'First - is - begin - -- Link_Rate is brutto with 8/10 bit symbols; three colors - pragma Assert (Positive (DP_Symbol_Rate (Link_Rate)) <= (Positive'Last / 8) * 3); - pragma Assert ((Int64 (DP_Symbol_Rate (Link_Rate)) * 8) / 3 - >= Int64 (BPC_Type'Last)); - return Positive - (((Int64 (DP_Symbol_Rate (Link_Rate)) * 8) / 3) - / Int64 (Mode.BPC)); - end Link_Pixel_Per_Second; - - Count : Natural; + Lane_Pixel_Per_Second : constant Pos64 := + (((DP_Symbol_Rate (Link.Bandwidth) * 8) / 3) / Mode.BPC); + Count : constant Pos64 := + Div_Round_Up (Mode.Dotclock, Lane_Pixel_Per_Second); begin - Count := Link_Pixel_Per_Second (Link.Bandwidth); - Count := (Positive (Mode.Dotclock) + Count - 1) / Count; - Success := True; case Count is when 1 => Link.Lane_Count := DP_Lane_Count_1; @@ -184,8 +167,8 @@ DATA_N_MAX : constant := 16#800000#; LINK_N_MAX : constant := 16#100000#; - subtype Calc_M_Type is Int64 range 0 .. 2 ** 36; - subtype Calc_N_Type is Int64 range 0 .. 2 ** 36; + subtype Calc_M_Type is Int64 range 0 .. 2 ** 38; + subtype Calc_N_Type is Int64 range 0 .. 2 ** 38; subtype N_Rounded_Type is Int64 range 0 .. Int64'Max (DATA_N_MAX, LINK_N_MAX); diff --git a/common/hw-gfx-gma-pch-vga.adb b/common/hw-gfx-gma-pch-vga.adb index fd82740..eb7f9a0 100644 --- a/common/hw-gfx-gma-pch-vga.adb +++ b/common/hw-gfx-gma-pch-vga.adb @@ -135,7 +135,7 @@ Mask => SBI_SSCCTL_DISABLE); Aux_Div := 16#0000_0000#; - Div_Sel := Word32 (Refclock / Mode.Dotclock - 2); + Div_Sel := Word32 (Refclock / Mode.Dotclock) - 2; Phase_Inc := Word32 ((Refclock * 64) / Mode.Dotclock) and 16#0000_003f#; Phase_Dir := 16#0000_0000#; diff --git a/common/hw-gfx.ads b/common/hw-gfx.ads index 93a3684..2cfc017 100644 --- a/common/hw-gfx.ads +++ b/common/hw-gfx.ads @@ -66,7 +66,7 @@ Rotation => No_Rotation, Offset => 0); - subtype Frequency_Type is Pos64 range 19_200_000 .. 624_000_000; + subtype Frequency_Type is Pos64 range 1_000_000 .. 2_500_000_000; type DP_Lane_Count is (DP_Lane_Count_1, DP_Lane_Count_2, DP_Lane_Count_4); subtype DP_Lane_Count_Type is Pos64 range 1 .. 4; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I3a159bc11ccadcaba8ad04e126e6feadfd46008e Gerrit-Change-Number: 35750 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: cpu/qemu-x86: Add x86_64 bootblock support
by build bot (Jenkins) (Code Review) 06 Oct '19

06 Oct '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35680 ) Change subject: cpu/qemu-x86: Add x86_64 bootblock support ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c File util/pgtblgen/pgtblgen.c: https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c@28 PS6, Line 28: printf("usage: %s -b <addr> -a <arch> -o <file>\n", argv[0]); Prefer using '"%s...", __func__' to using 'usage', this function's name, in a string https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c@1… PS6, Line 147: FILE *fd = fopen(filename, "wb"); need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/35680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Gerrit-Change-Number: 35680 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 06 Oct 2019 12:19:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/qemu-x86: Add x86_64 bootblock support
by Patrick Rudolph (Code Review) 06 Oct '19

06 Oct '19

Hello Kyösti Mälkki, Aaron Durbin, Alexandru Gagniuc, ron minnich, Gerd Hoffmann, Lee Leahy, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35680 to look at the new patch set (#6). Change subject: cpu/qemu-x86: Add x86_64 bootblock support ...................................................................... cpu/qemu-x86: Add x86_64 bootblock support Add support for x86_64 bootblock on qemu. Introduce a new approach to long mode support. The previous patch set generated page tables at runtime and placed them in heap. The new approach places the page tables in memory mapped ROM. Introduce a new tool called pgtblgen that creates x86 long mode compatible page tables and writes those to a file. The file is included into the CBFS and placed at a predefined offset. Add assembly code to load the page tables, based on a Kconfig symbol and enter long in bootblock. The code can be easily ported to real hardware bootblock. Tested on qemu q35. Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M Makefile.inc M src/arch/x86/Kconfig M src/arch/x86/bootblock_crt0.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S A src/cpu/x86/64bit/entry64.inc A util/pgtblgen/Makefile.inc A util/pgtblgen/description.md A util/pgtblgen/pgtblgen.c 9 files changed, 294 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/35680/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/35680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Gerrit-Change-Number: 35680 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2019