coreboot-gerrit October 2019

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Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Hung-Te Lin (Code Review) 07 Oct '19

07 Oct '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35775 ) Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 7 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Oct 2019 02:15:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/RFC: Drop obsolete doc
by Patrick Georgi (Code Review) 07 Oct '19

07 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35818 ) Change subject: Documentation/RFC: Drop obsolete doc ...................................................................... Documentation/RFC: Drop obsolete doc The format was retired 10 years ago when we moved to the new build system, kconfig and sconfig. Retire the doc as well. Change-Id: Ica1c353a80d411845b92038521d85ad5f3d359bc Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- D Documentation/RFC/config.tex 1 file changed, 0 insertions(+), 290 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/35818/1 diff --git a/Documentation/RFC/config.tex b/Documentation/RFC/config.tex deleted file mode 100644 index c11e622..0000000 --- a/Documentation/RFC/config.tex +++ /dev/null @@ -1,290 +0,0 @@ - New config language for LinuxBIOS - -\begin{abstract} -We describe the new configuration language for LinuxBIOS. -\end{abstract} - -\section{Scope} -This document defines the new configuration language for LinuxBIOS. - -\section{Goals} -The goals of the new language are these: -\begin{itemize} -\item Simplified Makefiles so people can see what is set -\item Move from the regular-expression-based language to something -a bit more comprehensible and flexible -\item make the specification easier for people to use and understand -\item allow unique register-set-specifiers for each chip -\item allow generic register-set-specifiers for each chip -\item generate static initialization code, as needed, for the -specifiers. -\end{itemize} - -\section{Language} -Here is the new language. It is very similar to the old one, differing -in only a few respects. It borrows heavily from Greg Watson's suggestions. - -I am presenting it in a pseudo-BNF in the hopes it will be easier. Things -in '' are keywords; things in ``'' are strings in the actual text. -\begin{verbatim} -#exprs are composed of factor or factor + factor etc. -expr ::= factor ( ``+'' factor | ``-'' factor | )* -#factors are term or term * term or term / term or ... -factor ::= term ( ``*'' term | ``/'' term | ... )* -# -unary-op ::= ``!'' ID -# term is a number, hexnumber, ID, unary-op, or a full-blown expression -term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)'' - -# Option command. Can be an expression or quote-string. -# Options are used in the config tool itself (in expressions and 'if') -# and are also passed to the C compiler when building linuxbios. -# It is an error to have two option commands in a file. -# It is an error to have an option command after the ID has been used -# in an expression (i.e. 'set after used' is an error) -option ::= 'option' ID '=' (``value'' | term) - -# Default command. The ID is set to this value if no option command -# is scanned. -# Multiple defaults for an ID will produce warning, but not errors. -# It is OK to scan a default command after use of an ID. -# Options always over-ride defaults. -default ::= 'default' ID '=' (``value'' | term) - -# the mainboard, southbridge, northbridge commands -# cause sourcing of Config.lb files as in the old config tool -# as parts are sourced, a device tree is built. The structure -# of the tree is determined by the structure of the components -# as they are specified. To attach a superio to a southbridge, for -# example, one would do this: -# southbridge acer/5432 -# superio nsc/123 -# end -# end -# the tool generates static initializers for this hierarchy. - -# add C code to the current component (motherboard, etc. ) -# to initialise the component-INDEPENDENT structure members -init ::= 'init' ``CODE'' - -# add C code to the current component (motherboard, etc. ) -# to initialise the component-DEPENDENT structure members -register ::= 'register' ``CODE'' - - -# mainboard command -# statements in this block will set variables controlling the mainboard, -# and will also place components (northbridge etc.) in the device tree -# under this mainboard -mainboard ::= 'mainboard' PATH (statements)* 'end' - -# standard linuxbios commands -southbridge ::= 'southbridge' PATH (statemnts)* 'end' -northbridge ::= 'northbridge' PATH (statemnts)* 'end' -superio ::= 'superio PATH (statemnts)* 'end' -cpu ::= 'cpu' PATH (statemnts)* 'end' -arch ::= 'arch' PATH (statemnts)* 'end' - -# files for building linuxbios -# include a file in crt0.S -mainboardinit ::= 'mainboardinit' PATH - -# object file -object ::= 'object' PATH -# driver objects are just built into the image in a different way -driver ::= 'driver' PATH - -# Use the Config.lb file in the PATH -dir ::= 'dir' PATH - -# add a file to the set of ldscript files -ldscript ::= 'ldscript' PATH - -# dependencies or actions for the makerule command -dep ::= 'dep' ``dependency-string'' -act ::= 'act' ``actions'' -depsacts ::= (dep | act)* -# set up a makerule -# -makerule ::= 'makerule' PATH depsacts - -#defines for use in makefiles only -# note usable in the config tool, not passed to cc -makedefine ::= 'makedefine' ``RAWTEXT'' - -# add an action to an existing make rule -addaction ::= 'addaction' PATH ``ACTION'' - -# statements -statement ::= - option - | default - | cpu - | arch - | northbridge - | southbridge - | superio - | object - | driver - | mainboardinit - | makerule - | makedefine - | addaction - | init - | register - | iif - | dir - | ldscript - -statements ::= (statement)* - -# target directory specification -target ::= 'target' PATH - -# and the whole thing -board ::= target (option)* mainboard - -\end{verbatim} - -\subsubsection{Command definitions} -\subsubsubsection{option} -\subsubsubsection{default} -\subsubsubsection{cpu} -\subsubsubsection{arch} -\subsubsubsection{northbridge} -\subsubsubsection{southbridge} -\subsubsubsection{superio} -\subsubsubsection{object} -\subsubsubsection{driver} -\subsubsubsection{mainboardinit} -\subsubsubsection{makerule} -\subsubsubsection{makedefine} -\subsubsubsection{addaction} -\subsubsubsection{init} -\subsubsubsection{register} -\subsubsubsection{iif} -\subsubsubsection{dir} -\subsubsubsection{ldscript} - - -A sample file: - -\begin{verbatim} -target x - -# over-ride the default ROM size in the mainboard file -option CONFIG_ROM_SIZE=1024*1024 -mainboard amd/solo -end - -\end{verbatim} - -Sample mainboard file -\begin{verbatim} -# -### -### Set all of the defaults for an x86 architecture -### -arch i386 end -cpu k8 end -# -option CONFIG_DEBUG=1 -default CONFIG_USE_FALLBACK_IMAGE=1 -option A=(1+2) -option B=0xa -# -### -### Build our 16 bit and 32 bit linuxBIOS entry code -### -mainboardinit cpu/i386/entry16.inc -mainboardinit cpu/i386/entry32.inc -ldscript cpu/i386/entry16.lds -ldscript cpu/i386/entry32.lds -# -### -### Build our reset vector (This is where linuxBIOS is entered) -### -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript cpu/i386/reset16.lds -else - mainboardinit cpu/i386/reset32.inc - ldscript cpu/i386/reset32.lds -end -. -. -. -if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end -# -### -### Romcc output -### -#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E" -#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" -#mainboardinit ./failover.inc -makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E" -makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc" -mainboardinit ./auto.inc -# -### -### Include the secondary Configuration files -### -northbridge amd/amdk8 -end -southbridge amd/amd8111 -end -#mainboardinit arch/i386/smp/secondary.inc -superio nsc/pc87360 - register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1" -end -dir /pc80 -##dir /src/superio/winbond/w83627hf -cpu p5 end -cpu p6 end -cpu k7 end -cpu k8 end -# -### -### Build the objects we have code for in this directory. -### -##object mainboard.o -driver mainboard.o -object static_devices.o -if CONFIG_HAVE_MP_TABLE object mptable.o end -if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -### Location of the DIMM EEPROMS on the SMBUS -### This is fixed into a narrow range by the DIMM package standard. -### -option SMBUS_MEM_DEVICE_START=(0xa << 3) -option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1) -option SMBUS_MEM_DEVICE_INC=1 -# -### The linuxBIOS bootloader. -### -option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) -option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) -# - -\end{verbatim} - -I've found the output of the new tool to be easier to -handle. Makefile.settings looks like this, for example: -\begin{verbatim} -TOP:=/home/rminnich/src/yapps2/freebios2 -TARGET_DIR:=x -export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo -export CONFIG_ARCH:=i386 -export CONFIG_RAMBASE:=0x4000 -export CONFIG_ROM_IMAGE_SIZE:=65535 -export CONFIG_PAYLOAD_SIZE:=131073 -export CONFIG_MAX_CPUS:=1 -export CONFIG_HEAP_SIZE:=8192 -export CONFIG_STACK_SIZE:=8192 -export CONFIG_MEMORY_HOLE:=0 -export COREBOOT_VERSION:=1.1.0 -export CC:=$(CONFIG_CROSS_COMPILE)gcc - -\end{verbatim} - -In other words, instead of expressions, we see the values. It's easier to -deal with. -- To view, visit https://review.coreboot.org/c/coreboot/+/35818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica1c353a80d411845b92038521d85ad5f3d359bc Gerrit-Change-Number: 35818 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add our issue tracker to services
by Patrick Georgi (Code Review) 07 Oct '19

07 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35806 ) Change subject: Documentation: Add our issue tracker to services ...................................................................... Documentation: Add our issue tracker to services Change-Id: Ib249d5c6f2431336a01850f4a8d708795983e7d3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/community/services.md 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35806/1 diff --git a/Documentation/community/services.md b/Documentation/community/services.md index afdf040..8a5b0b4 100644 --- a/Documentation/community/services.md +++ b/Documentation/community/services.md @@ -33,3 +33,7 @@ After you push for review, the system will automatically verify your change and, if adhering to these constraints, approve it. You can then immediately submit it. + +## Issue tracker +There's an issue tracker at ticket.coreboot.org for the coreboot codebase, +associated projects like libpayload and the coreboot infrastructure. -- To view, visit https://review.coreboot.org/c/coreboot/+/35806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib249d5c6f2431336a01850f4a8d708795983e7d3 Gerrit-Change-Number: 35806 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/mb: Link AMD mainboards directly in the big list
by Patrick Georgi (Code Review) 07 Oct '19

07 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35817 ) Change subject: Documentation/mb: Link AMD mainboards directly in the big list ...................................................................... Documentation/mb: Link AMD mainboards directly in the big list Fixes an issue with amd/index.md not being part of a toctree Change-Id: Id419695d24a49951afb844c81cc0951d6920e0d2 Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- D Documentation/mainboard/amd/index.md M Documentation/mainboard/index.md 2 files changed, 3 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35817/1 diff --git a/Documentation/mainboard/amd/index.md b/Documentation/mainboard/amd/index.md deleted file mode 100644 index 7a33de8..0000000 --- a/Documentation/mainboard/amd/index.md +++ /dev/null @@ -1,7 +0,0 @@ -# AMD platforms documentation - -This section contains documentation about specific AMD mainboards. - -## Mainboard - -- [padmelon](padmelon/padmelon.md) diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 9531940..83189757 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -2,6 +2,9 @@ This section contains documentation about coreboot on specific mainboards. +## AMD +- [padmelon](amd/padmelon/padmelon.md) + ## ASRock - [H81M-HDS](asrock/h81m-hds.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/35817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id419695d24a49951afb844c81cc0951d6920e0d2 Gerrit-Change-Number: 35817 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/mb/amd/padmelon: Fix relative link
by Patrick Georgi (Code Review) 07 Oct '19

07 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35816 ) Change subject: Documentation/mb/amd/padmelon: Fix relative link ...................................................................... Documentation/mb/amd/padmelon: Fix relative link Change-Id: I132aed69107153785c5e824108677e60243483ce Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M Documentation/mainboard/amd/padmelon/padmelon.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35816/1 diff --git a/Documentation/mainboard/amd/padmelon/padmelon.md b/Documentation/mainboard/amd/padmelon/padmelon.md index f606f47..20b1b13 100644 --- a/Documentation/mainboard/amd/padmelon/padmelon.md +++ b/Documentation/mainboard/amd/padmelon/padmelon.md @@ -75,6 +75,6 @@ [Merlin Falcon BKDG][merlinfalcon] -[merlinfalcon]: ../../soc/amd/family15h.md +[merlinfalcon]: ../../../soc/amd/family15h.md [padmelon]: padmelon.jpg [padmelon_io]: padmelon_io.jpg -- To view, visit https://review.coreboot.org/c/coreboot/+/35816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I132aed69107153785c5e824108677e60243483ce Gerrit-Change-Number: 35816 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: remove invalid fragment type specifier
by Patrick Georgi (Code Review) 07 Oct '19

07 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35815 ) Change subject: Documentation: remove invalid fragment type specifier ...................................................................... Documentation: remove invalid fragment type specifier Change-Id: I1a07180532c6fa7c7ac487e39632438eef3b34e7 Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M Documentation/superio/common/ssdt.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/35815/1 diff --git a/Documentation/superio/common/ssdt.md b/Documentation/superio/common/ssdt.md index 4353cde..f2bb334 100644 --- a/Documentation/superio/common/ssdt.md +++ b/Documentation/superio/common/ssdt.md @@ -19,7 +19,7 @@ This example is based on AST2400. -```code +``` # Add a "container" for proper ACPI code generation chip superio/common device pnp 2e.0 on # just for the base device, not for the LDNs -- To view, visit https://review.coreboot.org/c/coreboot/+/35815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a07180532c6fa7c7ac487e39632438eef3b34e7 Gerrit-Change-Number: 35815 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Fix typo
by Patrick Georgi (Code Review) 07 Oct '19

07 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35814 ) Change subject: Documentation: Fix typo ...................................................................... Documentation: Fix typo Change-Id: I832ff41a322081d3bae80df463659ec6ffffcd34 Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M Documentation/getting_started/architecture.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35814/1 diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md index 6ef6359..d037f75 100644 --- a/Documentation/getting_started/architecture.md +++ b/Documentation/getting_started/architecture.md @@ -1,6 +1,6 @@ # coreboot architecture -## Overwiew +## Overview ![][architecture] [architecture]: comparision_coreboot_uefi.svg -- To view, visit https://review.coreboot.org/c/coreboot/+/35814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I832ff41a322081d3bae80df463659ec6ffffcd34 Gerrit-Change-Number: 35814 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: start documenting our services
by Patrick Georgi (Code Review) 07 Oct '19

07 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35805 ) Change subject: Documentation: start documenting our services ...................................................................... Documentation: start documenting our services Change-Id: I4d687d13e8d47e3e3e6f319b9117d3c4f31caa78 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- A Documentation/community/services.md M Documentation/index.md 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/35805/1 diff --git a/Documentation/community/services.md b/Documentation/community/services.md new file mode 100644 index 0000000..afdf040 --- /dev/null +++ b/Documentation/community/services.md @@ -0,0 +1,35 @@ +# Accounts on coreboot.org + +There are a number of places where you can benefit from creaating an account +in our community. Since there is no single sign-on system in place (at this +time), they come with their own setup routines. + +## Gerrit code review +We exchange and review patches to the code using the Gerrit code review +system that is available on review.coreboot.org. + +It allows logging in with a Google or GitHub account using OAuth2 as well +as with any OpenID provider that you may already use. + +On https://review.coreboot.org/settings you can register all your email +addresses you intend to use in the context of coreboot development so that +commits with your email address in them are associated with you properly. + +### https push access +When using the https URLs to git repositories, you can push with the "HTTP +Credentials" you can have Gerrit generate for you on that page. By default, +git uses `$HOME/.netrc` for http authentication data, so add a line there +stating: + + machine review.coreboot.org login (your-user-name) password (your-password) + +### Gerrit user avatar +To setup an avatar to show in Gerrit, clone the avatars repository at +https://review.coreboot.org/gerrit-avatars.git and add a file named +$your-user-ID.jpg (the user ID is a number shown on the settings page linked +above). The image must be provided in JPEG format, must be square and at most +50000 bytes. + +After you push for review, the system will automatically verify your change +and, if adhering to these constraints, approve it. You can then immediately +submit it. diff --git a/Documentation/index.md b/Documentation/index.md index 39c8d11..e52c78a 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -166,6 +166,7 @@ * [Project Ideas](contributing/project_ideas.md) * [Code of Conduct](community/code_of_conduct.md) * [Community forums](community/forums.md) +* [Project services](commmunity/services.md) * [coreboot at conferences](community/conferences.md) * [Payloads](payloads.md) * [Distributions](distributions.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/35805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d687d13e8d47e3e3e6f319b9117d3c4f31caa78 Gerrit-Change-Number: 35805 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Update list of release notes
by Patrick Georgi (Code Review) 07 Oct '19

07 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35811 ) Change subject: Documentation: Update list of release notes ...................................................................... Documentation: Update list of release notes Change-Id: I963be1536be5155a114eef1149fdd8c5a067eff8 Signed-off-by: Patrick Georgi <patrick(a)georgi.software> --- M Documentation/releases/index.md 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35811/1 diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index ccbd6fe..c49a61a 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -10,6 +10,7 @@ * [4.7 - January 2018](coreboot-4.7-relnotes.md) * [4.8 - May 2018](coreboot-4.8.1-relnotes.md) * [4.9 - December 2018](coreboot-4.9-relnotes.md) +* [4.10 - July 2019](coreboot-4.10-relnotes.md) The checklist contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -21,4 +22,4 @@ ---------------- Please add to the release notes as changes are added: -* [4.10 - April 2019](coreboot-4.10-relnotes.md) +* [4.11 - October 2019](coreboot-4.11-relnotes.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/35811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I963be1536be5155a114eef1149fdd8c5a067eff8 Gerrit-Change-Number: 35811 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/hp: Add HP Compaq Pro 6300 SFF
by Angel Pons (Code Review) 06 Oct '19

06 Oct '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35829 ) Change subject: [WIP] mb/hp: Add HP Compaq Pro 6300 SFF ...................................................................... [WIP] mb/hp: Add HP Compaq Pro 6300 SFF Worked on the first try :-) Will be marked as WIP until I stop being screamed at by the CPU fan. Change-Id: I4c1a2785d0480a561e5c05471ec572f85f41004c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/hp/compaq_pro_6300_sff/Kconfig A src/mainboard/hp/compaq_pro_6300_sff/Kconfig.name A src/mainboard/hp/compaq_pro_6300_sff/Makefile.inc A src/mainboard/hp/compaq_pro_6300_sff/README.txt A src/mainboard/hp/compaq_pro_6300_sff/acpi/ec.asl A src/mainboard/hp/compaq_pro_6300_sff/acpi/platform.asl A src/mainboard/hp/compaq_pro_6300_sff/acpi/superio.asl A src/mainboard/hp/compaq_pro_6300_sff/acpi_tables.c A src/mainboard/hp/compaq_pro_6300_sff/board_info.txt A src/mainboard/hp/compaq_pro_6300_sff/data.vbt A src/mainboard/hp/compaq_pro_6300_sff/devicetree.cb A src/mainboard/hp/compaq_pro_6300_sff/dsdt.asl A src/mainboard/hp/compaq_pro_6300_sff/gma-mainboard.ads A src/mainboard/hp/compaq_pro_6300_sff/gpio.c A src/mainboard/hp/compaq_pro_6300_sff/hda_verb.c A src/mainboard/hp/compaq_pro_6300_sff/mainboard.c A src/mainboard/hp/compaq_pro_6300_sff/romstage.c 17 files changed, 915 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35829/1 diff --git a/src/mainboard/hp/compaq_pro_6300_sff/Kconfig b/src/mainboard/hp/compaq_pro_6300_sff/Kconfig new file mode 100644 index 0000000..3973a79 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/Kconfig @@ -0,0 +1,39 @@ +if BOARD_HP_COMPAQ_PRO_6300_SFF + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select SUPERIO_NUVOTON_NPCD378 + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select MAINBOARD_USES_IFD_GBE_REGION + +config MAINBOARD_DIR + string + default hp/compaq_pro_6300_sff + +config MAINBOARD_PART_NUMBER + string + default "HP Compaq Pro 6300 SFF" + +config DRAM_RESET_GATE_GPIO # Note: s3resume works with this value + int + default 29 # only GPIO that is GPIO, OUT and HIGH + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/hp/compaq_pro_6300_sff/Kconfig.name b/src/mainboard/hp/compaq_pro_6300_sff/Kconfig.name new file mode 100644 index 0000000..674cb9b --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_COMPAQ_PRO_6300_SFF + bool "HP Compaq Pro 6300 SFF" diff --git a/src/mainboard/hp/compaq_pro_6300_sff/Makefile.inc b/src/mainboard/hp/compaq_pro_6300_sff/Makefile.inc new file mode 100644 index 0000000..ebe01ae --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/compaq_pro_6300_sff/README.txt b/src/mainboard/hp/compaq_pro_6300_sff/README.txt new file mode 100644 index 0000000..5f9b749 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/README.txt @@ -0,0 +1,58 @@ +################################################################################################ +# # +# Dear reviewer reading this, # +# # +# Don't bother telling me this should be in documentation or something like that. Please. # +# This is a scratchpad for my own consumption, and once I am happy with this port I will then # +# document it properly. # +# # +# Thanks for *NOT* spending your time on this file. # +# # +################################################################################################ + + + +This board is called "Edison" and it's Revision A. This is printed out near the PCH, to the +right of the PCIe x1 slot. + +To do internal flashing, one just needs to bridge FDO (2-pin jumper around the midpoint of the +4x USB3 back side connector and the Q75 PCH). + +Working: +- Booting to Linux +- All four DDR3 slots +- Libgfxinit on VGA +- Serial port console via onboard RS232 port +- At least some SATA and USB ports +- S3 suspend and resume +- TPM detection + +NOT WORKING: +- SuperIO-related aspects, as there is no damn datasheet for that piece of cursed sand. + It is a Nuvoton NPCD379, which smells like a NPCD378, thus the latter's code is used for now. + +UNTESTED: +- PS/2 ports +- Parallel port +- The other serial port (likely works just fine) +- Audio +- DisplayPork +- All PCIe/PCI ports (not even tested with vendor firmware yet!!!) +- A true HP power supply (current setup involves two regular ATX PSUs and lots of insanity) +- MEDIA and MEDIA2 headers with coreboot (they are regular USB port pairs) + +TODO: +- Try soldering a PCIe x4 slot instead of the current PCIe x1. Also, SMD capacitors. +- Check if the connector sensing abilities vendor firmware has are implemented with GPIOs. + If these are PCH GPIOs, then identify which is which. +- Is the 2x7 pin header footprint between the PCH and the RTC battery a LPC tap? +- Can the "ROM recovery" header be used to flash in-circuit? Or is it meant to be used with a + second flash chip while disabling the onboard chip? +- Fully describe the front panel button header. Partial mapping: + + 0 2 6 8 + 1 3 5 7 9 + + 2 --> HDD LED --> 0 + 5 --> PWR BTN --> 7 + HDD LED is one of the things that vendor BIOS uses to complain at you. diff --git a/src/mainboard/hp/compaq_pro_6300_sff/acpi/ec.asl b/src/mainboard/hp/compaq_pro_6300_sff/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/acpi/ec.asl diff --git a/src/mainboard/hp/compaq_pro_6300_sff/acpi/platform.asl b/src/mainboard/hp/compaq_pro_6300_sff/acpi/platform.asl new file mode 100644 index 0000000..02a1b54 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/acpi/platform.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK, 1, NotSerialized) +{ + \_SB.PCI0.LPCB.SIO0.SIOW (Arg0) + + Return(Package(){0,0}) +} + +Method(_PTS, 1, NotSerialized) +{ + \_SB.PCI0.LPCB.SIO0.SIOS (Arg0) +} diff --git a/src/mainboard/hp/compaq_pro_6300_sff/acpi/superio.asl b/src/mainboard/hp/compaq_pro_6300_sff/acpi/superio.asl new file mode 100644 index 0000000..630c5e8 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/acpi/superio.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e + +#define SUPERIO_SHOW_SP2 +#define SUPERIO_SHOW_KBC + +#include <superio/nuvoton/npcd378/acpi/superio.asl> + +Scope (\_GPE) +{ + Method (_L08, 0, NotSerialized) + { + \_SB.PCI0.LPCB.SIO0.SIOH () + } + + Method (_L0D, 0, NotSerialized) + { + Notify (\_SB.PCI0.EHC1, 0x02) + Notify (\_SB.PCI0.EHC2, 0x02) + //FIXME: Add GBE device + //Notify (\_SB.PCI0.GBE, 0x02) + } + + Method (_L09, 0, NotSerialized) + { + Notify (\_SB.PCI0.RP01, 0x02) + Notify (\_SB.PCI0.RP02, 0x02) + Notify (\_SB.PCI0.RP03, 0x02) + Notify (\_SB.PCI0.RP04, 0x02) + Notify (\_SB.PCI0.RP05, 0x02) + Notify (\_SB.PCI0.RP06, 0x02) + Notify (\_SB.PCI0.RP07, 0x02) + Notify (\_SB.PCI0.RP08, 0x02) + Notify (\_SB.PCI0.PEGP, 0x02) + } +} diff --git a/src/mainboard/hp/compaq_pro_6300_sff/acpi_tables.c b/src/mainboard/hp/compaq_pro_6300_sff/acpi_tables.c new file mode 100644 index 0000000..8093e10 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/compaq_pro_6300_sff/board_info.txt b/src/mainboard/hp/compaq_pro_6300_sff/board_info.txt new file mode 100644 index 0000000..e2dc085 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://support.hp.com/us-en/product/hp-compaq-pro-6300-small-form-factor-p… +ROM IC: N25Q128..3E +ROM package: SOIC-16 +ROM socketed: no +Flashrom support: yes +Release year: 2013 diff --git a/src/mainboard/hp/compaq_pro_6300_sff/data.vbt b/src/mainboard/hp/compaq_pro_6300_sff/data.vbt new file mode 100644 index 0000000..dc63061 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/data.vbt Binary files differ diff --git a/src/mainboard/hp/compaq_pro_6300_sff/devicetree.cb b/src/mainboard/hp/compaq_pro_6300_sff/devicetree.cb new file mode 100644 index 0000000..293533f --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/devicetree.cb @@ -0,0 +1,186 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0x0 on + device pci 00.0 on # Host bridge + end + device pci 01.0 on # PEG + end + device pci 02.0 on # iGPU + end + subsystemid 0x103c 0x339a inherit + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00fc0801" + #register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x10" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + end + device pci 16.0 on # Management Engine Interface 1 + end + device pci 16.1 on # Management Engine Interface 2 + end + device pci 16.2 on # Management Engine IDE-R + end + device pci 16.3 on # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + end + device pci 1b.0 on # High Definition Audio controller + end + device pci 1c.0 on # PCIe Port #1 + end + device pci 1c.1 on # PCIe Port #2 + end + device pci 1c.2 on # PCIe Port #3 + end + device pci 1c.3 on # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + end + device pci 1c.5 on # PCIe Port #6 + end + device pci 1c.6 on # PCIe Port #7 + end + device pci 1c.7 on # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + end + device pci 1e.0 on # PCI bridge + end + device pci 1f.0 on # LPC bridge0x1495 + chip superio/nuvoton/npcd378 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off # Parallel port + # global + + # serialice: Vendor writes: + #irq 0x14 = 0x9c + #irq 0x1c = 0xa8 + #irq 0x1d = 0x08 + #irq 0x22 = 0x3f + #irq 0x1a = 0xb0 + # dumped from superiotool: + #irq 0x1b = 0x1e + #irq 0x27 = 0x08 + #irq 0x2a = 0x20 + #irq 0x2d = 0x01 + # parallel port + #io 0x60 = 0x378 + #irq 0x70 = 0x07 + #drq 0x74 = 0x01 + end + device pnp 2e.2 off # COM1 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off # LED control + #io 0x60 = 0x600 + # IOBASE[0h] = bit0 LED red / green + # IOBASE[0h] = bit1-4 LED PWM duty cycle + # IOBASE[1h] = bit6 SWCC + + #io 0x62 = 0x610 + # IOBASE [0h] = GPES + # IOBASE [1h] = GPEE + # IOBASE [4h:7h] = 32bit upcounter at 1Mhz + # IOBASE [8h:bh] = GPS + # IOBASE [ch:fh] = GPE + end + device pnp 2e.5 on # Mouse + irq 0x70 = 0xc + end + device pnp 2e.6 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 + # serialice: Vendor writes: + drq 0xf0 = 0x40 + end + device pnp 2e.7 off # WDT ? + #io 0x60 = 0x620 + end + device pnp 2e.8 off # HWM + #io 0x60 = 0x800 + # IOBASE[0h:feh] HWM page + # IOBASE[ffh] bit0-bit3 page selector + + #drq 0xf0 = 0x20 + #drq 0xf1 = 0x01 + #drq 0xf2 = 0x40 + #drq 0xf3 = 0x01 + + #drq 0xf4 = 0x66 + #drq 0xf5 = 0x67 + #drq 0xf6 = 0x66 + #drq 0xf7 = 0x01 + end + device pnp 2e.f off # GPIO OD ? + #drq 0xf1 = 0x97 + #drq 0xf2 = 0x01 + #drq 0xf5 = 0x08 + #drq 0xfe = 0x80 + end + device pnp 2e.15 off # BUS ? + #io 0x60 = 0x0680 + #io 0x62 = 0x0690 + end + device pnp 2e.1c off # Suspend Control ? + #io 0x60 = 0x640 + # writing to IOBASE[5h] + # 0x0: Power off + # 0x9: Power off and bricked until CMOS battery removed + end + device pnp 2e.1e off # GPIO ? + #io 0x60 = 0x660 + #drq 0xf4 = 0x01 + # skip the following, as it + # looks like remapped registers + #drq 0xf5 = 0x06 + #drq 0xf6 = 0x60 + #drq 0xfe = 0x03 + end + end + chip drivers/pc80/tpm + device pnp 4e.0 on end + end + end + device pci 1f.2 on # SATA Controller 1 + end + device pci 1f.3 on # SMBus + end + device pci 1f.4 on # Performance counters + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 on # Thermal + end + end + end +end diff --git a/src/mainboard/hp/compaq_pro_6300_sff/dsdt.asl b/src/mainboard/hp/compaq_pro_6300_sff/dsdt.asl new file mode 100644 index 0000000..7bbcd71 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/dsdt.asl @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/compaq_pro_6300_sff/gma-mainboard.ads b/src/mainboard/hp/compaq_pro_6300_sff/gma-mainboard.ads new file mode 100644 index 0000000..502b8c1 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: Only DP and VGA exist + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/compaq_pro_6300_sff/gpio.c b/src/mainboard/hp/compaq_pro_6300_sff/gpio.c new file mode 100644 index 0000000..c9b665a --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/gpio.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio71 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/compaq_pro_6300_sff/hda_verb.c b/src/mainboard/hp/compaq_pro_6300_sff/hda_verb.c new file mode 100644 index 0000000..7c9c192 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/hda_verb.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ + 0x103c339a, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c339a), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x90170110), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x02a11c3f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x01813c30), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x598301f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* NID 0x21. */ + AZALIA_PIN_CFG(0x0, 0x21, 0x0221102f), + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x1458a002, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x2, 0x11, 0x411110f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x2, 0x1f, 0x41c46060), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/compaq_pro_6300_sff/mainboard.c b/src/mainboard/hp/compaq_pro_6300_sff/mainboard.c new file mode 100644 index 0000000..9571fa4 --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/mainboard.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values, or kill the entire file. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/compaq_pro_6300_sff/romstage.c b/src/mainboard/hp/compaq_pro_6300_sff/romstage.c new file mode 100644 index 0000000..050024f --- /dev/null +++ b/src/mainboard/hp/compaq_pro_6300_sff/romstage.c @@ -0,0 +1,77 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <superio/nuvoton/npcd378/npcd378.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1409); + + /* COMA: 3F8h, COMB: 2F8h */ + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + /* BTX mainboard: Reversed mapping */ + read_spd(&spd[3], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[0], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c1a2785d0480a561e5c05471ec572f85f41004c Gerrit-Change-Number: 35829 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019