coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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1921 discussions

Change in coreboot[master]: build: Mark bootblock files on x86 as IBB
by Werner Zeh (Code Review) 08 Oct '19

08 Oct '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31497 ) Change subject: build: Mark bootblock files on x86 as IBB ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/31497/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/31497/13//COMMIT_MSG@10 PS13, Line 10: be used That is duplicated. -- To view, visit https://review.coreboot.org/c/coreboot/+/31497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Gerrit-Change-Number: 31497 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 08 Oct 2019 05:49:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/kohaku: Assign GPP_A19 as reset_gpio of stylus device
by shkim (Code Review) 08 Oct '19

08 Oct '19

shkim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35748 ) Change subject: mb/google/kohaku: Assign GPP_A19 as reset_gpio of stylus device ...................................................................... mb/google/kohaku: Assign GPP_A19 as reset_gpio of stylus device Applying reset_gpio config of stylus for kohaku. GPP_A19 has been assigned in latest schematics. BUG=b:141914474 BRANCH=none TEST=verified stylus works internally Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> Change-Id: I61f0f9a4378f47bf455f0726d44beeaf2f67197b --- M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 6 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35748/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 9654388..84270b3 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -23,16 +23,16 @@ PAD_NC(GPP_A0, NONE), /* A6 : SERIRQ ==> NC */ PAD_NC(GPP_A6, NONE), - /* A10 : PEN_RESET_ODL */ - PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A10 : CLKOUT_LPC1 ==> NC */ + PAD_NC(GPP_A10, NONE), /* A16 : EMR_GARAGE_DET (notification) */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A16, NONE, PLTRST), /* A17 : PIRQA# ==> NC */ PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> NC */ PAD_NC(GPP_A18, NONE), - /* A19 : ISH_GP1 ==> NC */ - PAD_NC(GPP_A19, NONE), + /* A19 : PEN_RESET_ODL */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), /* A20 : ISH_GP2 ==> NC */ PAD_NC(GPP_A20, NONE), /* A22 : ISH_GP4 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 8c7bb1f..37914fa 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -189,10 +189,8 @@ register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C15)" - # TODO: We can't use GPP_A10 as reset_gpio due to its voltage level, - # so we need to reassign it or remove it. - #register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A10)" - #register "generic.reset_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A19)" + register "generic.reset_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x09 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/35748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61f0f9a4378f47bf455f0726d44beeaf2f67197b Gerrit-Change-Number: 35748 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Hung-Te Lin (Code Review) 08 Oct '19

08 Oct '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35775 ) Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/35775/10/src/soc/mediatek/mt8183/i… File src/soc/mediatek/mt8183/include/soc/dramc_param.h: https://review.coreboot.org/c/coreboot/+/35775/10/src/soc/mediatek/mt8183/i… PS10, Line 68: dramc_param I think usually for 'ops' (see depthcharge) we won't put whole prarm struct here. It should be passed as a separate param, or a pointer to the real struct. -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 10 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Oct 2019 04:36:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Yu-Ping Wu (Code Review) 08 Oct '19

08 Oct '19

Hello Julius Werner, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35775 to look at the new patch set (#10). Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... soc/mediatek/mt8183: Add the shared 'dramc_param' module The dramc_param module simplifies the communication between coreboot and MTK DRAM full calibration blob, and is shared by both implementations to ensure the same format of parameters. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_param.c A src/soc/mediatek/mt8183/include/soc/dramc_param.h 3 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35775/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 10 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/hatch: Add option to enable WiFi SAR configs
by Kane Chen (Code Review) 08 Oct '19

08 Oct '19

Kane Chen has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35789 ) Change subject: mb/google/hatch: Add option to enable WiFi SAR configs ...................................................................... Abandoned This CL not required as mb/google/hatch is shared by different variants and so the the wifi sar table will not work for all. -- To view, visit https://review.coreboot.org/c/coreboot/+/35789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bb36dc2a68a3835d7126406c3403b2c0510202d Gerrit-Change-Number: 35789 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/drallion: Remove touch screen detect.
by JoeJ Chang (Code Review) 08 Oct '19

08 Oct '19

JoeJ Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35644 ) Change subject: mb/google/drallion: Remove touch screen detect. ...................................................................... mb/google/drallion: Remove touch screen detect. GPP_B4 is always high due to the cable issue, remove the HW strap detect temporarily. BUG=b:141722840 Signed-off-by: JoeJ Chang <joej_chang(a)compal.corp-partner.google.com> Change-Id: I8781f36d87ece1980137cddde9fe2b6e3f3d5636 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/35644/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d824a55..89e2df8 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -344,8 +344,6 @@ register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - register "generic.device_present_gpio" = "GPP_B4" - register "generic.device_present_gpio_invert" = "1" device i2c 10 on end end chip drivers/i2c/generic @@ -358,8 +356,6 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" - register "device_present_gpio" = "GPP_B4" - register "device_present_gpio_invert" = "1" device i2c 34 on end end end # I2C #0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8781f36d87ece1980137cddde9fe2b6e3f3d5636 Gerrit-Change-Number: 35644 Gerrit-PatchSet: 1 Gerrit-Owner: JoeJ Chang <joej_chang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mediatek/mt8183: Set DRAM voltage for each DRAM frequency
by Huayang Duan (Code Review) 08 Oct '19

08 Oct '19

Huayang Duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM voltage for each DRAM frequency ...................................................................... Patch Set 12: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 12 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 08 Oct 2019 01:25:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch: Preserve MRC training data across FW update
by Shelley Chen (Code Review) 07 Oct '19

07 Oct '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35803 ) Change subject: mb/google/hatch: Preserve MRC training data across FW update ...................................................................... mb/google/hatch: Preserve MRC training data across FW update Enable RW_RESERVE so that we retain the memory training data upon a FW update. BUG=b:142084637 BRANCH=None TEST=flash RW_SECTION_A, RW_SECTION_B, and WP_RO sections and make sure memory training doesn't occur on following bootup. Change-Id: Ia5eb228b1f665a8371982544723dab3dfc40d401 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/chromeos.fmd 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35803/1 diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 393ac80..07c739c 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -19,9 +19,11 @@ RW_FWID_B@0x3dffc0 0x40 } RW_MISC@0x17c0000 0x40000 { - UNIFIED_MRC_CACHE@0x0 0x30000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x20000 + RW_PRESERVE(PRESERVE) { + UNIFIED_MRC_CACHE@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } } RW_ELOG(PRESERVE)@0x30000 0x4000 RW_SHARED@0x34000 0x4000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/35803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5eb228b1f665a8371982544723dab3dfc40d401 Gerrit-Change-Number: 35803 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/fleex: Adjust I2C0 CLK to meet spec
by John Su (Code Review) 07 Oct '19

07 Oct '19

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35788 ) Change subject: mb/google/octopus/variants/fleex: Adjust I2C0 CLK to meet spec ...................................................................... mb/google/octopus/variants/fleex: Adjust I2C0 CLK to meet spec After adjustment on fleex I2C0 CLK: 389.9 KHz BUG=b:141729962 BRANCH=master TEST=emerge-octopus coreboot chromeos-bootimage measure by scope with fleex. Change-Id: I6a30257b7978cc8899a55f9fd6ffffe01cb2a851 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/fleex/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35788/1 diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index da4e701..1d1a67a 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -63,6 +63,8 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 25, + .fall_time_ns = 52, }, .i2c[5] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/35788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a30257b7978cc8899a55f9fd6ffffe01cb2a851 Gerrit-Change-Number: 35788 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Capitalize Super I/O
by HAOUAS Elyes (Code Review) 07 Oct '19

07 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35541 ) Change subject: src: Capitalize Super I/O ...................................................................... src: Capitalize Super I/O Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Documentation/mainboard/asrock/h81m-hds.md M Documentation/mainboard/asus/p8h61-m_lx.md M Documentation/mainboard/asus/p8h61-m_pro.md M Documentation/mainboard/supermicro/x10slm-f.md M src/device/pnp_device.c M src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl M src/superio/acpi/pnp_generic.asl M src/superio/acpi/pnp_kbc.asl M src/superio/acpi/pnp_uart.asl 9 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35541/1 diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index df00abd..6a0da5b 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -70,7 +70,7 @@ - The VGA port doesn't work until the OS reinitialises the display. - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, but the required driver doesn't exist in coreboot. The `coretemp` driver can still be used for accurate CPU temperature readings from an OS. diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md index 5eb7193..212ed97 100644 --- a/Documentation/mainboard/asus/p8h61-m_lx.md +++ b/Documentation/mainboard/asus/p8h61-m_lx.md @@ -49,7 +49,7 @@ suspend. - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, whose complete initialisation is not publicly documented. The `coretemp` driver can still be used for accurate CPU temperature readings. diff --git a/Documentation/mainboard/asus/p8h61-m_pro.md b/Documentation/mainboard/asus/p8h61-m_pro.md index 169678e..713c794 100644 --- a/Documentation/mainboard/asus/p8h61-m_pro.md +++ b/Documentation/mainboard/asus/p8h61-m_pro.md @@ -46,7 +46,7 @@ ## Known issues - There is no automatic, OS-independent fan control. This is because - the super I/O hardware monitor can only obtain valid CPU temperature + the Super I/O hardware monitor can only obtain valid CPU temperature readings from the PECI agent, whose complete initialisation is not publicly documented. The `coretemp` driver can still be used for accurate CPU temperature readings. diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md index 7fae61f..acb2c84 100644 --- a/Documentation/mainboard/supermicro/x10slm-f.md +++ b/Documentation/mainboard/supermicro/x10slm-f.md @@ -168,7 +168,7 @@ - VGA graphics - disabling VGA graphics using the jumper - hiding the AST2400 using the CMOS setting -- super I/O hardware monitor (see [Known issues](#known-issues)) +- Super I/O hardware monitor (see [Known issues](#known-issues)) - initialisation with Haswell MRC version 1.6.1 build 2 - flashrom under coreboot - Wake-on-LAN diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 164fc19..28a45d0 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -109,7 +109,7 @@ static void pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - /* The PNP_MSC super IO registers have the IRQ flag set. If no + /* The PNP_MSC Super IO registers have the IRQ flag set. If no value is assigned in the devicetree, the corresponding PNP_MSC register doesn't get written, which should be printed as warning and not as error. */ diff --git a/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl b/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl index d1b2193..9de6da0 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl +++ b/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl @@ -1 +1 @@ -/* no super i/o */ +/* no Super I/O */ diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index 980404e..dbae2ac 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -20,9 +20,9 @@ * * Controlled by the following preprocessor defines: * - * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) + * SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required) * SUPERIO_PNP_HID The EisaId string that identifies this device (optional) - * SUPERIO_PNP_LDN The logical device number on the super i/o + * SUPERIO_PNP_LDN The logical device number on the Super I/O * chip for this device (required) * SUPERIO_PNP_DDN A string literal that identifies the dos device * name (DDN) of this device (e.g. "COM1", optional) diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl index cbcfd55..541dce3 100644 --- a/src/superio/acpi/pnp_kbc.asl +++ b/src/superio/acpi/pnp_kbc.asl @@ -22,8 +22,8 @@ * * Controlled by the following preprocessor defines: * - * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) - * SUPERIO_KBC_LDN The logical device number on the super i/o + * SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required) + * SUPERIO_KBC_LDN The logical device number on the Super I/O * chip for this keyboard controller (required) * SUPERIO_KBC_PS2M If defined, PS/2 mouse support is included in * the KBC_LDN. Mouse irq is set at IRQ1 of the diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index f42cc42..3cbe65a 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -21,8 +21,8 @@ * * Controlled by the following preprocessor defines: * - * SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required) - * SUPERIO_UART_LDN The logical device number on the super i/o + * SUPERIO_CHIP_NAME The name of the Super I/O chip (unique, required) + * SUPERIO_UART_LDN The logical device number on the Super I/O * chip for this UART (required) * SUPERIO_UART_DDN A string literal that identifies the dos device * name (DDN) of this uart (e.g. "COM1", optional) -- To view, visit https://review.coreboot.org/c/coreboot/+/35541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5 Gerrit-Change-Number: 35541 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019