coreboot-gerrit October 2019

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Change in coreboot[master]: cpu/intel/model_2065x/bootblock: Remove dead code
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35810 ) Change subject: cpu/intel/model_2065x/bootblock: Remove dead code ...................................................................... cpu/intel/model_2065x/bootblock: Remove dead code This codepath is never takes as it checks if the CPU is at least ivybridge. Change-Id: Id064385f0c8bb0b094714129df6d8ba36c87a307 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_2065x/bootblock.c 1 file changed, 0 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/35810/1 diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index 273c193..399f5e0 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -57,60 +57,8 @@ wrmsr(MTRR_DEF_TYPE_MSR, msr); } -static void set_flex_ratio_to_tdp_nominal(void) -{ - msr_t flex_ratio, msr; - u32 soft_reset; - u8 nominal_ratio; - - /* Minimum CPU revision for configurable TDP support */ - if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) - return; - - /* Check for Flex Ratio support */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; - - /* Check for >0 configurable TDPs */ - msr = rdmsr(MSR_PLATFORM_INFO); - if (((msr.hi >> 1) & 3) == 0) - return; - - /* Use nominal TDP ratio for flex ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - nominal_ratio = msr.lo & 0xff; - - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - - /* Set flex ratio to nominal TDP ratio */ - flex_ratio.lo &= ~0xff00; - flex_ratio.lo |= nominal_ratio << 8; - flex_ratio.lo |= FLEX_RATIO_LOCK; - wrmsr(MSR_FLEX_RATIO, flex_ratio); - - /* Set flex ratio in soft reset data register bits 11:6. - * RCBA region is enabled in southbridge bootblock */ - soft_reset = RCBA32(SOFT_RESET_DATA); - soft_reset &= ~(0x3f << 6); - soft_reset |= (nominal_ratio & 0x3f) << 6; - RCBA32(SOFT_RESET_DATA) = soft_reset; - - /* Set soft reset control to use register value */ - RCBA32_OR(SOFT_RESET_CTRL, 1); - - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); -} - static void bootblock_cpu_init(void) { - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); enable_rom_caching(); intel_update_microcode_from_cbfs(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id064385f0c8bb0b094714129df6d8ba36c87a307 Gerrit-Change-Number: 35810 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/{lenovo/x201,packardbell/ms2290}: Remove unused APCI symbols
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35804 ) Change subject: mb/{lenovo/x201,packardbell/ms2290}: Remove unused APCI symbols ...................................................................... mb/{lenovo/x201,packardbell/ms2290}: Remove unused APCI symbols Change-Id: I3a3174cf20cea60d8b2c4d0311a48ce9ffe1a8a1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/acpi/platform.asl M src/mainboard/packardbell/ms2290/acpi/platform.asl 2 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35804/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 7d7013b..167fe03 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -14,10 +14,6 @@ * GNU General Public License for more details. */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - /* The APM port can be used for generating software SMIs */ OperationRegion (APMP, SystemIO, 0xb2, 2) diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 9812d14..21d8115 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -14,10 +14,6 @@ * GNU General Public License for more details. */ -/* These come from the dynamically created CPU SSDT */ -External(PDC0) -External(PDC1) - /* The APM port can be used for generating software SMIs */ OperationRegion (APMP, SystemIO, 0xb2, 2) -- To view, visit https://review.coreboot.org/c/coreboot/+/35804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a3174cf20cea60d8b2c4d0311a48ce9ffe1a8a1 Gerrit-Change-Number: 35804 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: nb/intel/nehalem: Don't run graphic init on S3 resume
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35773 ) Change subject: nb/intel/nehalem: Don't run graphic init on S3 resume ...................................................................... nb/intel/nehalem: Don't run graphic init on S3 resume The assumption is made that an ACPI aware an OS does not rely on firmware to initialize the display. TESTED on a Lenovo Thinkpad X201 with Linux 5.2, display still works after S3, more than 200ms in time saved (dropped from 411ms to 182ms in total in one test). Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35773 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/nehalem/gma.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 4333307..903ee27 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -176,7 +176,8 @@ if (!gtt_res || !gtt_res->base) return; - if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + if (!acpi_is_wakeup_s3() && + CONFIG(MAINBOARD_USE_LIBGFXINIT)) { struct northbridge_intel_nehalem_config *conf = dev->chip_info; int lightup_ok; printk(BIOS_SPEW, "Initializing VGA without OPROM."); -- To view, visit https://review.coreboot.org/c/coreboot/+/35773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f Gerrit-Change-Number: 35773 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: nb/intel/nehalem: Move romstage boilerplate in a common location
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35771 ) Change subject: nb/intel/nehalem: Move romstage boilerplate in a common location ...................................................................... nb/intel/nehalem: Move romstage boilerplate in a common location Move the mainboard_romstage_entry to a common location and provide mainboard specific callbacks. Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/northbridge/intel/nehalem/Makefile.inc M src/northbridge/intel/nehalem/nehalem.h A src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/pch.h 6 files changed, 148 insertions(+), 204 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35771/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8a75ae4..1440c19 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -19,24 +19,12 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ops.h> -#include <device/pci_def.h> -#include <cpu/x86/lapic.h> -#include <romstage_handoff.h> -#include <console/console.h> -#include <arch/romstage.h> #include <ec/acpi/ec.h> -#include <timestamp.h> -#include <arch/acpi.h> -#include "dock.h" #include <southbridge/intel/ibexpeak/pch.h> -#include <southbridge/intel/common/gpio.h> #include <northbridge/intel/nehalem/nehalem.h> -#include <northbridge/intel/nehalem/raminit.h> -#include <southbridge/intel/ibexpeak/me.h> - -static void pch_enable_lpc(void) +void mainboard_lpc_init(void) { /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ @@ -59,6 +47,9 @@ pci_write_config32(PCH_LPC_DEV, ETR3, pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); + + /* Enable USB Power. We need to do it early for usbdebug to work. */ + ec_set_bit(0x3b, 4); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -79,22 +70,6 @@ { 1, IF1_55F, 7 }, }; -static void rcba_config(void) -{ - southbridge_configure_default_intmap(); - - /* Must set BIT0 (hiders performance counters PCI), - BIT5-12 are to disable UHCI devices that are not present in - end user devices anyway. */ - RCBA32(FD) = (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) - | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 28) | 1; - - /* Set reserved bit to 1 */ - RCBA32(FD2) = 1; - - early_usb_init(mainboard_usb_ports); -} - static void set_fsb_frequency(void) { u8 block[5]; @@ -106,86 +81,18 @@ smbus_block_write(0x69, 0, 5, block); } -void mainboard_romstage_entry(void) +void mainboard_pre_raminit(void) { - u32 reg32; - int s3resume = 0; - const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; - enable_lapic(); - - nehalem_early_initialization(NEHALEM_MOBILE); - - pch_enable_lpc(); - - /* Enable USB Power. We need to do it early for usbdebug to work. */ - ec_set_bit(0x3b, 4); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - pch_setup_cir(NEHALEM_MOBILE); - - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - console_init(); - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - printk(BIOS_DEBUG, "a2: %02x\n", reg8); - if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } - } - } - - /* Enable SMBUS. */ - enable_smbus(); - outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, DEFAULT_GPIOBASE | 0x3a); outb(0x50, 0x15ec); outb(inb(0x15ee) & 0x70, 0x15ee); - early_thermal_init(); - - timestamp_add_now(TS_BEFORE_INITRAM); - - chipset_init(s3resume); - set_fsb_frequency(); +} - raminit(s3resume, spd_addrmap); - - timestamp_add_now(TS_AFTER_INITRAM); - - intel_early_me_status(); - - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - - romstage_handoff_init(s3resume); +void mainboard_get_spd_map(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x51; } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 5f909d4..b25676b 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -17,25 +17,12 @@ */ #include <stdint.h> -#include <arch/io.h> #include <device/pci_ops.h> -#include <device/pci_def.h> -#include <cpu/x86/lapic.h> -#include <romstage_handoff.h> -#include <console/console.h> -#include <arch/romstage.h> -#include <ec/acpi/ec.h> -#include <timestamp.h> -#include <arch/acpi.h> -#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> -#include <northbridge/intel/nehalem/raminit.h> -#include <southbridge/intel/ibexpeak/me.h> - -static void pch_enable_lpc(void) +void mainboard_lpc_init(void) { /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, @@ -75,95 +62,12 @@ { 1, IF1_55F, 7 }, }; -static void rcba_config(void) +void mainboard_pre_raminit(void) { - southbridge_configure_default_intmap(); - - /* Must set BIT0 (hiders performance counters PCI), - BIT5-12 are to disable UHCI devices that are not present in - end user devices anyway. */ - RCBA32(FD) |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) - | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 28) | 1; - - /* Set reserved bit to 1 */ - RCBA32(FD2) = 1; - - early_usb_init(mainboard_usb_ports); } -void mainboard_romstage_entry(void) +void mainboard_get_spd_map(u8 *spd_addrmap) { - u32 reg32; - int s3resume = 0; - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - - /* SERR pin is confused on reset. Clear NMI. */ - outb(4, 0x61); - outb(0, 0x61); - - enable_lapic(); - - nehalem_early_initialization(NEHALEM_MOBILE); - - pch_enable_lpc(); - - /* Enable GPIOs */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - pch_setup_cir(NEHALEM_MOBILE); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - console_init(); - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - printk(BIOS_DEBUG, "a2: %02x\n", reg8); - if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } - } - } - - /* Enable SMBUS. */ - enable_smbus(); - - early_thermal_init(); - - timestamp_add_now(TS_BEFORE_INITRAM); - - chipset_init(s3resume); - raminit(s3resume, spd_addrmap); - - timestamp_add_now(TS_AFTER_INITRAM); - - intel_early_me_status(); - - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - - romstage_handoff_init(s3resume); + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; } diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 180cc09..3b12bb5 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += raminit.c romstage-y += raminit_tables.c romstage-y += early_init.c +romstage-y += romstage.c smm-y += finalize.c diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 53743ec..bff5595 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -256,6 +256,8 @@ int bridge_silicon_revision(void); void nehalem_early_initialization(int chipset_type); void nehalem_late_initialization(void); +void mainboard_pre_raminit(void); +void mainboard_get_spd_map(u8 *spd_addrmap); #endif /* !__SMM__ */ diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c new file mode 100644 index 0000000..7d00e79 --- /dev/null +++ b/src/northbridge/intel/nehalem/romstage.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <console/console.h> +#include <cf9_reset.h> +#include <device/pci_ops.h> +#include <cpu/x86/lapic.h> +#include <timestamp.h> +#include <romstage_handoff.h> +#include "nehalem.h" +#include <arch/romstage.h> +#include <device/pci_def.h> +#include <device/device.h> +#include <northbridge/intel/nehalem/chip.h> +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/ibexpeak/me.h> +#include <southbridge/intel/common/pmclib.h> +#include <southbridge/intel/common/gpio.h> + +/* Platform has no romstage entry point under mainboard directory, + * so this one is named with prefix mainboard. + */ +void mainboard_romstage_entry(void) +{ + u32 reg32; + int s3resume = 0; + u8 spd_addrmap[4] = {}; + + enable_lapic(); + + /* TODO, make this configurable */ + nehalem_early_initialization(NEHALEM_MOBILE); + + /* mainboard_lpc_init */ + mainboard_lpc_init(); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&mainboard_gpio_map); + + /* TODO, make this configurable */ + pch_setup_cir(NEHALEM_MOBILE); + + southbridge_configure_default_intmap(); + + /* Must set BIT0 (hiders performance counters PCI), + BIT5-12 are to disable UHCI devices that are not present in + end user devices anyway. */ + RCBA32(FD) = (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) + | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 28) | 1; + + /* Set reserved bit to 1 */ + RCBA32(FD2) = 1; + + early_usb_init(mainboard_usb_ports); + + /* Initialize console device(s) */ + console_init(); + + /* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + u8 reg8; + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + printk(BIOS_DEBUG, "a2: %02x\n", reg8); + if (!(reg8 & 0x20)) { + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); + } else { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + } else { + printk(BIOS_DEBUG, + "Resume from S3 detected, but disabled.\n"); + } + } + } + + /* Enable SMBUS. */ + enable_smbus(); + + early_thermal_init(); + + timestamp_add_now(TS_BEFORE_INITRAM); + + chipset_init(s3resume); + + mainboard_pre_raminit(); + + mainboard_get_spd_map(spd_addrmap); + + raminit(s3resume, spd_addrmap); + + timestamp_add_now(TS_AFTER_INITRAM); + + intel_early_me_status(); + + if (s3resume) { + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } + + romstage_handoff_init(s3resume); +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 7f360a5..0254325 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -68,6 +68,7 @@ void early_thermal_init(void); void southbridge_configure_default_intmap(void); void pch_setup_cir(int chipset_type); +void mainboard_lpc_init(void); enum current_lookup_idx { IF1_F57 = 0, @@ -87,6 +88,8 @@ enum current_lookup_idx current; int oc_pin; }; + +extern const struct southbridge_usb_port mainboard_usb_ports[14]; void early_usb_init(const struct southbridge_usb_port *portmap); #ifndef __ROMCC__ -- To view, visit https://review.coreboot.org/c/coreboot/+/35771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9 Gerrit-Change-Number: 35771 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: nb/intel/nehalem: Don't link walkcbfs.S in romstage
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35770 ) Change subject: nb/intel/nehalem: Don't link walkcbfs.S in romstage ...................................................................... nb/intel/nehalem: Don't link walkcbfs.S in romstage Change-Id: I5bb0c38353d340cc5d356fba299a4460e3f5bddc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Makefile.inc 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35770/1 diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index ebb7b8b..180cc09 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -26,7 +26,6 @@ romstage-y += raminit.c romstage-y += raminit_tables.c romstage-y += early_init.c -romstage-y += ../../../arch/x86/walkcbfs.S smm-y += finalize.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bb0c38353d340cc5d356fba299a4460e3f5bddc Gerrit-Change-Number: 35770 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35769 ) Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ...................................................................... sb/intel/ibexpeak: Don't clear PMBASE regs in romstage Boots fine without it. Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c 2 files changed, 0 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35769/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 633bb21..8a75ae4 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -95,21 +95,6 @@ early_usb_init(mainboard_usb_ports); } -static inline void write_acpi32(u32 addr, u32 val) -{ - outl(val, DEFAULT_PMBASE | addr); -} - -static inline void write_acpi16(u32 addr, u16 val) -{ - outw(val, DEFAULT_PMBASE | addr); -} - -static inline u32 read_acpi32(u32 addr) -{ - return inl(DEFAULT_PMBASE | addr); -} - static void set_fsb_frequency(void) { u8 block[5]; @@ -180,20 +165,6 @@ outb(0x50, 0x15ec); outb(inb(0x15ee) & 0x70, 0x15ee); - write_acpi16(0x2, 0x0); - write_acpi32(0x28, 0x0); - write_acpi32(0x2c, 0x0); - if (!s3resume) { - read_acpi32(0x4); - read_acpi32(0x20); - read_acpi32(0x34); - write_acpi16(0x0, 0x900); - write_acpi32(0x20, 0xffff7ffe); - write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); - } - early_thermal_init(); timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index e2414bd..5f909d4 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -91,29 +91,6 @@ early_usb_init(mainboard_usb_ports); } -static inline void write_acpi32(u32 addr, u32 val) -{ - outl(val, DEFAULT_PMBASE | addr); -} - -static inline void write_acpi16(u32 addr, u16 val) -{ - outw(val, DEFAULT_PMBASE | addr); -} - -static inline u32 read_acpi32(u32 addr) -{ - return inl(DEFAULT_PMBASE | addr); -} - -// unused func - used for RE -#if 0 -static inline u16 read_acpi16(u32 addr) -{ - return inw(DEFAULT_PMBASE | addr); -} -#endif - void mainboard_romstage_entry(void) { u32 reg32; @@ -169,20 +146,6 @@ /* Enable SMBUS. */ enable_smbus(); - write_acpi16(0x2, 0x0); - write_acpi32(0x28, 0x0); - write_acpi32(0x2c, 0x0); - if (!s3resume) { - read_acpi32(0x4); - read_acpi32(0x20); - read_acpi32(0x34); - write_acpi16(0x0, 0x900); - write_acpi32(0x20, 0xffff7ffe); - write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); - } - early_thermal_init(); timestamp_add_now(TS_BEFORE_INITRAM); -- To view, visit https://review.coreboot.org/c/coreboot/+/35769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673 Gerrit-Change-Number: 35769 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: sb/intel/ibexpeak: Remove undocumented reset defaults from RCBA replay
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35760 ) Change subject: sb/intel/ibexpeak: Remove undocumented reset defaults from RCBA replay ...................................................................... sb/intel/ibexpeak: Remove undocumented reset defaults from RCBA replay The values read back in those ranges are identical before and after this change and it still boots fine. Change-Id: I406510e0573ac97003da7d97181abdfbfd2a872f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c 2 files changed, 0 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/35760/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 6b74cb2..04d1d79 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -91,25 +91,6 @@ /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, - /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, - /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36d0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000, - /* 36e0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000, - /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3700 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3710 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3720 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index de318ec..b4b9755 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -86,25 +86,6 @@ /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, - /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, - /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 36d0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000, - /* 36e0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000, - /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3700 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3710 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3720 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, }; unsigned i; -- To view, visit https://review.coreboot.org/c/coreboot/+/35760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I406510e0573ac97003da7d97181abdfbfd2a872f Gerrit-Change-Number: 35760 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: sb/intel/ibexpeak: Remove handled RCBA entries from replay
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35440 ) Change subject: sb/intel/ibexpeak: Remove handled RCBA entries from replay ...................................................................... sb/intel/ibexpeak: Remove handled RCBA entries from replay The RCBA registers 0x3400-0x3500 are all handled elsewhere in the code, so no need to have a 'replay' of those. The remainder now consist of USB setup and undocumented bits that should likely not be touched at all. Change-Id: I69fc8a5e16f7cf0e1068d0d2ed678a6c2f6e70a9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c 2 files changed, 4 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/35440/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 9d98637..df591cd 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -66,22 +66,6 @@ southbridge_configure_default_intmap(); static const u32 rcba_dump3[] = { - /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, - /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, - /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, - /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, - /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, @@ -120,8 +104,8 @@ }; unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3400) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3400); + RCBA32(4 * i + 0x3500) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3500); } } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index a426d89..644c1c2 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -61,22 +61,6 @@ southbridge_configure_default_intmap(); static const u32 rcba_dump3[] = { - /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, - /* 3410 */ 0x00000c61, 0x00000000, 0x16fc1fe1, 0xbf4f001f, - /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, - /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, - /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, @@ -116,8 +100,8 @@ unsigned i; for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { - RCBA32(4 * i + 0x3400) = rcba_dump3[i]; - (void)RCBA32(4 * i + 0x3400); + RCBA32(4 * i + 0x3500) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3500); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69fc8a5e16f7cf0e1068d0d2ed678a6c2f6e70a9 Gerrit-Change-Number: 35440 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 21

Change in coreboot[master]: sb/intel/ibexpeak: Fix enabling HPTC
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35757 ) Change subject: sb/intel/ibexpeak: Fix enabling HPTC ...................................................................... sb/intel/ibexpeak: Fix enabling HPTC RCBA_HPTC needs to be read back to properly work. This fixes SeaBIOS endlessly waiting for input instead of booting the default entry. Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/ibexpeak/lpc.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35757/1 diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 4a25181..8088827 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -393,6 +393,7 @@ reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; + RCBA32(HPTC); /* Read back for it to work */ write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58 Gerrit-Change-Number: 35757 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: nb/intel/nehalem: Remove bogus GT PM init
by Arthur Heymans (Code Review) 06 Oct '19

06 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35746 ) Change subject: nb/intel/nehalem: Remove bogus GT PM init ...................................................................... nb/intel/nehalem: Remove bogus GT PM init This was simply copied from sandybridge/gma.c. All these registers read back 0xffffffff or 0 or don't respond to reads. Change-Id: I094e7caa889a3175477aa78b91545ca804d423c8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/gma.c 1 file changed, 3 insertions(+), 430 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35746/1 diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 087d37e..4333307 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -36,225 +36,6 @@ #include "chip.h" #include "nehalem.h" -struct gt_powermeter { - u16 reg; - u32 value; -}; - -static const struct gt_powermeter snb_pm_gt1[] = { - {0xa200, 0xcc000000}, - {0xa204, 0x07000040}, - {0xa208, 0x0000fe00}, - {0xa20c, 0x00000000}, - {0xa210, 0x17000000}, - {0xa214, 0x00000021}, - {0xa218, 0x0817fe19}, - {0xa21c, 0x00000000}, - {0xa220, 0x00000000}, - {0xa224, 0xcc000000}, - {0xa228, 0x07000040}, - {0xa22c, 0x0000fe00}, - {0xa230, 0x00000000}, - {0xa234, 0x17000000}, - {0xa238, 0x00000021}, - {0xa23c, 0x0817fe19}, - {0xa240, 0x00000000}, - {0xa244, 0x00000000}, - {0xa248, 0x8000421e}, - {0} -}; - -static const struct gt_powermeter snb_pm_gt2[] = { - {0xa200, 0x330000a6}, - {0xa204, 0x402d0031}, - {0xa208, 0x00165f83}, - {0xa20c, 0xf1000000}, - {0xa210, 0x00000000}, - {0xa214, 0x00160016}, - {0xa218, 0x002a002b}, - {0xa21c, 0x00000000}, - {0xa220, 0x00000000}, - {0xa224, 0x330000a6}, - {0xa228, 0x402d0031}, - {0xa22c, 0x00165f83}, - {0xa230, 0xf1000000}, - {0xa234, 0x00000000}, - {0xa238, 0x00160016}, - {0xa23c, 0x002a002b}, - {0xa240, 0x00000000}, - {0xa244, 0x00000000}, - {0xa248, 0x8000421e}, - {0} -}; - -static const struct gt_powermeter ivb_pm_gt1[] = { - {0xa800, 0x00000000}, - {0xa804, 0x00021c00}, - {0xa808, 0x00000403}, - {0xa80c, 0x02001700}, - {0xa810, 0x05000200}, - {0xa814, 0x00000000}, - {0xa818, 0x00690500}, - {0xa81c, 0x0000007f}, - {0xa820, 0x01002501}, - {0xa824, 0x00000300}, - {0xa828, 0x01000331}, - {0xa82c, 0x0000000c}, - {0xa830, 0x00010016}, - {0xa834, 0x01100101}, - {0xa838, 0x00010103}, - {0xa83c, 0x00041300}, - {0xa840, 0x00000b30}, - {0xa844, 0x00000000}, - {0xa848, 0x7f000000}, - {0xa84c, 0x05000008}, - {0xa850, 0x00000001}, - {0xa854, 0x00000004}, - {0xa858, 0x00000007}, - {0xa85c, 0x00000000}, - {0xa860, 0x00010000}, - {0xa248, 0x0000221e}, - {0xa900, 0x00000000}, - {0xa904, 0x00001c00}, - {0xa908, 0x00000000}, - {0xa90c, 0x06000000}, - {0xa910, 0x09000200}, - {0xa914, 0x00000000}, - {0xa918, 0x00590000}, - {0xa91c, 0x00000000}, - {0xa920, 0x04002501}, - {0xa924, 0x00000100}, - {0xa928, 0x03000410}, - {0xa92c, 0x00000000}, - {0xa930, 0x00020000}, - {0xa934, 0x02070106}, - {0xa938, 0x00010100}, - {0xa93c, 0x00401c00}, - {0xa940, 0x00000000}, - {0xa944, 0x00000000}, - {0xa948, 0x10000e00}, - {0xa94c, 0x02000004}, - {0xa950, 0x00000001}, - {0xa954, 0x00000004}, - {0xa960, 0x00060000}, - {0xaa3c, 0x00001c00}, - {0xaa54, 0x00000004}, - {0xaa60, 0x00060000}, - {0} -}; - -static const struct gt_powermeter ivb_pm_gt2_17w[] = { - {0xa800, 0x20000000}, - {0xa804, 0x000e3800}, - {0xa808, 0x00000806}, - {0xa80c, 0x0c002f00}, - {0xa810, 0x0c000800}, - {0xa814, 0x00000000}, - {0xa818, 0x00d20d00}, - {0xa81c, 0x000000ff}, - {0xa820, 0x03004b02}, - {0xa824, 0x00000600}, - {0xa828, 0x07000773}, - {0xa82c, 0x00000000}, - {0xa830, 0x00020032}, - {0xa834, 0x1520040d}, - {0xa838, 0x00020105}, - {0xa83c, 0x00083700}, - {0xa840, 0x000016ff}, - {0xa844, 0x00000000}, - {0xa848, 0xff000000}, - {0xa84c, 0x0a000010}, - {0xa850, 0x00000002}, - {0xa854, 0x00000008}, - {0xa858, 0x0000000f}, - {0xa85c, 0x00000000}, - {0xa860, 0x00020000}, - {0xa248, 0x0000221e}, - {0xa900, 0x00000000}, - {0xa904, 0x00003800}, - {0xa908, 0x00000000}, - {0xa90c, 0x0c000000}, - {0xa910, 0x12000800}, - {0xa914, 0x00000000}, - {0xa918, 0x00b20000}, - {0xa91c, 0x00000000}, - {0xa920, 0x08004b02}, - {0xa924, 0x00000300}, - {0xa928, 0x01000820}, - {0xa92c, 0x00000000}, - {0xa930, 0x00030000}, - {0xa934, 0x15150406}, - {0xa938, 0x00020300}, - {0xa93c, 0x00903900}, - {0xa940, 0x00000000}, - {0xa944, 0x00000000}, - {0xa948, 0x20001b00}, - {0xa94c, 0x0a000010}, - {0xa950, 0x00000000}, - {0xa954, 0x00000008}, - {0xa960, 0x00110000}, - {0xaa3c, 0x00003900}, - {0xaa54, 0x00000008}, - {0xaa60, 0x00110000}, - {0} -}; - -static const struct gt_powermeter ivb_pm_gt2_35w[] = { - {0xa800, 0x00000000}, - {0xa804, 0x00030400}, - {0xa808, 0x00000806}, - {0xa80c, 0x0c002f00}, - {0xa810, 0x0c000300}, - {0xa814, 0x00000000}, - {0xa818, 0x00d20d00}, - {0xa81c, 0x000000ff}, - {0xa820, 0x03004b02}, - {0xa824, 0x00000600}, - {0xa828, 0x07000773}, - {0xa82c, 0x00000000}, - {0xa830, 0x00020032}, - {0xa834, 0x1520040d}, - {0xa838, 0x00020105}, - {0xa83c, 0x00083700}, - {0xa840, 0x000016ff}, - {0xa844, 0x00000000}, - {0xa848, 0xff000000}, - {0xa84c, 0x0a000010}, - {0xa850, 0x00000001}, - {0xa854, 0x00000008}, - {0xa858, 0x00000008}, - {0xa85c, 0x00000000}, - {0xa860, 0x00020000}, - {0xa248, 0x0000221e}, - {0xa900, 0x00000000}, - {0xa904, 0x00003800}, - {0xa908, 0x00000000}, - {0xa90c, 0x0c000000}, - {0xa910, 0x12000800}, - {0xa914, 0x00000000}, - {0xa918, 0x00b20000}, - {0xa91c, 0x00000000}, - {0xa920, 0x08004b02}, - {0xa924, 0x00000300}, - {0xa928, 0x01000820}, - {0xa92c, 0x00000000}, - {0xa930, 0x00030000}, - {0xa934, 0x15150406}, - {0xa938, 0x00020300}, - {0xa93c, 0x00903900}, - {0xa940, 0x00000000}, - {0xa944, 0x00000000}, - {0xa948, 0x20001b00}, - {0xa94c, 0x0a000010}, - {0xa950, 0x00000000}, - {0xa954, 0x00000008}, - {0xa960, 0x00110000}, - {0xaa3c, 0x00003900}, - {0xaa54, 0x00000008}, - {0xaa60, 0x00110000}, - {0} -}; - /* some vga option roms are used for several chipsets but they only have one * PCI ID in their header. If we encounter such an option rom, we need to do * the mapping ourselves @@ -281,12 +62,6 @@ write32(res2mmio(gtt_res, reg, 0), data); } -static inline void gtt_write_powermeter(const struct gt_powermeter *pm) -{ - for (; pm && pm->reg; pm++) - gtt_write(pm->reg, pm->value); -} - #define GTT_RETRY 1000 int gtt_poll(u32 reg, u32 mask, u32 value) { @@ -317,196 +92,6 @@ gnvs_ptr->aslb = aslb; } -static void gma_pm_init_pre_vbios(struct device *dev) -{ - u32 reg32; - - printk(BIOS_DEBUG, "GT Power Management Init\n"); - - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!gtt_res || !gtt_res->base) - return; - - if (bridge_silicon_revision() < IVB_STEP_C0) { - /* 1: Enable force wake */ - gtt_write(0xa18c, 0x00000001); - gtt_poll(0x130090, (1 << 0), (1 << 0)); - } else { - gtt_write(0xa180, 1 << 5); - gtt_write(0xa188, 0xffff0001); - gtt_poll(0x130040, (1 << 0), (1 << 0)); - } - - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ - reg32 = gtt_read(0x42004); - reg32 |= (1 << 14) | (1 << 15); - gtt_write(0x42004, reg32); - } - - if (bridge_silicon_revision() >= IVB_STEP_A0) { - /* Display Reset Acknowledge Settings */ - reg32 = gtt_read(0x45010); - reg32 |= (1 << 1) | (1 << 0); - gtt_write(0x45010, reg32); - } - - /* 2: Get GT SKU from GTT+0x911c[13] */ - reg32 = gtt_read(0x911c); - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - if (reg32 & (1 << 13)) { - printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); - gtt_write_powermeter(snb_pm_gt1); - } else { - printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); - gtt_write_powermeter(snb_pm_gt2); - } - } else { - u32 unit = MCHBAR32(0x5938) & 0xf; - - if (reg32 & (1 << 13)) { - /* GT1 SKU */ - printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); - gtt_write_powermeter(ivb_pm_gt1); - } else { - /* GT2 SKU */ - u32 tdp = MCHBAR32(0x5930) & 0x7fff; - tdp /= (1 << unit); - - if (tdp <= 17) { - /* <=17W ULV */ - printk(BIOS_DEBUG, "IVB GT2 17W " - "Power Meter Weights\n"); - gtt_write_powermeter(ivb_pm_gt2_17w); - } else if ((tdp >= 25) && (tdp <= 35)) { - /* 25W-35W */ - printk(BIOS_DEBUG, "IVB GT2 25W-35W " - "Power Meter Weights\n"); - gtt_write_powermeter(ivb_pm_gt2_35w); - } else { - /* All others */ - printk(BIOS_DEBUG, "IVB GT2 35W " - "Power Meter Weights\n"); - gtt_write_powermeter(ivb_pm_gt2_35w); - } - } - } - - /* 3: Gear ratio map */ - gtt_write(0xa004, 0x00000010); - - /* 4: GFXPAUSE */ - gtt_write(0xa000, 0x00070020); - - /* 5: Dynamic EU trip control */ - gtt_write(0xa080, 0x00000004); - - /* 6: ECO bits */ - reg32 = gtt_read(0xa180); - reg32 |= (1 << 26) | (1 << 31); - /* (bit 20=1 for SNB step D1+ / IVB A0+) */ - if (bridge_silicon_revision() >= SNB_STEP_D1) - reg32 |= (1 << 20); - gtt_write(0xa180, reg32); - - /* 6a: for SnB step D2+ only */ - if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && - (bridge_silicon_revision() >= SNB_STEP_D2)) { - reg32 = gtt_read(0x9400); - reg32 |= (1 << 7); - gtt_write(0x9400, reg32); - - reg32 = gtt_read(0x941c); - reg32 &= 0xf; - reg32 |= (1 << 1); - gtt_write(0x941c, reg32); - gtt_poll(0x941c, (1 << 1), (0 << 1)); - } - - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - reg32 = gtt_read(0x907c); - reg32 |= (1 << 16); - gtt_write(0x907c, reg32); - - /* 6b: Clocking reset controls */ - gtt_write(0x9424, 0x00000001); - } else { - /* 6b: Clocking reset controls */ - gtt_write(0x9424, 0x00000000); - } - - /* 7 */ - if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { - gtt_write(0x138128, 0x00000029); /* Mailbox Data */ - gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ - if (gtt_poll(0x138124, (1 << 31), (0 << 31))) - gtt_write(0x138124, 0x8000000a); - gtt_poll(0x138124, (1 << 31), (0 << 31)); - } - - /* 8 */ - gtt_write(0xa090, 0x00000000); /* RC Control */ - gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ - gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ - gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ - gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ - gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ - - /* 9 */ - gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ - gtt_write(0x12054, 0x0000000a); /* Video Idle Max Count */ - gtt_write(0x22054, 0x0000000a); /* Blitter Idle Max Count */ - - /* 10 */ - gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ - gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ - gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ - gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ - gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ - - /* 11 */ - gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ - gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ - gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ - gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ - gtt_write(0xa068, 0x000186a0); /* RP Up EI */ - gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ - gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ - - /* 11a: Enable Render Standby (RC6) */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - /* - * IvyBridge should also support DeepRenderStandby. - * - * Unfortunately it does not work reliably on all SKUs so - * disable it here and it can be enabled by the kernel. - */ - gtt_write(0xa090, 0x88040000); /* HW RC Control */ - } else { - gtt_write(0xa090, 0x88040000); /* HW RC Control */ - } - - /* 12: Normal Frequency Request */ - /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ - /* only the lower 7 bits are used and shifted left by 25 */ - reg32 = MCHBAR32(0x5998); - reg32 >>= 16; - reg32 &= 0x7f; - reg32 <<= 25; - gtt_write(0xa008, reg32); - - /* 13: RP Control */ - gtt_write(0xa024, 0x00000592); - - /* 14: Enable PM Interrupts */ - gtt_write(0x4402c, 0x03000076); - - /* Clear 0x6c024 [8:6] */ - reg32 = gtt_read(0x6c024); - reg32 &= ~0x000001c0; - gtt_write(0x6c024, reg32); -} - static void gma_pm_init_post_vbios(struct device *dev) { struct northbridge_intel_nehalem_config *conf = dev->chip_info; @@ -514,19 +99,6 @@ printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); - /* 15: Deassert Force Wake */ - if (bridge_silicon_revision() < IVB_STEP_C0) { - gtt_write(0xa18c, gtt_read(0xa18c) & ~1); - gtt_poll(0x130090, (1 << 0), (0 << 0)); - } else { - gtt_write(0xa188, 0x1fffe); - if (gtt_poll(0x130040, (1 << 0), (0 << 0))) - gtt_write(0xa188, gtt_read(0xa188) | 1); - } - - /* 16: SW RC Control */ - gtt_write(0xa094, 0x00060000); - /* Setup Digital Port Hotplug */ reg32 = gtt_read(0xc4030); if (!reg32) { @@ -600,8 +172,9 @@ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Init graphics power management */ - gma_pm_init_pre_vbios(dev); + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!gtt_res || !gtt_res->base) + return; if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { struct northbridge_intel_nehalem_config *conf = dev->chip_info; -- To view, visit https://review.coreboot.org/c/coreboot/+/35746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I094e7caa889a3175477aa78b91545ca804d423c8 Gerrit-Change-Number: 35746 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019