coreboot-gerrit October 2019

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Change in coreboot[master]: intel/fsp_baytrail: Define PCH_DEV_SLOT_I2C1
by Kyösti Mälkki (Code Review) 05 Oct '19

05 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35733 ) Change subject: intel/fsp_baytrail: Define PCH_DEV_SLOT_I2C1 ...................................................................... intel/fsp_baytrail: Define PCH_DEV_SLOT_I2C1 Change-Id: I02c08b847fa1523e3296bdf9e3db5a7a322df72e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_baytrail/i2c.c M src/soc/intel/fsp_baytrail/include/soc/pci_devs.h 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35733/1 diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index 3ea91e3..5f6ca467 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -117,7 +117,7 @@ base_ptr = (char*)base_adr[bus]; /* Set the I2C-device the user wants to use */ - dev = pcidev_on_root(I2C1_DEV, bus + 1); + dev = pcidev_on_root(PCH_DEV_SLOT_I2C1, bus + 1); /* Ensure we have the right PCI device */ if ((pci_read_config16(dev, 0x0) != I2C_PCI_VENDOR_ID) || @@ -174,7 +174,7 @@ int stat; /* Get base address of desired I2C-controller */ - dev = pcidev_on_root(I2C1_DEV, bus + 1); + dev = pcidev_on_root(PCH_DEV_SLOT_I2C1, bus + 1); base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); if (base_ptr == NULL) { printk(BIOS_INFO, "I2C: Invalid Base address\n"); @@ -233,7 +233,7 @@ int stat; /* Get base address of desired I2C-controller */ - dev = pcidev_on_root(I2C1_DEV, bus + 1); + dev = pcidev_on_root(PCH_DEV_SLOT_I2C1, bus + 1); base_ptr = (char *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); if (base_ptr == NULL) { return I2C_ERR_INVALID_ADR; diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index 5f2b1b6..e0c2ff0 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -139,6 +139,8 @@ # define XXX_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) # define XXX_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) +#define PCH_DEV_SLOT_I2C1 I2C1_DEV + /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02c08b847fa1523e3296bdf9e3db5a7a322df72e Gerrit-Change-Number: 35733 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/fsp_baytrail: Rename from xx_DEV_FUNC
by Kyösti Mälkki (Code Review) 05 Oct '19

05 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35732 ) Change subject: intel/fsp_baytrail: Rename from xx_DEV_FUNC ...................................................................... intel/fsp_baytrail: Rename from xx_DEV_FUNC Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/include/soc/lpc.h M src/soc/intel/fsp_baytrail/include/soc/pci_devs.h 4 files changed, 62 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35732/1 diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb941ab..59dc6be 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -175,7 +175,7 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN); + struct device *lpcdev = pcidev_path_on_root(PCH_DEVFN_LPC); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = config_of(lpcdev); diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c0b0998..0df07ee 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -79,7 +79,7 @@ DEVTREE_CONST config_t *config; printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); - dev = pcidev_path_on_root(SOC_DEV_FUNC); + dev = pcidev_path_on_root(XXX_DEVFN_SOC); config = config_of(dev); /* Set up default verb tables - Just HDMI audio */ @@ -142,26 +142,26 @@ continue; switch (dev->path.pci.devfn) { - UPD_DEVICE_CHECK(SDIO_DEV_FUNC, PcdEnableSdio, "Sdio:\t\t\t"); - UPD_DEVICE_CHECK(SD_DEV_FUNC, PcdEnableSdcard, "Sdcard:\t\t\t"); - UPD_DEVICE_CHECK(SIO_DMA1_DEV_FUNC, PcdEnableDma0, "SIO Dma 0:\t\t"); - UPD_DEVICE_CHECK(I2C1_DEV_FUNC, PcdEnableI2C0, "SIO I2C0:\t\t"); - UPD_DEVICE_CHECK(I2C2_DEV_FUNC, PcdEnableI2C1, "SIO I2C1:\t\t"); - UPD_DEVICE_CHECK(I2C3_DEV_FUNC, PcdEnableI2C2, "SIO I2C2:\t\t"); - UPD_DEVICE_CHECK(I2C4_DEV_FUNC, PcdEnableI2C3, "SIO I2C3:\t\t"); - UPD_DEVICE_CHECK(I2C5_DEV_FUNC, PcdEnableI2C4, "SIO I2C4:\t\t"); - UPD_DEVICE_CHECK(I2C6_DEV_FUNC, PcdEnableI2C5, "SIO I2C5:\t\t"); - UPD_DEVICE_CHECK(I2C7_DEV_FUNC, PcdEnableI2C6, "SIO I2C6:\t\t"); - UPD_DEVICE_CHECK(SIO_DMA2_DEV_FUNC, PcdEnableDma1, "SIO Dma1:\t\t"); - UPD_DEVICE_CHECK(PWM1_DEV_FUNC, PcdEnablePwm0, "Pwm0:\t\t\t"); - UPD_DEVICE_CHECK(PWM2_DEV_FUNC, PcdEnablePwm1, "Pwm1:\t\t\t"); - UPD_DEVICE_CHECK(HSUART1_DEV_FUNC, PcdEnableHsuart0, "Hsuart0:\t\t"); - UPD_DEVICE_CHECK(HSUART2_DEV_FUNC, PcdEnableHsuart1, "Hsuart1:\t\t"); - UPD_DEVICE_CHECK(SPI_DEV_FUNC, PcdEnableSpi, "Spi:\t\t\t"); - UPD_DEVICE_CHECK(SATA_DEV_FUNC, PcdEnableSata, "SATA:\t\t\t"); - UPD_DEVICE_CHECK(HDA_DEV_FUNC, PcdEnableAzalia, "Azalia:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SDIO, PcdEnableSdio, "Sdio:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SD, PcdEnableSdcard, "Sdcard:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SIO_DMA1, PcdEnableDma0, "SIO Dma 0:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C1, PcdEnableI2C0, "SIO I2C0:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C2, PcdEnableI2C1, "SIO I2C1:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C3, PcdEnableI2C2, "SIO I2C2:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C4, PcdEnableI2C3, "SIO I2C3:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C5, PcdEnableI2C4, "SIO I2C4:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C6, PcdEnableI2C5, "SIO I2C5:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_I2C7, PcdEnableI2C6, "SIO I2C6:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SIO_DMA2, PcdEnableDma1, "SIO Dma1:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_PWM1, PcdEnablePwm0, "Pwm0:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_PWM2, PcdEnablePwm1, "Pwm1:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_HSUART1, PcdEnableHsuart0, "Hsuart0:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_HSUART2, PcdEnableHsuart1, "Hsuart1:\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SPI, PcdEnableSpi, "Spi:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_SATA, PcdEnableSata, "SATA:\t\t\t"); + UPD_DEVICE_CHECK(XXX_DEVFN_HDA, PcdEnableAzalia, "Azalia:\t\t\t"); - case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ + case XXX_DEVFN_MIPI: /* Camera / Image Signal Processing */ if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { UpdData->ISPEnable = dev->enabled; } else { @@ -174,24 +174,24 @@ printk(FSP_INFO_LEVEL, "MIPI/ISP:\t\t%s\n", dev->enabled?"Enabled":"Disabled"); break; - case EMMC_DEV_FUNC: /* EMMC 4.1*/ + case XXX_DEVFN_EMMC: /* EMMC 4.1*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; break; - case MMC45_DEV_FUNC: /* MMC 4.5*/ + case XXX_DEVFN_MMC45: /* MMC 4.5*/ if ((dev->enabled) && (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; break; - case XHCI_DEV_FUNC: + case XXX_DEVFN_XHCI: UpdData->PcdEnableXhci = dev->enabled; break; - case EHCI_DEV_FUNC: + case XXX_DEVFN_EHCI: UpdData->PcdEnableXhci = !(dev->enabled); break; - case LPE_DEV_FUNC: + case XXX_DEVFN_LPE: if (dev->enabled) UpdData->PcdEnableLpe = config->LpeAcpiModeEnable; else diff --git a/src/soc/intel/fsp_baytrail/include/soc/lpc.h b/src/soc/intel/fsp_baytrail/include/soc/lpc.h index 5abe719..defd34a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/lpc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/lpc.h @@ -17,8 +17,6 @@ #ifndef _BAYTRAIL_LPC_H_ #define _BAYTRAIL_LPC_H_ -#define FADT_SOC_LPC_DEVFN PCI_DEVFN(0x1f, 0) - /* PCI config registers in LPC bridge. */ #define REVID 0x08 #define ABASE 0x40 /* IO BAR */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index 5d70879..5f2b1b6 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -27,39 +27,39 @@ #define SOC_DEV 0x0 #define SOC_FUNC 0 # define SOC_DEVID 0x0f00 -# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) +# define XXX_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 # define GFX_DEVID 0x0f31 -# define GFX_DEV_FUNC PCI_DEVFN(GFX_DEV,GFX_FUNC) +# define XXX_DEVFN_GFX PCI_DEVFN(GFX_DEV,GFX_FUNC) /* MIPI */ #define MIPI_DEV 0x3 #define MIPI_FUNC 0 # define MIPI_DEVID 0x0f38 -# define MIPI_DEV_FUNC PCI_DEVFN(MIPI_DEV,MIPI_FUNC) +# define XXX_DEVFN_MIPI PCI_DEVFN(MIPI_DEV,MIPI_FUNC) /* SDIO Port */ #define EMMC_DEV 0x10 #define EMMC_FUNC 0 # define EMMC_DEVID 0x0f14 -# define EMMC_DEV_FUNC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) +# define XXX_DEVFN_EMMC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 # define SDIO_DEVID 0x0f15 -# define SDIO_DEV_FUNC PCI_DEVFN(SDIO_DEV,SDIO_FUNC) +# define XXX_DEVFN_SDIO PCI_DEVFN(SDIO_DEV,SDIO_FUNC) /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 # define SD_DEVID 0x0f16 -# define SD_DEV_FUNC PCI_DEVFN(SD_DEV,SD_FUNC) +# define XXX_DEVFN_SD PCI_DEVFN(SD_DEV,SD_FUNC) /* SATA */ #define SATA_DEV 0x13 @@ -74,7 +74,7 @@ # define SATA_SP 0xD0 # define SATA_BIST1 0xE4 # define SATA_BIST2 0xE8 -# define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV,SATA_FUNC) +# define XXX_DEVFN_SATA PCI_DEVFN(SATA_DEV,SATA_FUNC) /* xHCI */ @@ -84,25 +84,25 @@ # define XHCI_FUS_REG 0xE0 # define XHCI_FUNC_DISABLE (1 << 0) # define XHCI_USB2PR_REG 0xD0 -# define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +# define XXX_DEVFN_XHCI PCI_DEVFN(XHCI_DEV,XHCI_FUNC) /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 # define LPE_DEVID 0x0f28 -# define LPE_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define XXX_DEVFN_LPE PCI_DEVFN(LPE_DEV,LPE_FUNC) /* OTG */ #define OTG_DEV 0x16 #define OTG_FUNC 0 # define OTG_DEVID 0x0f37 -# define OTG_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) +# define XXX_DEVFN_OTG PCI_DEVFN(LPE_DEV,LPE_FUNC) /* MMC Port */ #define MMC45_DEV 0x17 #define MMC45_FUNC 0 # define MMC45_DEVID 0x0f50 -# define MMC45_DEV_FUNC PCI_DEVFN(MMC45_DEV,MMC45_FUNC) +# define XXX_DEVFN_MMC45 PCI_DEVFN(MMC45_DEV,MMC45_FUNC) /* Serial IO 1 */ #define SIO1_DEV 0x18 @@ -130,26 +130,26 @@ # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 # define I2C7_DEVID 0x0f47 -# define SIO_DMA1_DEV_FUNC PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) -# define I2C1_DEV_FUNC PCI_DEVFN(I2C1_DEV,I2C1_FUNC) -# define I2C2_DEV_FUNC PCI_DEVFN(I2C2_DEV,I2C2_FUNC) -# define I2C3_DEV_FUNC PCI_DEVFN(I2C3_DEV,I2C3_FUNC) -# define I2C4_DEV_FUNC PCI_DEVFN(I2C4_DEV,I2C4_FUNC) -# define I2C5_DEV_FUNC PCI_DEVFN(I2C5_DEV,I2C5_FUNC) -# define I2C6_DEV_FUNC PCI_DEVFN(I2C6_DEV,I2C6_FUNC) -# define I2C7_DEV_FUNC PCI_DEVFN(I2C7_DEV,I2C7_FUNC) +# define XXX_DEVFN_SIO_DMA1 PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) +# define XXX_DEVFN_I2C1 PCI_DEVFN(I2C1_DEV,I2C1_FUNC) +# define XXX_DEVFN_I2C2 PCI_DEVFN(I2C2_DEV,I2C2_FUNC) +# define XXX_DEVFN_I2C3 PCI_DEVFN(I2C3_DEV,I2C3_FUNC) +# define XXX_DEVFN_I2C4 PCI_DEVFN(I2C4_DEV,I2C4_FUNC) +# define XXX_DEVFN_I2C5 PCI_DEVFN(I2C5_DEV,I2C5_FUNC) +# define XXX_DEVFN_I2C6 PCI_DEVFN(I2C6_DEV,I2C6_FUNC) +# define XXX_DEVFN_I2C7 PCI_DEVFN(I2C7_DEV,I2C7_FUNC) /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 # define TXE_DEVID 0x0f18 -# define TXE_DEV_FUNC PCI_DEVFN(TXE_DEV,TXE_FUNC) +# define XXX_DEVFN_TXE PCI_DEVFN(TXE_DEV,TXE_FUNC) /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 # define HDA_DEVID 0x0f04 -# define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC) +# define XXX_DEVFN_HDA PCI_DEVFN(HDA_DEV,HDA_FUNC) # define HDA_AZUBAR 0x14 # define HDA_MMLA 0x64 # define HDA_MMUA 0x68 @@ -168,16 +168,16 @@ # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 # define PCIE_PORT4_DEVID 0x0f4e -# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) -# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) -# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) -# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) +# define XXX_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) +# define XXX_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) +# define XXX_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) +# define XXX_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_DEV,PCIE_PORT4_FUNC) /* EHCI */ #define EHCI_DEV 0x1d #define EHCI_FUNC 0 # define EHCI_DEVID 0x0f34 -# define EHCI_DEV_FUNC PCI_DEVFN(EHCI_DEV,EHCI_FUNC) +# define XXX_DEVFN_EHCI PCI_DEVFN(EHCI_DEV,EHCI_FUNC) /* Serial IO 2 */ #define SIO2_DEV 0x1e @@ -199,12 +199,12 @@ # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 # define SPI_DEVID 0xf0e -# define SIO_DMA2_DEV_FUNC PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) -# define PWM1_DEV_FUNC PCI_DEVFN(PWM1_DEV,PWM1_FUNC) -# define PWM2_DEV_FUNC PCI_DEVFN(PWM2_DEV,PWM2_FUNC) -# define HSUART1_DEV_FUNC PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) -# define HSUART2_DEV_FUNC PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) -# define SPI_DEV_FUNC PCI_DEVFN(SPI_DEV,SPI_FUNC) +# define XXX_DEVFN_SIO_DMA2 PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) +# define XXX_DEVFN_PWM1 PCI_DEVFN(PWM1_DEV,PWM1_FUNC) +# define XXX_DEVFN_PWM2 PCI_DEVFN(PWM2_DEV,PWM2_FUNC) +# define XXX_DEVFN_HSUART1 PCI_DEVFN(HSUART1_DEV,HSUART1_FUNC) +# define XXX_DEVFN_HSUART2 PCI_DEVFN(HSUART2_DEV,HSUART2_FUNC) +# define XXX_DEVFN_SPI PCI_DEVFN(SPI_DEV,SPI_FUNC) /* Platform Controller Unit */ @@ -212,11 +212,12 @@ # define LPC_DEV PCU_DEV # define LPC_FUNC 0 # define LPC_DEVID 0x0f1c +# define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) +# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) + # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 # define SMBUS_DEVID 0x0f12 -# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) -# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) -# define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +# define XXX_DEVFN_SMBUS PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) #endif /* _BAYTRAIL_PCI_DEVS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f Gerrit-Change-Number: 35732 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNC
by Kyösti Mälkki (Code Review) 05 Oct '19

05 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35730 ) Change subject: sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNC ...................................................................... sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNC Change-Id: I6ead2bc5e41a86c9aeef730f5664a30406414c8c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c M src/southbridge/intel/fsp_rangeley/pci_devs.h 2 files changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/35730/1 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 43e71f4..a9d2ba7 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -52,7 +52,7 @@ DEVTREE_CONST config_t *config; printk(BIOS_DEBUG, "Configure Default UPD Data\n"); - dev = pcidev_path_on_root(SOC_DEV_FUNC); + dev = pcidev_path_on_root(XXX_DEVFN_SOC); config = dev->chip_info; /* Set SPD addresses */ @@ -103,30 +103,30 @@ continue; switch (dev->path.pci.devfn) { - case GBE1_DEV_FUNC: - case GBE2_DEV_FUNC: - case GBE3_DEV_FUNC: - case GBE4_DEV_FUNC: + case XXX_DEVFN_GBE1: + case XXX_DEVFN_GBE2: + case XXX_DEVFN_GBE3: + case XXX_DEVFN_GBE4: UpdData->PcdEnableLan |= dev->enabled; printk(BIOS_DEBUG, "PcdEnableLan %d\n", UpdData->PcdEnableLan); break; - case SATA2_DEV_FUNC: + case XXX_DEVFN_SATA2: UpdData->PcdEnableSata2 = dev->enabled; printk(BIOS_DEBUG, "PcdEnableSata2 %d\n", UpdData->PcdEnableSata2); break; - case SATA3_DEV_FUNC: + case XXX_DEVFN_SATA3: UpdData->PcdEnableSata3 = dev->enabled; printk(BIOS_DEBUG, "PcdEnableSata3 %d\n", UpdData->PcdEnableSata3); break; - case IQAT_DEV_FUNC: + case XXX_DEVFN_IQAT: UpdData->PcdEnableIQAT |= dev->enabled; printk(BIOS_DEBUG, "PcdEnableIQAT %d\n", UpdData->PcdEnableIQAT); break; - case USB2_DEV_FUNC: + case XXX_DEVFN_USB2: UpdData->PcdEnableUsb20 = dev->enabled; printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n", UpdData->PcdEnableUsb20); diff --git a/src/southbridge/intel/fsp_rangeley/pci_devs.h b/src/southbridge/intel/fsp_rangeley/pci_devs.h index 89f3c5c..69edae6 100644 --- a/src/southbridge/intel/fsp_rangeley/pci_devs.h +++ b/src/southbridge/intel/fsp_rangeley/pci_devs.h @@ -26,72 +26,72 @@ /* Host Bridge */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) +# define XXX_DEVFN_SOC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* PCIE Port 1 */ #define PCIE_PORT1_DEV 0x1 #define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) +# define XXX_DEVFN_PCIE_PORT1 PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) /* PCIE Port 2 */ #define PCIE_PORT2_DEV 0x2 #define PCIE_PORT2_FUNC 0 -# define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) +# define XXX_DEVFN_PCIE_PORT2 PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) /* PCIE Port 3 */ #define PCIE_PORT3_DEV 0x3 #define PCIE_PORT3_FUNC 0 -# define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) +# define XXX_DEVFN_PCIE_PORT3 PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) /* PCIE Port 4 */ #define PCIE_PORT4_DEV 0x4 #define PCIE_PORT4_FUNC 0 -# define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) +# define XXX_DEVFN_PCIE_PORT4 PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) /* Host Bridge, Fabric, and RAS Registers */ #define HOST_BRIDGE_DEV 0xe #define HOST_BRIDGE_FUNC 0 -# define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) +# define XXX_DEVFN_HOST_BRIDGE PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) /* Root Complex Event Collector (RCEC) */ #define RCEC_DEV 0xf #define RCEC_FUNC 0 -# define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) +# define XXX_DEVFN_RCEC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) /* SMBus 2.0 1 */ #define SMBUS1_DEV 0x13 #define SMBUS1_FUNC 0 -# define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) +# define XXX_DEVFN_SMBUS1 PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) /* Gigabit Ethernet (GbE) */ #define GBE_DEV 0x14 #define GBE1_DEV GBE_DEV #define GBE1_FUNC 0 -# define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC) +# define XXX_DEVFN_GBE1 PCI_DEVFN(GBE1_DEV,GBE1_FUNC) #define GBE2_DEV GBE_DEV #define GBE2_FUNC 1 -# define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC) +# define XXX_DEVFN_GBE2 PCI_DEVFN(GBE2_DEV,GBE2_FUNC) #define GBE3_DEV GBE_DEV #define GBE3_FUNC 2 -# define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC) +# define XXX_DEVFN_GBE3 PCI_DEVFN(GBE3_DEV,GBE3_FUNC) #define GBE4_DEV GBE_DEV #define GBE4_FUNC 3 -# define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC) +# define XXX_DEVFN_GBE4 PCI_DEVFN(GBE4_DEV,GBE4_FUNC) /* USB 2.0 */ #define USB2_DEV 0x16 #define USB2_FUNC 0 -# define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC) +# define XXX_DEVFN_USB2 PCI_DEVFN(USB2_DEV,USB2_FUNC) /* SATA Gen 2 */ #define SATA2_DEV 0x17 #define SATA2_FUNC 0 -# define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC) +# define XXX_DEVFN_SATA2 PCI_DEVFN(SATA2_DEV,SATA2_FUNC) /* SATA Gen 3 */ #define SATA3_DEV 0x18 #define SATA3_FUNC 0 -# define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC) +# define XXX_DEVFN_SATA3 PCI_DEVFN(SATA3_DEV,SATA3_FUNC) /* Platform Control Unit (PCU) */ #define PCU_DEV 0x1f @@ -99,18 +99,18 @@ /* Low Pin Count (LPC/ISA) */ #define LPC_DEV PCU_DEV #define LPC_FUNC 0 -# define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) +# define XXX_DEVFN_LPC PCI_DEVFN(LPC_DEV,LPC_FUNC) # define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC) /* SMBus 2.0 0 */ #define SMBUS0_DEV PCU_DEV #define SMBUS0_FUNC 3 -# define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) +# define XXX_DEVFN_SMBUS0 PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) /* Intel QuickAssist Integrated Accelerator (IQIA) */ #define IQAT_DEV 0xb #define IQAT_FUNC 0 -# define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC) +# define XXX_DEVFN_IQAT PCI_DEVFN(IQAT_DEV,IQAT_FUNC) #define SOC_DEVID 0x1f08 #define PCIE_PORT1_DEVID 0x1f10 -- To view, visit https://review.coreboot.org/c/coreboot/+/35730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ead2bc5e41a86c9aeef730f5664a30406414c8c Gerrit-Change-Number: 35730 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: util/sconfig: Issue header for exposed PCI and PNP names
by Nico Huber (Code Review) 05 Oct '19

05 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35488 ) Change subject: util/sconfig: Issue header for exposed PCI and PNP names ...................................................................... util/sconfig: Issue header for exposed PCI and PNP names Let `sconfig` output a C header file with the symbol names that we generate since 5e2a2cd5e7 (util/sconfig: Expose usable PCI and PNP device names). We add another command line argument for the path to the header file. As the file is similar in nature to our `config.h` we simply put it in $(obj)/ too. Change-Id: I8f87288c82f2844b61eba6534797a42b978b47bb Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M Makefile.inc M util/sconfig/main.c 2 files changed, 38 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35488/1 diff --git a/Makefile.inc b/Makefile.inc index 3c3088d..aca787f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -591,11 +591,12 @@ endif DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c +DEVICETREE_STATIC_H := $(obj)/static.h $(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(dir $(DEVICETREE_STATIC_C)) - $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(OVERRIDE_DEVICETREE_FILE) + $(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(DEVICETREE_STATIC_H) $(OVERRIDE_DEVICETREE_FILE) ramstage-y+=$(DEVICETREE_STATIC_C) romstage-y+=$(DEVICETREE_STATIC_C) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 6b421ec..5c23333 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -696,7 +696,7 @@ return 0; } -static void pass0(FILE *fil, struct device *ptr, struct device *next) +static void pass0(FILE *fil, FILE *head, struct device *ptr, struct device *next) { if (ptr == &base_root_dev) { fprintf(fil, "STORAGE struct bus %s_links[];\n", @@ -781,7 +781,7 @@ fprintf(fil, "\t};\n"); } -static void pass1(FILE *fil, struct device *ptr, struct device *next) +static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next) { int pin; struct chip_instance *chip_ins = ptr->chip_instance; @@ -883,16 +883,22 @@ emit_dev_links(fil, ptr); } -static void expose_device_names(FILE *fil, struct device *ptr, struct device *next) +static void expose_device_names(FILE *fil, FILE *head, struct device *ptr, struct device *next) { /* Only devices on root bus here. */ - if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) + if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) { + fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d;\n", + ptr->path_a, ptr->path_b); fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pci_0_%02x_%d = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); + } - if (ptr->bustype == PNP) + if (ptr->bustype == PNP) { + fprintf(head, "extern DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x;\n", + ptr->path_a, ptr->path_b); fprintf(fil, "DEVTREE_CONST struct device *DEVTREE_CONST __pnp_%04x_%02x = &%s;\n", ptr->path_a, ptr->path_b, ptr->name); + } } static void add_siblings_to_queue(struct queue_entry **bfs_q_head, @@ -916,8 +922,8 @@ } } -static void walk_device_tree(FILE *fil, struct device *ptr, - void (*func)(FILE *, struct device *, +static void walk_device_tree(FILE *fil, FILE *head, struct device *ptr, + void (*func)(FILE *, FILE *, struct device *, struct device *)) { struct queue_entry *bfs_q_head = NULL; @@ -926,7 +932,7 @@ while ((ptr = dequeue_head(&bfs_q_head))) { add_children_to_queue(&bfs_q_head, ptr); - func(fil, ptr, peek_queue_head(bfs_q_head)); + func(fil, head, ptr, peek_queue_head(bfs_q_head)); } } @@ -995,7 +1001,7 @@ } } -static void inherit_subsystem_ids(FILE *file, struct device *dev, +static void inherit_subsystem_ids(FILE *file, FILE *head, struct device *dev, struct device *next) { struct device *p; @@ -1020,17 +1026,18 @@ static void usage(void) { - printf("usage: sconfig devicetree_file output_file [override_devicetree_file]\n"); + printf("usage: sconfig devicetree_file output_file header_file [override_devicetree_file]\n"); exit(1); } enum { DEVICEFILE_ARG = 1, OUTPUTFILE_ARG, + HEADERFILE_ARG, OVERRIDE_DEVICEFILE_ARG, }; -#define MANDATORY_ARG_COUNT 3 +#define MANDATORY_ARG_COUNT 4 #define OPTIONAL_ARG_COUNT 1 #define TOTAL_ARG_COUNT (MANDATORY_ARG_COUNT + OPTIONAL_ARG_COUNT) @@ -1365,6 +1372,7 @@ const char *base_devtree = argv[DEVICEFILE_ARG]; const char *outputc = argv[OUTPUTFILE_ARG]; + const char *outputh = argv[HEADERFILE_ARG]; const char *override_devtree; parse_devicetree(base_devtree, &base_root_bus); @@ -1389,18 +1397,31 @@ exit(1); } + FILE *autohead = fopen(outputh, "w"); + if (!autohead) { + fprintf(stderr, "Could not open file '%s' for writing: ", outputh); + perror(NULL); + fclose(autogen); + exit(1); + } + fprintf(autohead, "#ifndef __STATIC_DEVICE_TREE_H\n"); + fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n"); + fprintf(autohead, "#include <device/device.h>\n\n"); + emit_chips(autogen); - walk_device_tree(autogen, &base_root_dev, inherit_subsystem_ids); + walk_device_tree(autogen, autohead, &base_root_dev, inherit_subsystem_ids); fprintf(autogen, "\n/* pass 0 */\n"); - walk_device_tree(autogen, &base_root_dev, pass0); + walk_device_tree(autogen, autohead, &base_root_dev, pass0); fprintf(autogen, "\n/* pass 1 */\n"); - walk_device_tree(autogen, &base_root_dev, pass1); + walk_device_tree(autogen, autohead, &base_root_dev, pass1); /* Expose static devicenames to global namespace. */ fprintf(autogen, "\n/* expose_device_names */\n"); - walk_device_tree(autogen, &base_root_dev, expose_device_names); + walk_device_tree(autogen, autohead, &base_root_dev, expose_device_names); + fprintf(autohead, "\n#endif /* __STATIC_DEVICE_TREE_H */\n"); + fclose(autohead); fclose(autogen); return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/35488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f87288c82f2844b61eba6534797a42b978b47bb Gerrit-Change-Number: 35488 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Yu-Ping Wu (Code Review) 05 Oct '19

05 Oct '19

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35775 ) Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... Patch Set 6: (3 comments) https://review.coreboot.org/c/coreboot/+/35775/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35775/3//COMMIT_MSG@7 PS3, Line 7: mediatek/mt8183 > soc/mediatek/mt8183 Done https://review.coreboot.org/c/coreboot/+/35775/3//COMMIT_MSG@9 PS3, Line 9: is shared with repository mt8183-dramk-private. : It is added here to simplify the communication between coreboot and the : program dram.elf. > simplifies the communication between coreboot and MTK DRAM calibration blob, and is shared by both i […] Done https://review.coreboot.org/c/coreboot/+/35775/3//COMMIT_MSG@13 PS3, Line 13: 139099592 > b:139099592 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 6 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Oct 2019 02:33:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Yu-Ping Wu (Code Review) 05 Oct '19

05 Oct '19

Hello Julius Werner, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35775 to look at the new patch set (#6). Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... soc/mediatek/mt8183: Add the shared 'dramc_param' module The dramc_param module simplifies the communication between coreboot and MTK DRAM full calibration blob, and is shared by both implementations to ensure the same format of parameters. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_param.c A src/soc/mediatek/mt8183/include/soc/dramc_param.h 3 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35775/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 6 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in libgfxinit[master]: gma: Merge `Config_State` into `State`
by Nico Huber (Code Review) 05 Oct '19

05 Oct '19

Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/35713 ) Change subject: gma: Merge `Config_State` into `State` ...................................................................... gma: Merge `Config_State` into `State` Treating `Config_State` separately was merely cosmetic and caused lots of trouble. Its usage depends heavily on the selected plat- form. Hence, `Global` contracts were not stable across different configurations. Let's avoid the annotation mess that it brought us and merge it into `State`. Change-Id: Ie28ccfc7ffbe08e0b3fe343d9e6df2420611834e Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35713 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads 4 files changed, 19 insertions(+), 44 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 1f6fea6..d5bd2ba 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -71,7 +71,7 @@ Dyn_CPU => Gen_CPU_Type'First, Dyn_CPU_Var => Gen_CPU_Variant'First); - Variable : Variable_Config with Part_Of => GMA.Config_State; + Variable : Variable_Config with Part_Of => GMA.State; Valid_Port : Valid_Port_Array renames Variable.Valid_Port; Raw_Clock : Frequency_Type renames Variable.Raw_Clock; diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index e9c8ab4..81fb219 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -1763,7 +1763,7 @@ (GTT_State =>+ (Config.Variable, GTT_Page, Device_Address, Valid)), Annotate => (GNATprove, Intentional, - """GMA.Config_State"" of ""Write_GTT"" not read", + """GMA.State"" of ""Write_GTT"" not read", "Reading of Config_State depends on the platform configuration."); procedure Read_GTT @@ -1779,7 +1779,7 @@ (Config.Variable, GTT_State, GTT_Page)), Annotate => (GNATprove, Intentional, - """GMA.Config_State"" of ""Read_GTT"" not read", + """GMA.State"" of ""Read_GTT"" not read", "Reading of Config_State depends on the platform configuration."); pragma Warnings (GNATprove, On, "no check message justified by this"); diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 8352e1c..3221e3e 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -38,7 +38,8 @@ package body HW.GFX.GMA with Refined_State => (State => - (PCI_Usable, + (Config.Variable, + PCI_Usable, Dev.Address_State, Registers.Address_State, PCode.Mailbox_Ready, @@ -47,7 +48,6 @@ HPD_Delay, Wait_For_HPD, Linear_FB_Base), Init_State => Initialized, - Config_State => (Config.Variable), Device_State => (Dev.PCI_State, Registers.Register_State, Registers.GTT_State)) is diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 3a4580e..bdc4704 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -24,7 +24,6 @@ Abstract_State => (State, Init_State, - Config_State, (Device_State with External)), Initializes => Init_State is @@ -105,7 +104,7 @@ with Global => (In_Out => (Device_State, Port_IO.State), - Output => (State, Init_State, Config_State), + Output => (State, Init_State), Input => (Time.State)), Post => Success = Is_Initialized; function Is_Initialized return Boolean @@ -116,7 +115,7 @@ procedure Power_Up_VGA with Global => - (Input => (State, Config_State, Time.State), + (Input => (State, Time.State), In_Out => (Device_State), Proof_In => (Init_State)), Pre => Is_Initialized; @@ -126,24 +125,17 @@ procedure Update_Outputs (Configs : Pipe_Configs) with Global => - (Input => (Config_State, Time.State), + (Input => (Time.State), In_Out => (State, Device_State, Port_IO.State), Proof_In => (Init_State)), Pre => Is_Initialized; - pragma Warnings (GNATprove, Off, "no check message justified by this", - Reason => "see Annotate aspects."); procedure Update_Cursor (Pipe : Pipe_Index; Cursor : Cursor_Type) with Global => - (Input => (Config_State), - In_Out => (State, Device_State), + (In_Out => (State, Device_State), Proof_In => (Init_State)), - Pre => Is_Initialized, - Annotate => - (GNATprove, Intentional, - "global input ""GMA.Config_State"" of ""Update_Cursor"" not read", - "Reading of Config_State depends on the platform configuration."); + Pre => Is_Initialized; procedure Place_Cursor (Pipe : Pipe_Index; @@ -151,14 +143,9 @@ Y : Cursor_Pos) with Global => - (Input => (Config_State), - In_Out => (State, Device_State), + (In_Out => (State, Device_State), Proof_In => (Init_State)), - Pre => Is_Initialized, - Annotate => - (GNATprove, Intentional, - "global input ""GMA.Config_State"" of ""Place_Cursor"" not read", - "Reading of Config_State depends on the platform configuration."); + Pre => Is_Initialized; procedure Move_Cursor (Pipe : Pipe_Index; @@ -166,14 +153,9 @@ Y : Cursor_Pos) with Global => - (Input => (Config_State), - In_Out => (State, Device_State), + (In_Out => (State, Device_State), Proof_In => (Init_State)), - Pre => Is_Initialized, - Annotate => - (GNATprove, Intentional, - "global input ""GMA.Config_State"" of ""Move_Cursor"" not read", - "Reading of Config_State depends on the platform configuration."); + Pre => Is_Initialized; ---------------------------------------------------------------------------- @@ -183,7 +165,7 @@ Valid : Boolean) with Global => - (Input => Config_State, + (Input => State, In_Out => Device_State, Proof_In => Init_State), Pre => Is_Initialized; @@ -193,7 +175,7 @@ GTT_Page : in GTT_Range) with Global => - (Input => Config_State, + (Input => State, In_Out => Device_State, Proof_In => Init_State), Pre => Is_Initialized; @@ -203,8 +185,7 @@ Success : out Boolean) with Global => - (Input => Config_State, - In_Out => + (In_Out => (State, Device_State, Framebuffer_Filler.State, Framebuffer_Filler.Base_Address), Proof_In => (Init_State)), @@ -213,15 +194,9 @@ procedure Map_Linear_FB (Linear_FB : out Word64; FB : in Framebuffer_Type) with Global => - (Input => Config_State, - In_Out => (State, Device_State), + (In_Out => (State, Device_State), Proof_In => (Init_State)), - Pre => Is_Initialized and HW.Config.Dynamic_MMIO, - Annotate => - (GNATprove, Intentional, - "global input ""GMA.Config_State"" of ""Map_Linear_FB"" not read", - "Reading of Config_State depends on the platform configuration."); - pragma Warnings (GNATprove, On, "no check message justified by this"); + Pre => Is_Initialized and HW.Config.Dynamic_MMIO; ---------------------------------------------------------------------------- -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ie28ccfc7ffbe08e0b3fe343d9e6df2420611834e Gerrit-Change-Number: 35713 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in libgfxinit[master]: gma: Merge `Config_State` into `State`
by Nico Huber (Code Review) 05 Oct '19

05 Oct '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35713 ) Change subject: gma: Merge `Config_State` into `State` ...................................................................... Patch Set 4: Verified+1 (1 comment) https://review.coreboot.org/c/libgfxinit/+/35713/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/libgfxinit/+/35713/3//COMMIT_MSG@10 PS3, Line 10: It's > Its Done -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ie28ccfc7ffbe08e0b3fe343d9e6df2420611834e Gerrit-Change-Number: 35713 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 04 Oct 2019 22:17:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in libgfxinit[master]: gma: Merge `Config_State` into `State`
by Nico Huber (Code Review) 05 Oct '19

05 Oct '19

Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/libgfxinit/+/35713 to look at the new patch set (#4). Change subject: gma: Merge `Config_State` into `State` ...................................................................... gma: Merge `Config_State` into `State` Treating `Config_State` separately was merely cosmetic and caused lots of trouble. Its usage depends heavily on the selected plat- form. Hence, `Global` contracts were not stable across different configurations. Let's avoid the annotation mess that it brought us and merge it into `State`. Change-Id: Ie28ccfc7ffbe08e0b3fe343d9e6df2420611834e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads 4 files changed, 19 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/13/35713/4 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ie28ccfc7ffbe08e0b3fe343d9e6df2420611834e Gerrit-Change-Number: 35713 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in libgfxinit[master]: gma: Allow private sub-packages to access PCI config
by Nico Huber (Code Review) 05 Oct '19

05 Oct '19

Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/35712 ) Change subject: gma: Allow private sub-packages to access PCI config ...................................................................... gma: Allow private sub-packages to access PCI config Only export Read16() for now, which we need in a follow-up. Change-Id: I2ca17cab0566d50000369263ab56e122ac6cbb8b Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35712 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads 2 files changed, 22 insertions(+), 2 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 269feec..8352e1c 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -38,7 +38,8 @@ package body HW.GFX.GMA with Refined_State => (State => - (Dev.Address_State, + (PCI_Usable, + Dev.Address_State, Registers.Address_State, PCode.Mailbox_Ready, PLLs.State, Panel.Panel_State, @@ -384,7 +385,8 @@ (Input => (Time.State), In_Out => (Dev.PCI_State, Registers.Register_State, Port_IO.State), Output => - (Config.Variable, + (PCI_Usable, + Config.Variable, Dev.Address_State, Registers.Address_State, PCode.Mailbox_Ready, @@ -446,6 +448,7 @@ pragma Debug (Debug.Set_Register_Write_Delay (Write_Delay)); + PCI_Usable := False; Linear_FB_Base := 0; PCode.Mailbox_Ready := False; Wait_For_HPD := HPD_Type'(others => False); @@ -470,6 +473,7 @@ Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => MMIO_GTT_Offset); if PCI_MMIO_Base /= 0 and PCI_GTT_Base /= 0 then Registers.Set_Register_Base (PCI_MMIO_Base, PCI_GTT_Base); + PCI_Usable := True; else pragma Debug (Debug.Put_Line ("ERROR: Couldn't map resoure0.")); @@ -934,4 +938,11 @@ end loop; end Dump_Configs; + ---------------------------------------------------------------------------- + + procedure PCI_Read16 (Value : out Word16; Offset : HW.PCI.Index) is + begin + Dev.Read16 (Value, Offset); + end PCI_Read16; + end HW.GFX.GMA; diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 353ec4b..3a4580e 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -15,6 +15,7 @@ with HW.Config; with HW.Time; +with HW.PCI; with HW.Port_IO; with HW.GFX.Framebuffer_Filler; @@ -230,6 +231,14 @@ private + PCI_Usable : Boolean with Part_Of => State; + use type HW.PCI.Index; + procedure PCI_Read16 (Value : out Word16; Offset : HW.PCI.Index) + with + Pre => PCI_Usable and Offset mod 2 = 0; + + ---------------------------------------------------------------------------- + -- For the default framebuffer setup (see below) with 90 degree rotations, -- we expect the offset which is used for the final scanout to be above -- `GTT_Rotation_Offset`. So we can use `Offset - GTT_Rotation_Offset` for -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I2ca17cab0566d50000369263ab56e122ac6cbb8b Gerrit-Change-Number: 35712 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit October 2019