coreboot-gerrit October 2019

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Change in coreboot[master]: acpi_table_header: Replace hard-code revision via macro
by Name of user not set (Code Review) 04 Oct '19

04 Oct '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35539 ) Change subject: acpi_table_header: Replace hard-code revision via macro ...................................................................... acpi_table_header: Replace hard-code revision via macro Minimize use of hard code value for acpi_table_header->revision to soft code. Replace with macro defined in arch/acpi.h Change-Id: I99e59afc1a87203499d2da6dedaedfa643ca7eac Signed-off-by: Sourabh Kashyap <Sourabhka(a)hcl.com> --- M src/mainboard/amd/torpedo/fadt.c M src/mainboard/intel/galileo/acpi_tables.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/portwell/m107/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/nvidia/mcp55/fadt.c 7 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35539/1 diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 9e33c07..25fb448 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -50,7 +50,7 @@ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = ACPI_FADT_REV_ACPI_1_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/intel/galileo/acpi_tables.c b/src/mainboard/intel/galileo/acpi_tables.c index 78b05ab..bba8ced 100644 --- a/src/mainboard/intel/galileo/acpi_tables.c +++ b/src/mainboard/intel/galileo/acpi_tables.c @@ -26,7 +26,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 5; + header->revision = ACPI_FADT_REV_ACPI_5_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index a7c6536..7d9096c 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -24,7 +24,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 5; + header->revision = ACPI_FADT_REV_ACPI_5_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/portwell/m107/fadt.c b/src/mainboard/portwell/m107/fadt.c index 7814106..82986f6 100644 --- a/src/mainboard/portwell/m107/fadt.c +++ b/src/mainboard/portwell/m107/fadt.c @@ -25,7 +25,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 3; + header->revision = ACPI_FADT_REV_ACPI_2_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 9515c01..26a1570 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -39,7 +39,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = 244; - header->revision = 1; + header->revision = ACPI_FADT_REV_ACPI_1_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8d4c4e6..83c455f 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -74,7 +74,7 @@ /* Fill the SSDT header */ memset((void *)ssdt, 0, sizeof(acpi_header_t)); memcpy(&ssdt->signature, "SSDT", 4); - ssdt->revision = 2; + ssdt->revision = get_acpi_table_revision(SSDT); memcpy(&ssdt->oem_id, OEM_ID, 6); memcpy(&ssdt->oem_table_id, "SERIALIO", 8); ssdt->oem_revision = 43; diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c index 6aaa702..9a70ba1 100644 --- a/src/southbridge/nvidia/mcp55/fadt.c +++ b/src/southbridge/nvidia/mcp55/fadt.c @@ -39,7 +39,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 1; + header->revision = ACPI_FADT_REV_ACPI_1_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/35539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99e59afc1a87203499d2da6dedaedfa643ca7eac Gerrit-Change-Number: 35539 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Philip Chen (Code Review) 04 Oct '19

04 Oct '19

Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/35794/2/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/35794/2/src/mainboard/google/hatch… PS2, Line 16: #define DPTF_CPU_PASSIVE 0 Just curious, why do we set DPTF_CPU_PASSIVE, DPTF_TSR1_PASSIVE, and DPTF_TSR2_PASSIVE 0? It seems low to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 04 Oct 2019 18:30:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch: Add option to enable WiFi SAR configs
by Furquan Shaikh (Code Review) 04 Oct '19

04 Oct '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35789 ) Change subject: mb/google/hatch: Add option to enable WiFi SAR configs ...................................................................... Patch Set 3: Code-Review-1 This is not required as mb/google/hatch is shared by different variants and so the the wifi sar table will not work for all. -- To view, visit https://review.coreboot.org/c/coreboot/+/35789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bb36dc2a68a3835d7126406c3403b2c0510202d Gerrit-Change-Number: 35789 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 04 Oct 2019 16:55:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: devicetree: Fix improper use of chip_operations
by Kyösti Mälkki (Code Review) 04 Oct '19

04 Oct '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35096 ) Change subject: devicetree: Fix improper use of chip_operations ...................................................................... devicetree: Fix improper use of chip_operations Auto-discoverable PCI devices do not require field .enable_dev of chip_operations to be set. They are matched with PCI drivers by the use of PCI vendor and device ID fields. The name given for the chip_operations struct must match the pathname the way it is present in the devicetree.cb files. If there was no match, util/sconfig would currently choose to use the empty weak declaration it creates in static.c file. Change-Id: I684a087a1f8ee4e1a5fd83450cd371fcfdbb6847 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/generic/bayhub/bh720.c M src/drivers/ricoh/rce822/rce822.c M src/soc/cavium/common/pci/uart.c M src/southbridge/intel/i82870/pcibridge.c M src/southbridge/ti/pci7420/cardbus.c M src/southbridge/ti/pci7420/firewire.c 6 files changed, 13 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/35096/1 diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index 09fa578..b365132 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -82,12 +82,6 @@ .devices = pci_device_ids, }; -static void bh720_enable(struct device *dev) -{ - dev->ops = &bh720_ops; -} - -struct chip_operations bayhub_bh720_ops = { +struct chip_operations drivers_generic_bayhub_ops = { CHIP_NAME("BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge") - .enable_dev = bh720_enable, }; diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index 72862f5..485bdd0 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -71,3 +71,7 @@ .vendor = PCI_VENDOR_ID_RICOH, .devices = pci_device_ids, }; + +struct chip_operations drivers_ricoh_rce822_ops = { + CHIP_NAME("RICOH RCE822") +}; diff --git a/src/soc/cavium/common/pci/uart.c b/src/soc/cavium/common/pci/uart.c index 6e41e1d..efa1b37 100644 --- a/src/soc/cavium/common/pci/uart.c +++ b/src/soc/cavium/common/pci/uart.c @@ -38,3 +38,7 @@ .vendor = PCI_VENDOR_CAVIUM, .device = PCI_DEVICE_ID_CAVIUM_THUNDERX_UART, }; + +struct chip_operations soc_cavium_common_pci_ops = { + CHIP_NAME("Cavium ThunderX") +}; diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c index a375568..cb6ace8 100644 --- a/src/southbridge/intel/i82870/pcibridge.c +++ b/src/southbridge/intel/i82870/pcibridge.c @@ -47,3 +47,7 @@ .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82870_1F0, }; + +struct chip_operations southbridge_intel_i82870_ops = { + CHIP_NAME("Intel 82870") +}; diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 2c5679b..44a38ea 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -111,12 +111,6 @@ .device = 0xac8d, }; -static void ti_pci7420_enable_dev(struct device *dev) -{ - /* Nothing here yet */ -} - struct chip_operations southbridge_ti_pci7420_ops = { CHIP_NAME("Texas Instruments PCI7420/7620 Cardbus Controller") - .enable_dev = ti_pci7420_enable_dev, }; diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c index 4058540..dac273a 100644 --- a/src/southbridge/ti/pci7420/firewire.c +++ b/src/southbridge/ti/pci7420/firewire.c @@ -48,13 +48,3 @@ .vendor = 0x104c, .device = 0x802e, }; - -static void ti_pci7420_firewire_enable_dev(struct device *dev) -{ - /* Nothing here yet */ -} - -struct chip_operations southbridge_ti_pci7420_firewire_ops = { - CHIP_NAME("Texas Instruments PCI7420/7620 FireWire (IEEE 1394)") - .enable_dev = ti_pci7420_firewire_enable_dev, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/35096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I684a087a1f8ee4e1a5fd83450cd371fcfdbb6847 Gerrit-Change-Number: 35096 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: Kconfig: Change STACK_SIZE value to decimal
by HAOUAS Elyes (Code Review) 04 Oct '19

04 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35593 ) Change subject: Kconfig: Change STACK_SIZE value to decimal ...................................................................... Kconfig: Change STACK_SIZE value to decimal STACK_SIZE value needs to be changed from hex to decimal, since -Wstack-usage doesn't recognize hexadecimal numbers anymore. Change-Id: I73606d347194af5de5882a3387a4a5db17f9d94b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig M src/soc/cavium/cn81xx/Kconfig 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/35593/1 diff --git a/src/Kconfig b/src/Kconfig index a1c016e..2be653e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -471,9 +471,9 @@ default 0x4000 config STACK_SIZE - hex - default 0x1000 if ARCH_X86 - default 0x0 + int + default 4096 if ARCH_X86 + default 0 config MAX_CPUS int diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index f64350e..900cade 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -30,7 +30,7 @@ default 0x10000 config STACK_SIZE - default 0x2000 + default 8192 config MMCONF_BASE_ADDRESS default 0x848000000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/35593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73606d347194af5de5882a3387a4a5db17f9d94b Gerrit-Change-Number: 35593 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 13

Change in ...coreboot[master]: mb/intel/{galileo,wtm2}: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 04 Oct '19

04 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33438 Change subject: mb/intel/{galileo,wtm2}: Use macro instead of magic number ...................................................................... mb/intel/{galileo,wtm2}: Use macro instead of magic number Change-Id: Ib8a08e9f854b2b0786c69943d6dbb66abe3ad4d8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/galileo/acpi_tables.c M src/mainboard/intel/wtm2/fadt.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/33438/1 diff --git a/src/mainboard/intel/galileo/acpi_tables.c b/src/mainboard/intel/galileo/acpi_tables.c index 78b05ab..bba8ced 100644 --- a/src/mainboard/intel/galileo/acpi_tables.c +++ b/src/mainboard/intel/galileo/acpi_tables.c @@ -26,7 +26,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 5; + header->revision = ACPI_FADT_REV_ACPI_5_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index a7c6536..7d9096c 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -24,7 +24,7 @@ memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 5; + header->revision = ACPI_FADT_REV_ACPI_5_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); -- To view, visit https://review.coreboot.org/c/coreboot/+/33438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8a08e9f854b2b0786c69943d6dbb66abe3ad4d8 Gerrit-Change-Number: 33438 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/google/kukui: Extend FMAP to 8MB layout
by Hung-Te Lin (Code Review) 04 Oct '19

04 Oct '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35612 ) Change subject: mb/google/kukui: Extend FMAP to 8MB layout ...................................................................... mb/google/kukui: Extend FMAP to 8MB layout The SPI flash component requirement for Kukui family is 8K so we should update FMAP for that: - Add more comments to alignment or size recommendation. - Enlarge RO to 4M, and RW_SECTION_{A,B} both 1M. - BOOTBLOCK: 32K->128K, aligned with other ARM boards. - Reorder the sections for better alignment. BUG=b:134624821 TEST=Built Kukui image and boots on Rev2 units. Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/chromeos.fmd 1 file changed, 24 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/35612/1 diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index d183273..0b54e84 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -1,30 +1,33 @@ -FLASH@0x0 0x800000 { - WP_RO@0x0 0x200000 { - RO_SECTION@0x0 0x1f8000 { - BOOTBLOCK@0 32K - FMAP@0x8000 0x1000 - COREBOOT(CBFS)@0x9000 0x1ec000 +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K # Offset better aligned with larger values. + COREBOOT(CBFS) GBB 0x2f00 RO_FRID 0x100 } - RO_VPD(PRESERVE)@0x1f8000 0x8000 + RO_VPD(PRESERVE) 32K # Recommended size: at least 16K. } - RW_SECTION_A@0x200000 0x7c000 { - VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS) 0x79f00 + RW_SECTION_A 1M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) RW_FWID_A 0x100 } - RW_SHARED@0x27c000 0x1000 { - SHARED_DATA@0x0 0x1000 - } - RW_NVRAM(PRESERVE)@0x27d000 0x2000 - # ELOG driver has hard-coded the size to 4k. - RW_ELOG(PRESERVE)@0x27f000 0x1000 - RW_SECTION_B@0x280000 0x7c000 { - VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS) 0x79f00 + RW_SECTION_B 1M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) RW_FWID_B 0x100 } - RW_VPD(PRESERVE)@0x2fc000 0x4000 - RW_LEGACY(CBFS)@0x300000 0x100000 + RW_PRESERVE(PRESERVE) 36K { + RW_VPD 16K # Recommended size: at least 8K. + RW_NVRAM 8K # 8K at aligned address. + RW_DDR_TRAINING 8K + RW_ELOG 4K # ELOG driver hard-coded 4K size. + } + RW_UNUSED + RW_SHARED 4K { + SHARED_DATA 4K # 4K or less for netboot params. + } + RW_LEGACY(CBFS) 1M # Minimal 1M. } -- To view, visit https://review.coreboot.org/c/coreboot/+/35612 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09 Gerrit-Change-Number: 35612 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: mb/facebook/fbg1701: Remove ONBOARD_MICRON_MEM
by Frans Hendriks (Code Review) 04 Oct '19

04 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35742 ) Change subject: mb/facebook/fbg1701: Remove ONBOARD_MICRON_MEM ...................................................................... mb/facebook/fbg1701: Remove ONBOARD_MICRON_MEM Config ONBOARD_MICRON_MEM and ONBOARD_SAMSUNG_MEM are available. These configs are used to determine if Samsung or Micron onboard memory is assembled. This can not detected run-time. One CONFIG value will be enough to determine if Samsung memory is assembled. Only oldest HW revision contains Samsung module, so set CONFIG_ONBOARD_SAMSUNG memory to default No. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 Change-Id: Id65e92bd4b8d4fe3a6b87dec9bf77e3a62e1be96 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/facebook/fbg1701/romstage.c 2 files changed, 2 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/35742/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index ce90758..066008e 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -31,21 +31,12 @@ select INTEL_GMA_HAVE_VBT select GENERIC_SPD_BIN -choice - prompt "Onboard memory manufacturer" - default ONBOARD_MICRON_MEM - config ONBOARD_SAMSUNG_MEM bool "Samsung" + default n help Samsung K4B8G1646D memory -config ONBOARD_MICRON_MEM - bool "Micron" - help - Micron MT41K512M16HA memory -endchoice - config MAINBOARD_DIR string default facebook/fbg1701 diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index e2e37d6..7b68914 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -31,7 +31,7 @@ struct region_device spd_rdev; u8 spd_index = 0; - if (CONFIG(ONBOARD_MICRON_MEM)) + if (!CONFIG(ONBOARD_SAMSUNG_MEM)) spd_index = 1; if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) die("spd.bin not found\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/35742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id65e92bd4b8d4fe3a6b87dec9bf77e3a62e1be96 Gerrit-Change-Number: 35742 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: completely rework documentation
by Michael Niewöhner (Code Review) 04 Oct '19

04 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35547 ) Change subject: mb/supermicro/x11-lga1151-series: completely rework documentation ...................................................................... mb/supermicro/x11-lga1151-series: completely rework documentation This completely reworks the documentation for both boards of the series and moves common stuff to the series documentation. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I40ddd0b5cce0b1a3306eae22fc0a0bc6b2a6263c --- D Documentation/mainboard/supermicro/x11-lga1151-series/index.md A Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md 4 files changed, 149 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35547/1 diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/index.md b/Documentation/mainboard/supermicro/x11-lga1151-series/index.md deleted file mode 100644 index 63b730c..0000000 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/index.md +++ /dev/null @@ -1,8 +0,0 @@ -# X11 LGA1151 series - -The supermicros X11 series with socket LGA1151 are mostly the same boards with some minor -differences in internal and external interfaces like available PCIe slots, 1 GbE, 10 GbE, -IPMI etc. This is why those boards are grouped as "X11 LGA1151 series". - -- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) -- [X11SSM-F](x11ssm-f/x11ssm-f.md) diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md new file mode 100644 index 0000000..21685a8 --- /dev/null +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -0,0 +1,62 @@ +# X11 LGA1151 series + +The [Supermicro X11 LGA1151 series] are mostly the same boards with some minor differences in +internal and external interfaces like available PCIe slots, NICs (1 GbE, 10 GbE), IPMI, RAID +Controller etc. + +## Supported boards + +- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) +- [X11SSM-F](x11ssm-f/x11ssm-f.md) + +## Required proprietary blobs + +- [Intel FSP2.0] +- Intel ME + +## De-blobbing + +- [Intel FSP2.0] can not be removed as long as there is no free replacement +- Intel ME can be cleaned using me_cleaner (~4.5 MB more free space) +- Intel Ethernet Controller Firmware can be removed when it's extended functionality is not + needed. For more details refer to the respective datasheet (e.g 333016-008 for I210). +- Boards with [AST2400] BMC/IPMI: Firmware can be replaced by [OpenBMC] + +## Flashing coreboot + +Look at the [flashing tutorial] and the board-specific section. + +## Known issues + +These issues apply to all boards. Have a look at the board-specific issues, too. + +- Intel SGX causes secondary APs to crash (disabled for now) when HT is enabled +- TianoCore doesn't work with Aspeed NGI, as it's text mode only + +## ToDo + +- Fix issues above +- Fix issues in board specific sections +- Fix TODOs mentioned in code +- Add more boards! :-) + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C232/C236 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +[Supermicro X11 LGA1151 series]: https://www.supermicro.com/products/motherboard/Xeon3000/#1151 +[OpenBMC]: https://www.openbmc.org/ +[flashrom]: https://flashrom.org/Flashrom +[flashing tutorial]: ../../../../flash_tutorial/ext_power.md +[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md index 79e7f3e..30400e0 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md @@ -2,46 +2,40 @@ This section details how to run coreboot on the [Supermicro X11SSH-TF]. -## Required proprietary blobs - -* [Intel FSP2.0] -* Intel ME - ## Flashing coreboot -The board can be flashed externally using *some* programmers. -The CH341 was found working, while Dediprog won't detect the chip. - -For more details have a look at the [flashing tutorial]. +The board can be flashed externally using *some* programmers. The CH341 was found working, while +Dediprog didn't detect the chip. The flash IC can be found between the two PCIe slots near the southbridge: ![](x11ssh-tf_flash.jpg) ## BMC (IPMI) -This board has an ASPEED [AST2400], which has BMC functionality. The -BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the -mainboard near the [AST2400]. This chip is an [MX25L25635F]. +This board has an ASPEED [AST2400], which has BMC functionality. The BMC firmware resides in a +32 MiB SOIC-16 chip in the corner of the mainboard near the [AST2400]. This chip is an +[MX25L25635F]. ## Known issues -- Intel SGX causes secondary APs to crash (disabled for now). -- Tianocore doesn't work with Aspeed NGI, as it's text mode only. -- SMBus / I2C does not work (interrupt timeout) +See general issue section. + +## ToDo + +- Fix TODOs mentioned in code ## Tested and working - USB ports -- M.2 2280 NVMe slot -- 2x 10GB Ethernet -- SATA -- RS232 -- VGA on Aspeed -- Super I/O initialisation +- Ethernet +- SATA ports +- RS232 external - ECC DRAM detection - PCIe slots -- TPM on TPM expansion header +- M.2 2280 NVMe slot - BMC (IPMI) +- VGA on Aspeed +- TPM on TPM expansion header ## Technology @@ -51,23 +45,45 @@ +------------------+--------------------------------------------------+ | PCH | Intel C236 | +------------------+--------------------------------------------------+ -| Super I/O | ASPEED AST2400 | -+------------------+--------------------------------------------------+ | Coprocessor | Intel SPS (server version of the ME) | +------------------+--------------------------------------------------+ -| Coprocessor | ASPEED AST2400 | +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel® X550 10GBase-T Ethernet | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x8 | +| | 1x 3.0 x2 (in x4) | +| | 1x 3.0 M.2 2260 x4 (Key M, with S-ATA) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 8x SATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 6x PWM Fan connector | +| | 2x I-SGPIO | +| | 2x S-ATA DOM Power connector | +| | 1x XDP Port | +| | 1x External BMC I2C Header (for IPMI card) | +| | 1x Chassis Intrusion Header | +------------------+--------------------------------------------------+ ``` ## Extra links +- [Supermicro X11SSH-TF] - [Board manual] -[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF [Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf -[flashrom]: https://flashrom.org/Flashrom +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 [MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf [N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/… -[flashing tutorial]: ../../../../flash_tutorial/ext_power.md -[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md -[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md index c39de36..913d58e 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-tf.md @@ -2,51 +2,28 @@ This section details how to run coreboot on the [Supermicro X11SSM-F]. -## Required proprietary blobs - -* [Intel FSP2.0] -* Intel ME - -## De-blobbing - -* [Intel FSP2.0] can not be removed as long as there is no free replacement -* Intel ME can be cleaned using me_cleaner (~4.5 MB more free space) -* Intel Ethernet Controller I210 Firmware can be removed when it's extended - functionality is not needed. For more details refer to Intel document - 333016-008. -* BMC/IPMI Firmware can be replaced by OpenBMC - ## Flashing coreboot -The board can be flashed externally using *some* programmers. -FTDI FT2232H and FT232H based programmers worked. - -For more details have a look at the [flashing tutorial]. +The board can be flashed externally using *some* programmers. FTDI FT2232H and FT232H based +programmers worked. The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4. ## BMC (IPMI) -This board has an ASPEED [AST2400], which has BMC functionality. The -BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the -mainboard near the PCH PCIe Slot 4. This chip is an [MX25L25635F]. +This board has an ASPEED [AST2400], which has BMC functionality. The BMC firmware resides in a +32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a +[MX25L25635F]. ## Known issues -- Intel SGX causes secondary APs to crash (disabled for now). -- Tianocore doesn't work with Aspeed NGI, as it's text mode only. -- SATA Hotplug does not work -- SMBus / I2C does not work (interrupt timeout) - P2SB / 1f.1 hidden access error - "only partially covers this bridge" error - LNXTHERM missing (acpi, src/mainboard/gigabyte/ga-h61m-s2pv/acpi/thermal.asl maybe?) -- Error no CMOS option 'power_on_after_fail' - PCI function 4 swapped to 0 (huh?) - PCI function 2 swapped to 0 (huh?) - register differences to vendor firmare: - BIOS_PCI_EXP_EN 1->0 - - ETR3_CF9LOCK 1->0 - - HOT_PLUG_EN 1->0 (fsp pcie hotplug?) - PCI_EXP_EN 1->0 - GPIO_TIER2_SCI_EN 1->0 @@ -60,17 +37,16 @@ ## Tested and working - USB ports -- 2x GbE -- SATA -- RS232 -- Super I/O initialisation +- Ethernet +- SATA ports +- RS232 external - ECC DRAM detection - PCIe slots - BMC (IPMI) +- VGA on Aspeed ## Not tested yet -- VGA on Aspeed - TPM on TPM expansion header ## Technology @@ -81,23 +57,47 @@ +------------------+--------------------------------------------------+ | PCH | Intel C236 | +------------------+--------------------------------------------------+ -| Super I/O | ASPEED AST2400 | -+------------------+--------------------------------------------------+ | Coprocessor | Intel SPS (server version of the ME) | +------------------+--------------------------------------------------+ -| Coprocessor | ASPEED AST2400 | +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Ethernet | 2x Intel I210-AT 1 GbE | +| | 1x dedicated BMC | ++------------------+--------------------------------------------------+ +| PCIe slots | 1x 3.0 x8 | +| | 1x 3.0 x8 (in x16) | +| | 2x 3.0 x4 (in x8) | ++------------------+--------------------------------------------------+ +| USB slots | 2x USB 2.0 (ext) | +| | 2x USB 3.0 (ext) | +| | 1x USB 3.0 (int) | +| | 1x dual USB 3.0 header | +| | 2x dual USB 2.0 header | ++------------------+--------------------------------------------------+ +| SATA slots | 8x S-ATA III | ++------------------+--------------------------------------------------+ +| Other slots | 1x RS232 (ext) | +| | 1x RS232 header | +| | 1x TPM header | +| | 1x Power SMB header | +| | 5x PWM Fan connector | +| | 2x I-SGPIO | +| | 2x S-ATA DOM Power connector | +| | 1x XDP Port | +| | 1x External BMC I2C Header (for IPMI card) | +| | 1x Chassis Intrusion Header | +------------------+--------------------------------------------------+ ``` ## Extra links +- [Supermicro X11SSM-F] - [Board manual] +- [Log dumps] -[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[Supermicro X11SSM-F]: https://www.supermicro.com/en/products/motherboard/X11SSM-F [Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1785.pdf -[flashrom]: https://flashrom.org/Flashrom +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 [MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf [MX25L12873F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L12873F.pdf -[flashing tutorial]: ../../../../flash_tutorial/ext_power.md -[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md -[Supermicro X11SSM-F]: https://www.supermicro.com/en/products/motherboard/X11SSM-F +[Log dumps]: log_dumps.tgz -- To view, visit https://review.coreboot.org/c/coreboot/+/35547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40ddd0b5cce0b1a3306eae22fc0a0bc6b2a6263c Gerrit-Change-Number: 35547 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: soc/skl/vr_config: fix KBL-U GT3 detection bug
by Patrick Georgi (Code Review) 04 Oct '19

04 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35782 ) Change subject: soc/skl/vr_config: fix KBL-U GT3 detection bug ...................................................................... soc/skl/vr_config: fix KBL-U GT3 detection bug Some VR parameter values for KBL-U with GT3 graphics are different from values for other CPUs in this series [1]. However, GT3 iGPU will never be detected, since the igd_id variable is compared with the LPC device PCI ID. The patch fixes this bug. [1] page 109, 7th Generation Intel(R) Processor Families for U/Y Platforms and 8th Generation Intel(R) Processor Family for U Quad Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019. Document Number: 334661-006 Change-Id: I33527d90550a1de78c9375d3d3b0e046787a559b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35782 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index de5ad2c..121a344 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -213,7 +213,8 @@ VR_CFG_AMP(31), }; - if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22) + if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || + (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) icc_max[VR_IA_CORE] = VR_CFG_AMP(29); return icc_max[domain]; @@ -285,7 +286,8 @@ VR_CFG_MOHMS(3.1), }; - if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22) { + if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || + (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) { loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2); loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33527d90550a1de78c9375d3d3b0e046787a559b Gerrit-Change-Number: 35782 Gerrit-PatchSet: 4 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2019