Change in coreboot[master]: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1394 - coreboot-gerrit

7 Oct 2019

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35851 )
Change subject: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1394
......................................................................
src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1394
Change-Id: I19a931d9aecead1e81937db69436abf67f293d35
Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
---
M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
M src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h
3 files changed, 91 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/35851/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
index 962463e..aee01c8 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
@@ -37,19 +37,19 @@
#pragma pack(1)
-
-#include <MemInfoHob.h>
-
-///
-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
-///
-typedef struct {
-  UINT8             Revision;         ///< Chipset Init Info Revision
-  UINT8             Rsvd[3];          ///< Reserved
-  UINT16            MeChipInitCrc;    ///< 16 bit CRC value of MeChipInit Table
-  UINT16            BiosChipInitCrc;  ///< 16 bit CRC value of PchChipInit Table
-} CHIPSET_INIT_INFO;
-
+
+#include <MemInfoHob.h>
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+  UINT8             Revision;         ///< Chipset Init Info Revision
+  UINT8             Rsvd[3];          ///< Reserved
+  UINT16            MeChipInitCrc;    ///< 16 bit CRC value of MeChipInit Table
+  UINT16            BiosChipInitCrc;  ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
/** Fsp M Configuration
 **/
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
index 0df3063..a92b0ae 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h
@@ -37,49 +37,49 @@
#pragma pack(1)
-
-///
-/// Azalia Header structure
-///
-typedef struct {
-  UINT16 VendorId;           ///< Codec Vendor ID
-  UINT16 DeviceId;           ///< Codec Device ID
-  UINT8  RevisionId;         ///< Revision ID of the codec. 0xFF matches any revision.
-  UINT8  SdiNum;             ///< SDI number, 0xFF matches any SDI.
-  UINT16 DataDwords;         ///< Number of data DWORDs pointed by the codec data buffer.
-  UINT32 Reserved;           ///< Reserved for future use. Must be set to 0.
-} AZALIA_HEADER;
-
-///
-/// Audio Azalia Verb Table structure
-///
-typedef struct {
-  AZALIA_HEADER Header;      ///< AZALIA PCH header
-  UINT32        *Data;       ///< Pointer to the data buffer. Its length is specified in the header
-} AUDIO_AZALIA_VERB_TABLE;
-
-///
-/// Refer to the definition of PCH_INT_PIN
-///
-typedef enum {
-  SiPchNoInt,        ///< No Interrupt Pin
-  SiPchIntA,
-  SiPchIntB,
-  SiPchIntC,
-  SiPchIntD
-} SI_PCH_INT_PIN;
-///
-/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
-///
-typedef struct {
-  UINT8        Device;                  ///< Device number
-  UINT8        Function;                ///< Device function
-  UINT8        IntX;                    ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
-  UINT8        Irq;                     ///< IRQ to be set for device.
-} SI_PCH_DEVICE_INTERRUPT_CONFIG;
-
-#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG  64       ///< Number of all PCH devices
-
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+  UINT16 VendorId;           ///< Codec Vendor ID
+  UINT16 DeviceId;           ///< Codec Device ID
+  UINT8  RevisionId;         ///< Revision ID of the codec. 0xFF matches any revision.
+  UINT8  SdiNum;             ///< SDI number, 0xFF matches any SDI.
+  UINT16 DataDwords;         ///< Number of data DWORDs pointed by the codec data buffer.
+  UINT32 Reserved;           ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+  AZALIA_HEADER Header;      ///< AZALIA PCH header
+  UINT32        *Data;       ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+  SiPchNoInt,        ///< No Interrupt Pin
+  SiPchIntA,
+  SiPchIntB,
+  SiPchIntC,
+  SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+  UINT8        Device;                  ///< Device number
+  UINT8        Function;                ///< Device function
+  UINT8        IntX;                    ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+  UINT8        Irq;                     ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG  64       ///< Number of all PCH devices
+
/** Fsp S Configuration
 **/
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h
index 508705c..ee3405d 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FsptUpd.h
@@ -129,31 +129,47 @@
 **/
   UINT8                       PcdSerialIoUartAutoFlow;
-/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
-  Select RX pin muxing for SerialIo UART used for debug
+/** Offset 0x0058 - PcdSerialIoUartPinMux - FSPT
+  Applies only to UART0 muxed with CNVI <b> 0 = GPIO C8 to C11 </b> 1 = GPIO F5 -
+  F7 (PCH LP) J5 - J7 (PCH H)
+  0: GPIO C8 to C11, 1: GPIO F5 - F7 (PCH LP) J5 - J7 (PCH H)
 **/
-  UINT32                      PcdSerialIoUartRxPinMux;
+  UINT8                       PcdSerialIoUartPinMux;
-/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
-  Select TX pin muxing for SerialIo UART used for debug
+/** Offset 0x0059 - PcdLpcUartDebugEnable
+  Enable to initialize LPC Uart device in FSP.
+  0:Disable, 1:Enable
 **/
-  UINT32                      PcdSerialIoUartTxPinMux;
+  UINT8                       PcdLpcUartDebugEnable;
-/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
-  Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
-  for possible values.
+/** Offset 0x005A - Debug Interfaces
+  Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+  BIT2 - Not used.
 **/
-  UINT32                      PcdSerialIoUartRtsPinMux;
+  UINT8                       PcdDebugInterfaceFlags;
-/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
-  Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
-  for possible values.
+/** Offset 0x005B - PcdSerialDebugLevel
+  Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose.
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info, 5:Load Error Warnings Info and Verbose
 **/
-  UINT32                      PcdSerialIoUartCtsPinMux;
+  UINT8                       PcdSerialDebugLevel;
-/** Offset 0x0068
+/** Offset 0x005C - ISA Serial Base selection
+  Select ISA Serial Base address. Default is 0x3F8.
+  0:0x3F8, 1:0x2F8
 **/
-  UINT8                       ReservedFsptUpd1[24];
+  UINT8                       PcdIsaSerialUartBase;
+
+/** Offset 0x005D
+**/
+  UINT8                       UnusedUpdSpace1[7];
+
+/** Offset 0x0064
+**/
+  UINT8                       ReservedFsptUpd1[20];
 } FSP_T_CONFIG;
/** Fsp T UPD Configuration
@@ -172,11 +188,11 @@
 **/
   FSP_T_CONFIG                FsptConfig;
-/** Offset 0x0080
+/** Offset 0x0078
 **/
-  UINT8                       UnusedUpdSpace1[6];
+  UINT8                       UnusedUpdSpace2[6];
-/** Offset 0x0086
+/** Offset 0x007E
 **/
   UINT16                      UpdTerminator;
 } FSPT_UPD;
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I19a931d9aecead1e81937db69436abf67f293d35
Gerrit-Change-Number: 35851
Gerrit-PatchSet: 1
Gerrit-Owner: Ronak Kanabar ronak.kanabar@intel.com
Gerrit-MessageType: newchange



    