coreboot-gerrit October 2019

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Change in coreboot[master]: [TEST] intel/broadwell: Hook libgfxinit up
by Paul Menzel (Code Review) 09 Oct '19

09 Oct '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20100 ) Change subject: [TEST] intel/broadwell: Hook libgfxinit up ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/20100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Gerrit-Change-Number: 20100 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Oct 2019 09:03:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Hung-Te Lin (Code Review) 09 Oct '19

09 Oct '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35775 ) Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 12 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 09 Oct 2019 07:34:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Yu-Ping Wu (Code Review) 09 Oct '19

09 Oct '19

Hello Julius Werner, Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35775 to look at the new patch set (#12). Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... soc/mediatek/mt8183: Add the shared 'dramc_param' module The dramc_param module simplifies the communication between coreboot and MTK DRAM full calibration blob, and is shared by both implementations to ensure the same format of parameters. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_param.c A src/soc/mediatek/mt8183/include/soc/dramc_param.h 3 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35775/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 12 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] 3rdparty/libgfxinit: Update submodule pointer
by Matt DeVillier (Code Review) 09 Oct '19

09 Oct '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35898 ) Change subject: [WIP] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... Patch Set 1: Code-Review+1 current libgfxinit patch train tested and verified working on BDW-U, SKL-U/Y, KBL-U -- To view, visit https://review.coreboot.org/c/coreboot/+/35898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Gerrit-Change-Number: 35898 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Oct 2019 06:13:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST] intel/broadwell: Hook libgfxinit up
by Matt DeVillier (Code Review) 09 Oct '19

09 Oct '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20100 ) Change subject: [TEST] intel/broadwell: Hook libgfxinit up ...................................................................... Patch Set 5: Code-Review+2 verified on google/lulu and purism/librem_13v1 -- To view, visit https://review.coreboot.org/c/coreboot/+/20100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Gerrit-Change-Number: 20100 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Oct 2019 06:09:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: Change to use the shared 'dramc_param' module
by Hung-Te Lin (Code Review) 09 Oct '19

09 Oct '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35646 ) Change subject: WIP: Change to use the shared 'dramc_param' module ...................................................................... WIP: Change to use the shared 'dramc_param' module A demonstration for how to use the dramc_param module shared with mtk-dramk blob. Change-Id: I611490f00a5507caded7321dfc0359fcdf10e4e0 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_param.c A src/soc/mediatek/mt8183/include/soc/dramc_param.h M src/soc/mediatek/mt8183/include/soc/emi.h 5 files changed, 151 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35646/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index cc1def7..f2dd4e4 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -18,22 +18,22 @@ #include <cbfs.h> #include <console/console.h> #include <fmap.h> +#include <soc/dramc_param.h> #include <soc/emi.h> #include <soc/mmu_operations.h> #include <soc/mt6358.h> #include <soc/pll.h> #include <soc/rtc.h> +#include <string.h> #include "early_init.h" -struct params_data calibration_results; - #define CALIBRATION_REGION "RW_DDR_TRAINING" + static bool read_calibration_data_from_flash(void *data, size_t length) { size_t ret = fmap_read_area(CALIBRATION_REGION, data, length); - printk(BIOS_INFO, "%s: ret=%#lx, length=%#lx\n", - __func__, ret, length); + printk(BIOS_INFO, "%s: ret=%#lx, length=%#lx\n", __func__, ret, length); return ret == length; } @@ -47,25 +47,16 @@ return ret == length; } +/* dramc_param is ~2K and too large to fit in stack. */ +static struct dramc_param dparam; + void clean_calibration_data(void) { - size_t ret; - struct params_data *params_result = &calibration_results; - size_t length = sizeof(calibration_results); - - if (read_calibration_data_from_flash(params_result, length) && - have_calibration_params(params_result->freq_params)) { - /* reset all params to 0 */ - memset(params_result, 0x0, length); - - ret = fmap_overwrite_area(CALIBRATION_REGION, - params_result, length); - printk(BIOS_INFO, "%s: ret=%#lx, length=%#lx\n", - __func__, ret, length); - } + dparam.header.status = DRAMC_ERR_RECALIBRATE; + fmap_overwrite_area(CALIBRATION_REGION, &dparam, sizeof(dparam)); } -static int dram_run_full_calibration(struct params_data *params_result) +static int dram_run_full_calibration(struct dramc_param *param) { /* Load and run the provided blob for full-calibration if available */ struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); @@ -76,10 +67,9 @@ if (cbfs_prog_stage_load(&dram)) return -2; - prog_set_entry(&dram, prog_entry(&dram), params_result); + prog_set_entry(&dram, prog_entry(&dram), param); prog_run(&dram); - - return 0; + return param->header.status == DRAMC_SUCCESS; } static void init_sdram_params(struct sdram_params *dst, @@ -92,30 +82,28 @@ static void dram_initialize(void) { - u16 is_emcp = 0; - struct params_data *params_result = &calibration_results; - size_t length = sizeof(calibration_results); - struct sdram_params *freq_params = params_result->freq_params; + struct sdram_params *freq_params = &dparam.freq_params[0]; - if (!read_calibration_data_from_flash(params_result, length) && - (params_result->param_header.pl_version != PARAM_PL_VERSION)) { + u32 flags = 0; + if (CONFIG(MT8183_DRAM_EMCP)) + flags |= DRAMC_FLAG_HAS_EMCP; - /* EMCP devices should run 3600Mbps for high frequency calibartion */ - is_emcp = CONFIG(MT8183_DRAM_EMCP) ? PARAM_EMCP_MAGIC : 0; - params_result->param_header.is_emcp = is_emcp; - printk(BIOS_INFO, "is_emcp current DDR type is %s\n", - (is_emcp == PARAM_EMCP_MAGIC) ? "EMCP" : "Discrete"); - /* try to re-run DRAM full calibration if avalible */ - int err = dram_run_full_calibration(params_result); + if (!read_calibration_data_from_flash(&dparam, sizeof(dparam)) || + !is_valid_dramc_param(&dparam) || + dparam.header.flags != flags) { + + initialize_dramc_param(&dparam, flags); + /* try to re-run DRAM full calibration if available */ + int err = dram_run_full_calibration(&dparam); if (err == 0) { printk(BIOS_INFO, "successfully load dram_blob and " "run DRAM calibration\n"); - printk(BIOS_INFO, "save params to flash. pl_version: 0x%x, body_size: 0x%x\n", - params_result->param_header.pl_version, - params_result->param_header.body_size); + printk(BIOS_INFO, "save params to flash. pl_version: %#x, body_size: %#x\n", + dparam.header.version, + dparam.header.size); - write_calibration_data_to_flash(freq_params, length); + write_calibration_data_to_flash(&dparam, sizeof(dparam)); return; } @@ -124,11 +112,8 @@ /* init params setting from sdram configs if no have dram calibraion result */ init_sdram_params(freq_params, get_sdram_config()); - mt_mem_init(freq_params); - } else { - printk(BIOS_INFO, "have dram calibraion params\n"); - mt_mem_init(freq_params); } + mt_mem_init(freq_params); } void platform_romstage_main(void) diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b6c3a33..27591df 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += auxadc.c romstage-y += ../common/cbmem.c emi.c romstage-y += dramc_init_setting.c +romstage-y += dramc_param.c romstage-y += dramc_pi_basic_api.c romstage-y += dramc_pi_calibration_api.c romstage-y += memory.c diff --git a/src/soc/mediatek/mt8183/dramc_param.c b/src/soc/mediatek/mt8183/dramc_param.c new file mode 100644 index 0000000..31d71c7 --- /dev/null +++ b/src/soc/mediatek/mt8183/dramc_param.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include "soc/dramc_param.h" + +struct dramc_param *get_dramc_param_from_blob(void *blob) +{ + return (struct dramc_param *)blob; +} + +int validate_dramc_param(const void *blob) +{ + const struct dramc_param *param = blob; + const struct dramc_param_header *hdr = &param->header; + + if (hdr->magic != DRAMC_PARAM_HEADER_MAGIC) + return DRAMC_ERR_INVALID_MAGIC; + + if (hdr->version != DRAMC_PARAM_HEADER_VERSION) + return DRAMC_ERR_INVALID_VERSION; + + if (hdr->size != sizeof(*param)) + return DRAMC_ERR_INVALID_SIZE; + + /* TODO(hungte) Verify and check hdr->checksum. */ + return DRAMC_SUCCESS; +} + +int is_valid_dramc_param(const void *blob) +{ + return validate_dramc_param(blob) == DRAMC_SUCCESS; +} + +int initialize_dramc_param(void *blob, u32 flags) +{ + struct dramc_param *param = blob; + struct dramc_param_header *hdr = &param->header; + + memset(blob, 0, sizeof(*param)); + hdr->magic = DRAMC_PARAM_HEADER_MAGIC; + hdr->size = sizeof(*param); + hdr->version = DRAMC_PARAM_HEADER_VERSION; + hdr->flags = flags; + return 0; +} + diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h new file mode 100644 index 0000000..aa8a4e8 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_DRAMC_PARAM_H +#define SOC_MEDIATEK_MT8183_DRAMC_PARAM_H + +#include <stdint.h> +#include <sys/types.h> + +#include "emi.h" + +enum { + DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, + DRAMC_PARAM_HEADER_VERSION = 1, +}; + +enum DRAMC_PARAM_STATUS_CODES { + DRAMC_SUCCESS = 0, + DRAMC_ERR_INVALID_MAGIC, + DRAMC_ERR_INVALID_VERSION, + DRAMC_ERR_INVALID_SIZE, + DRAMC_ERR_INVALID_CHECKSUM, + DRAMC_ERR_INVALID_FLAGS, + DRAMC_ERR_RECALIBRATE, +}; + +/* Bit flags. */ +enum DRAMC_PARAM_FLAGS { + DRAMC_FLAG_HAS_EMCP = 0x0001, +}; + +struct dramc_param_header { + u32 status; /* DRAMC_PARAM_STATUS_CODES */ + u32 magic; + u32 version; + u32 size; /* size of whole dramc_param */ + u32 flags; /* DRAMC_PARAM_FLAGS */ + u32 checksum; +}; + +struct dramc_param { + struct dramc_param_header header; + struct sdram_params freq_params[DRAM_DFS_SHUFFLE_MAX]; +}; + +struct dramc_param *get_dramc_param_from_blob(void *blob); +int validate_dramc_param(const void *blob); +int is_valid_dramc_param(const void *blob); +int initialize_dramc_param(void *blob, u32 flags); + +#endif /* SOC_MEDIATEK_MT8183_DRAMC_PARAM_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index a4b9150..be10bf5 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -22,14 +22,6 @@ #define PARAM_START_PATTERN 0x5a5a #define PARAM_END_PATTERN 0x3c3c -#define PARAM_PL_VERSION 0x20190927 -#define PARAM_EMCP_MAGIC 0x5acc - -struct sdram_params_header { - u32 pl_version; - u16 is_emcp; - u16 body_size; -}; struct sdram_params { u16 calibration_result_start; @@ -77,11 +69,6 @@ u16 calibration_result_end; }; -struct params_data { - struct sdram_params_header param_header; - struct sdram_params freq_params[DRAM_DFS_SHUFFLE_MAX]; -}; - enum { LP4X_DDR1600, LP4X_DDR2400, -- To view, visit https://review.coreboot.org/c/coreboot/+/35646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I611490f00a5507caded7321dfc0359fcdf10e4e0 Gerrit-Change-Number: 35646 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Add the shared 'dramc_param' module
by Hung-Te Lin (Code Review) 09 Oct '19

09 Oct '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35775 ) Change subject: soc/mediatek/mt8183: Add the shared 'dramc_param' module ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/35775/11/src/soc/mediatek/mt8183/i… File src/soc/mediatek/mt8183/include/soc/dramc_param.h: https://review.coreboot.org/c/coreboot/+/35775/11/src/soc/mediatek/mt8183/i… PS11, Line 71: const struct sdram_params* (*get_sdram_config)(void); Looking at follow up CLs, I'm not so sure if we need this (see my comments there) -- To view, visit https://review.coreboot.org/c/coreboot/+/35775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfd634da1855a76706aab0b050197251e2ed4dd Gerrit-Change-Number: 35775 Gerrit-PatchSet: 11 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 09 Oct 2019 03:53:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST] intel/broadwell: Hook libgfxinit up
by Nico Huber (Code Review) 08 Oct '19

08 Oct '19

Hello Matt DeVillier, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/20100 to look at the new patch set (#5). Change subject: [TEST] intel/broadwell: Hook libgfxinit up ...................................................................... [TEST] intel/broadwell: Hook libgfxinit up Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/broadwell/igd.c 1 file changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/20100/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/20100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Gerrit-Change-Number: 20100 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: HACK: soc/intel/broadwell: Force libgfxinit
by Nico Huber (Code Review) 08 Oct '19

08 Oct '19

Nico Huber has restored this change. ( https://review.coreboot.org/c/coreboot/+/20100 ) Change subject: HACK: soc/intel/broadwell: Force libgfxinit ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/20100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Gerrit-Change-Number: 20100 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in coreboot[master]: soc/intel/skylake: fix platform detection when PCIe port 1 is disabled
by Michael Niewöhner (Code Review) 08 Oct '19

08 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35894 ) Change subject: soc/intel/skylake: fix platform detection when PCIe port 1 is disabled ...................................................................... soc/intel/skylake: fix platform detection when PCIe port 1 is disabled PCIe root port 1 may be disabled. This prevents reading the device id, which is used for platform detection used for PCIe root port swapping, when PCIe function 0 of a port is disabled. This fixes platform detection in such cases by using the LPC device id instead, which normally shouldn't be disabled. FSP does exactly the same (checked by FSP disassembling / reverse-engineering). Change-Id: I792a1825a7910135a9a82864c8f1f577f5a10235 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/include/device/pci_ids.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35894/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6abedb4..350f362 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2700,6 +2700,9 @@ #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48 #define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM 0x9d46 +#define PCI_DEVICE_ID_INTEL_SPT_H_LPC_BASE 0xa140 +#define PCI_DEVICE_ID_INTEL_SPT_H_LPC_BASE 0xa1ff +#define PCI_DEVICE_ID_INTEL_SPT_H_LPC_BASE 0x001e #define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143 #define PCI_DEVICE_ID_INTEL_SPT_H_H170 0xa144 #define PCI_DEVICE_ID_INTEL_SPT_H_Z170 0xa145 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 55fedd3..1499a6f 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -140,7 +140,8 @@ { uint16_t id, id_mask; - id = pci_read_config16(PCH_DEV_PCIE1, PCI_DEVICE_ID); + id = pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); + /* * We may read an ID other than func 0 after FSP-S. * Strip out 4 least significant bits. -- To view, visit https://review.coreboot.org/c/coreboot/+/35894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792a1825a7910135a9a82864c8f1f577f5a10235 Gerrit-Change-Number: 35894 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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coreboot-gerrit October 2019