Change in coreboot[master]: soc/intel/skylake: fix platform detection when PCIe port 1 is disabled

[Michael Niewöhner (Code Review)]

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35894 )

Change subject: soc/intel/skylake: fix platform detection when PCIe port 1 is disabled
......................................................................

soc/intel/skylake: fix platform detection when PCIe port 1 is disabled

PCIe root port 1 may be disabled. This prevents reading the device id,
which is used for platform detection used for PCIe root port swapping,
when PCIe function 0 of a port is disabled.

This fixes platform detection in such cases by using the LPC device id
instead, which normally shouldn't be disabled. FSP does exactly the
same (checked by FSP disassembling / reverse-engineering).

Change-Id: I792a1825a7910135a9a82864c8f1f577f5a10235
Signed-off-by: Michael Niewöhner 
---
M src/include/device/pci_ids.h
M src/soc/intel/skylake/chip_fsp20.c
2 files changed, 5 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35894/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 6abedb4..350f362 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2700,6 +2700,9 @@
 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE		0x9d43
 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM		0x9d48
 #define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM		0x9d46
+#define PCI_DEVICE_ID_INTEL_SPT_H_LPC_BASE		0xa140
+#define PCI_DEVICE_ID_INTEL_SPT_H_LPC_BASE		0xa1ff
+#define PCI_DEVICE_ID_INTEL_SPT_H_LPC_BASE		0x001e
 #define PCI_DEVICE_ID_INTEL_SPT_H_H110			0xa143
 #define PCI_DEVICE_ID_INTEL_SPT_H_H170			0xa144
 #define PCI_DEVICE_ID_INTEL_SPT_H_Z170			0xa145
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 55fedd3..1499a6f 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -140,7 +140,8 @@
 {
    uint16_t id, id_mask;

-	id = pci_read_config16(PCH_DEV_PCIE1, PCI_DEVICE_ID);
+	id = pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
+
    /*
     * We may read an ID other than func 0 after FSP-S.
     * Strip out 4 least significant bits.

[Michael Niewöhner (Code Review)]

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35894 )

Change subject: soc/intel/skylake: fix platform detection when PCIe port 1 is disabled
......................................................................

Abandoned

integrated into cb:35763