Change in coreboot[master]: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage

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Arthur Heymans (Code Review)

18 Aug 2019 18 Aug '19

5:16 a.m.

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34978 )

Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage ......................................................................

sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage

This is now done during the romstage.

Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 0 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/34978/1

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index bd3c993..0036bb1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -458,18 +458,6 @@ RCBA32_OR(LCTL, 0x3); }

-static void pch_decode_init(struct device *dev) -{ - config_t *config = dev->chip_info; - - printk(BIOS_DEBUG, "pch_decode_init\n"); - - pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); -} - static void pch_spi_init(const struct device *const dev) { const config_t *const config = dev->chip_info; @@ -681,7 +669,6 @@

static void pch_lpc_enable_resources(struct device *dev) { - pch_decode_init(dev); return pci_dev_enable_resources(dev); }

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Kyösti Mälkki (Code Review)

18 Aug 18 Aug

4:09 p.m.

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34978 )

Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage ......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34978/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/lpc.c:

https://review.coreboot.org/c/coreboot/+/34978/1/src/southbridge/intel/bd82x... PS1, Line 907: .enable_resources = pch_lpc_enable_resources, pci_dev_enable_resources

-- To view, visit https://review.coreboot.org/c/coreboot/+/34978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Gerrit-Change-Number: 34978 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Comment-Date: Sun, 18 Aug 2019 19:09:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Angel Pons (Code Review)

29 Aug 29 Aug

9:57 p.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34978 )

Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage ......................................................................

Patch Set 1: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/34978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Gerrit-Change-Number: 34978 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Comment-Date: Fri, 30 Aug 2019 00:57:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Arthur Heymans (Code Review)

6 Oct 6 Oct

7:13 p.m.

Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34978

to look at the new patch set (#2).

Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage ......................................................................

sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage

This is now done during the romstage.

Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 1 insertion(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/34978/2

-- To view, visit https://review.coreboot.org/c/coreboot/+/34978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Gerrit-Change-Number: 34978 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-MessageType: newpatchset

Arthur Heymans (Code Review)

7 Oct 7 Oct

5:58 a.m.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34978 )

Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage ......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34978/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/lpc.c:

https://review.coreboot.org/c/coreboot/+/34978/1/src/southbridge/intel/bd82x... PS1, Line 907: .enable_resources = pch_lpc_enable_resources,

...

pci_dev_enable_resources

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/34978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Gerrit-Change-Number: 34978 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Comment-Date: Mon, 07 Oct 2019 08:58:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-MessageType: comment

Patrick Rudolph (Code Review)

10:39 a.m.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34978 )

Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage ......................................................................

Patch Set 2: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/34978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Gerrit-Change-Number: 34978 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-Comment-Date: Mon, 07 Oct 2019 13:39:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Patrick Georgi (Code Review)

9 Oct 9 Oct

7:19 p.m.

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34978 )

Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage ......................................................................

sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage

This is now done during the romstage.

Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/34978 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 1 insertion(+), 19 deletions(-)

Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index f67d1e4..5f0dd8c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -460,18 +460,6 @@ RCBA32_OR(LCTL, 0x3); }

-static void pch_lpc_enable_resources(struct device *dev) -{ - pch_decode_init(dev); - return pci_dev_enable_resources(dev); -} - static void pch_lpc_enable(struct device *dev) { /* Enable PCH Display Port */ @@ -910,7 +892,7 @@ static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pch_lpc_enable_resources, + .enable_resources = pci_dev_enable_resources, .write_acpi_tables = acpi_write_hpet, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .acpi_fill_ssdt_generator = southbridge_fill_ssdt,

-- To view, visit https://review.coreboot.org/c/coreboot/+/34978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d Gerrit-Change-Number: 34978 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Kyösti Mälkki kyosti.malkki@gmail.com Gerrit-MessageType: merged

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Angel Pons (Code Review)
Arthur Heymans (Code Review)
Kyösti Mälkki (Code Review)
Patrick Georgi (Code Review)
Patrick Rudolph (Code Review)