coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src: Get rid of non-local header treated as local
by Elyes HAOUAS (Code Review) 03 Jul '18

03 Jul '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/27331 ) Change subject: src: Get rid of non-local header treated as local ...................................................................... src: Get rid of non-local header treated as local Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/car/post_cache_as_ram.c M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c M src/cpu/intel/haswell/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl M src/mainboard/asus/kcma-d8/dsdt.asl M src/mainboard/asus/kfsn4-dre/dsdt.asl M src/mainboard/asus/kgpe-d16/dsdt.asl M src/mainboard/asus/p2b-ls/dsdt.asl M src/mainboard/asus/p2b/dsdt.asl M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c 11 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27331/2 -- To view, visit https://review.coreboot.org/27331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Gerrit-Change-Number: 27331 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src: Get rid of non-local header treated as local
by Elyes HAOUAS (Code Review) 03 Jul '18

03 Jul '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27331 Change subject: src: Get rid of non-local header treated as local ...................................................................... src: Get rid of non-local header treated as local Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/car/post_cache_as_ram.c M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c M src/cpu/intel/haswell/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl M src/mainboard/asus/kcma-d8/dsdt.asl M src/mainboard/asus/kfsn4-dre/dsdt.asl M src/mainboard/asus/kgpe-d16/dsdt.asl M src/mainboard/asus/p2b-ls/dsdt.asl M src/mainboard/asus/p2b/dsdt.asl M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c 11 files changed, 26 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27331/1 diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 2fb46d2..32ea166 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -31,7 +31,7 @@ #include "cpu/amd/car/disable_cache_as_ram.c" // For set_sysinfo_in_ram() -#include "northbridge/amd/amdfam10/raminit.h" +#include <northbridge/amd/amdfam10/raminit.h> #if CONFIG_RAMTOP <= 0x100000 #error "You need to set CONFIG_RAMTOP greater than 1M" diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 562a267..4602de9 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -24,7 +24,7 @@ #include <cpu/x86/pae.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include <cpu/amd/model_10xxx_rev.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> @@ -97,6 +97,7 @@ enable_cache(); /* Set up other MTRRs */ + amd_setup_mtrrs(); } else { while (!fam15h_startup_flags[id.nodeid][id.coreid - 1]) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 0e91dae..a26b549 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -38,10 +38,10 @@ #include <ec/google/chromeec/ec.h> #endif #include "haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/me.h" +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/me.h> #include <security/tpm/tspi.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl index 54ead92..f8709a4 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl @@ -230,5 +230,5 @@ Z00A, 8 } - #include "northbridge/amd/amdfam10/amdfam10_util.asl" + #include <northbridge/amd/amdfam10/amdfam10_util.asl> } diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index 5754d7c..b6dd211 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -39,8 +39,8 @@ 0x00000001 /* OEM Revision */ ) { - #include "northbridge/amd/amdfam10/amdfam10_util.asl" - #include "southbridge/amd/sr5650/acpi/sr5650.asl" + #include <northbridge/amd/amdfam10/amdfam10_util.asl> + #include <southbridge/amd/sr5650/acpi/sr5650.asl> /* Some global data */ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ @@ -427,7 +427,7 @@ { Name (_ADR, 0x00110000) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/sata.asl" + #include <southbridge/amd/sb700/acpi/sata.asl> } /* 0:12.0 SP5100 USB 0 */ @@ -477,7 +477,7 @@ { Name (_ADR, 0x00140001) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/ide.asl" + #include <southbridge/amd/sb700/acpi/ide.asl> } /* 0:14.3 SP5100 LPC */ diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl index 575715c..f3d59ce 100644 --- a/src/mainboard/asus/kfsn4-dre/dsdt.asl +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -39,7 +39,7 @@ 0x00000001 /* OEM Revision */ ) { - #include "northbridge/amd/amdfam10/amdfam10_util.asl" + #include <northbridge/amd/amdfam10/amdfam10_util.asl> /* Some global data */ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ @@ -404,7 +404,7 @@ Return (Local3) } -#include "southbridge/nvidia/ck804/acpi/ck804.asl" +#include <southbridge/nvidia/ck804/acpi/ck804.asl> /* PCI Routing Table Access */ Method (_PRT, 0, NotSerialized) { diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index ab6547c..7b78b5d 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -39,8 +39,8 @@ 0x00000001 /* OEM Revision */ ) { - #include "northbridge/amd/amdfam10/amdfam10_util.asl" - #include "southbridge/amd/sr5650/acpi/sr5650.asl" + #include <northbridge/amd/amdfam10/amdfam10_util.asl> + #include <southbridge/amd/sr5650/acpi/sr5650.asl> /* Some global data */ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ @@ -427,7 +427,7 @@ { Name (_ADR, 0x00110000) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/sata.asl" + #include <southbridge/amd/sb700/acpi/sata.asl> } /* 0:12.0 SP5100 USB 0 */ @@ -477,7 +477,7 @@ { Name (_ADR, 0x00140001) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/ide.asl" + #include <southbridge/amd/sb700/acpi/ide.asl> } /* 0:14.3 SP5100 LPC */ diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 304a0f4..73d9508 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -116,7 +116,7 @@ Return (0x0B) } } - #include "southbridge/intel/i82371eb/acpi/intx.asl" + #include <southbridge/intel/i82371eb/acpi/intx.asl> PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) @@ -174,7 +174,7 @@ Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, }) - #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" + #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> /* Begin southbridge block */ Device (PX40) @@ -230,7 +230,7 @@ Return (BUF1) } } - #include "southbridge/intel/i82371eb/acpi/i82371eb.asl" + #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> } Device (PX43) { diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 8ddbf28..93f6afe 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -112,7 +112,7 @@ Return (0x0B) } } - #include "southbridge/intel/i82371eb/acpi/intx.asl" + #include <southbridge/intel/i82371eb/acpi/intx.asl> PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) @@ -160,7 +160,7 @@ Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, }) - #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" + #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> /* Begin southbridge block */ Device (PX40) @@ -216,7 +216,7 @@ Return (BUF1) } } - #include "southbridge/intel/i82371eb/acpi/i82371eb.asl" + #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> } Device (PX43) { diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 74df691..2f598d8 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <program_loading.h> -#include "northbridge/intel/fsp_rangeley/northbridge.h" +#include <northbridge/intel/fsp_rangeley/northbridge.h> #include "southbridge/intel/fsp_rangeley/soc.h" #include "southbridge/intel/fsp_rangeley/gpio.h" #include "southbridge/intel/fsp_rangeley/romstage.h" diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index cb4bc7e..4c45613 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -27,7 +27,7 @@ #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #else -#include "southbridge/intel/common/gpio.h" +#include <southbridge/intel/common/gpio.h> #endif const struct rcba_config_instruction pch_early_config[] = { -- To view, visit https://review.coreboot.org/27331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Gerrit-Change-Number: 27331 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: intel/i945: add timestamps in romstage
by Elyes HAOUAS (Code Review) 03 Jul '18

03 Jul '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/27330 ) Change subject: intel/i945: add timestamps in romstage ...................................................................... Patch Set 1: this to remove "timestamp_add_now" from mb/*/*/romstage.c ? -- To view, visit https://review.coreboot.org/27330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic95313a19646b66dc1633fb680e54bfc61ec90be Gerrit-Change-Number: 27330 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 03 Jul 2018 12:32:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: intel/i945: add timestamps in romstage
by Patrick Georgi (Code Review) 03 Jul '18

03 Jul '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/27330 Change subject: intel/i945: add timestamps in romstage ...................................................................... intel/i945: add timestamps in romstage It is able to do so if timestamps are initialized. Change-Id: Ic95313a19646b66dc1633fb680e54bfc61ec90be Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27330/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index d7a349ff..05d6609 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -29,6 +29,7 @@ #include "chip.h" #include <cbmem.h> #include <device/dram/ddr2.h> +#include <timestamp.h> /* Debugging macros. */ #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) @@ -2728,6 +2729,7 @@ struct sys_info sysinfo; u8 reg8; + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); memset(&sysinfo, 0, sizeof(sysinfo)); @@ -2829,4 +2831,5 @@ printk(BIOS_DEBUG, "RAM initialization finished.\n"); sdram_setup_processor_side(); + timestamp_add_now(TS_AFTER_INITRAM); } -- To view, visit https://review.coreboot.org/27330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic95313a19646b66dc1633fb680e54bfc61ec90be Gerrit-Change-Number: 27330 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: timestamps: denote "end of romstage" right before loading ramstage
by Patrick Georgi (Code Review) 03 Jul '18

03 Jul '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/27329 Change subject: timestamps: denote "end of romstage" right before loading ramstage ...................................................................... timestamps: denote "end of romstage" right before loading ramstage Change-Id: I3524a757f5274815d62a17c58a18ed6b9aa726bf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- M src/arch/x86/cbfs_and_run.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/27329/1 diff --git a/src/arch/x86/cbfs_and_run.c b/src/arch/x86/cbfs_and_run.c index f25052b..d403009 100644 --- a/src/arch/x86/cbfs_and_run.c +++ b/src/arch/x86/cbfs_and_run.c @@ -15,8 +15,10 @@ #include <arch/stages.h> #include <program_loading.h> +#include <timestamp.h> asmlinkage void copy_and_run(void) { + timestamp_add_now(TS_END_ROMSTAGE); run_ramstage(); } -- To view, visit https://review.coreboot.org/27329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3524a757f5274815d62a17c58a18ed6b9aa726bf Gerrit-Change-Number: 27329 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: chromeec: PS2K node can't be under SIO node
by Patrick Georgi (Code Review) 03 Jul '18

03 Jul '18

Hello Stefan Reinauer, I'd like you to do a code review. Please visit https://review.coreboot.org/27328 to review the following change. Change subject: chromeec: PS2K node can't be under SIO node ...................................................................... chromeec: PS2K node can't be under SIO node Some operating systems won't find the keyboard if it is under the SIO node. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> BRANCH=none BUG=none TEST=Boot Windows, observe that keyboard is working Change-Id: I76b1ca9bf9243ffa861bed9c356a45377e7f43ef Reviewed-on: https://chromium-review.googlesource.com/895364 Commit-Ready: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 28 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27328/1 diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 7cd6523..051eff3 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -131,21 +131,34 @@ }) } #endif +} #ifdef SIO_EC_ENABLE_PS2K - Device (PS2K) // Keyboard +Device (PS2K) // Keyboard +{ + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() { - Name (_UID, 0) - Name (_ADR, 0) - Name (_HID, EISAID("PNP0303")) - Name (_CID, EISAID("PNP030B")) + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) +#ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ +#else + IRQ (Edge, ActiveHigh, Exclusive) {1} +#endif + }) - Method (_STA, 0, NotSerialized) { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate() - { + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { IO (Decode16, 0x60, 0x60, 0x01, 0x01) IO (Decode16, 0x64, 0x64, 0x01, 0x01) #ifdef SIO_EC_PS2K_IRQ @@ -153,21 +166,8 @@ #else IRQ (Edge, ActiveHigh, Exclusive) {1} #endif - }) - - Name (_PRS, ResourceTemplate() - { - StartDependentFn (0, 0) { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) -#ifdef SIO_EC_PS2K_IRQ - SIO_EC_PS2K_IRQ -#else - IRQ (Edge, ActiveHigh, Exclusive) {1} -#endif - } - EndDependentFn () - }) - } -#endif + } + EndDependentFn () + }) } +#endif -- To view, visit https://review.coreboot.org/27328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I76b1ca9bf9243ffa861bed9c356a45377e7f43ef Gerrit-Change-Number: 27328 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <reinauer(a)chromium.org>

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Change in coreboot[master]: soc/amd/stoneyridge: correct GPIO emission error in ACPI
by build bot (Jenkins) (Code Review) 03 Jul '18

03 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27306 ) Change subject: soc/amd/stoneyridge: correct GPIO emission error in ACPI ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75675/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/29727/ : SUCCESS -- To view, visit https://review.coreboot.org/27306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Gerrit-Change-Number: 27306 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Jul 2018 12:00:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/grunt: Update Raydium TS device ACPI nodes
by Kevin Chiu (Code Review) 03 Jul '18

03 Jul '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/27327 Change subject: google/grunt: Update Raydium TS device ACPI nodes ...................................................................... google/grunt: Update Raydium TS device ACPI nodes change I2C irq to EDGE trigger BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: Iff3acf4199d23b29dff209ec1c03a731679c6cbe Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/careena/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/27327/1 diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 3863100..2b6041f 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -140,7 +140,7 @@ register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" -- To view, visit https://review.coreboot.org/27327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iff3acf4199d23b29dff209ec1c03a731679c6cbe Gerrit-Change-Number: 27327 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: google/grunt: Update Raydium TS device ACPI nodes
by build bot (Jenkins) (Code Review) 03 Jul '18

03 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27306 ) Change subject: google/grunt: Update Raydium TS device ACPI nodes ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75674/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/29726/ : SUCCESS -- To view, visit https://review.coreboot.org/27306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Gerrit-Change-Number: 27306 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Jul 2018 11:22:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: payloads/seabios: Update stable from 1.11.1 to 1.11.2
by build bot (Jenkins) (Code Review) 03 Jul '18

03 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27326 ) Change subject: payloads/seabios: Update stable from 1.11.1 to 1.11.2 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75673/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/29725/ : SUCCESS -- To view, visit https://review.coreboot.org/27326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0 Gerrit-Change-Number: 27326 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Jul 2018 06:03:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit July 2018