coreboot-gerrit July 2018

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Change in coreboot[master]: smmstore: Add a key/val store facility in flash, mediated through SMM
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

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Change in coreboot[master]: riscv: use __riscv_atomic to check support A extended.
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27300 ) Change subject: riscv: use __riscv_atomic to check support A extended. ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75646/ : SUCCESS -- To view, visit https://review.coreboot.org/27300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475 Gerrit-Change-Number: 27300 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 08:19:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: use __riscv_atomic to check support A extended.
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27300 ) Change subject: riscv: use __riscv_atomic to check support A extended. ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/29700/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/75645/ : ABORTED -- To view, visit https://review.coreboot.org/27300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475 Gerrit-Change-Number: 27300 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 08:19:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: use __riscv_atomic to check support A extended.
by Anonymous Coward (Code Review) 02 Jul '18

02 Jul '18

Anonymous Coward #1001664 has uploaded a new patch set (#2). ( https://review.coreboot.org/27300 ) Change subject: riscv: use __riscv_atomic to check support A extended. ...................................................................... riscv: use __riscv_atomic to check support A extended. GCC pre-defined some macros for detecting ISA extensions. We should use these macros to detect ISA features. Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475 Signed-off-by: XiangWang <wxjstz(a)126.com> --- M src/arch/riscv/include/atomic.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/27300/2 -- To view, visit https://review.coreboot.org/27300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475 Gerrit-Change-Number: 27300 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward #1001664

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Change in coreboot[master]: use __riscv_atomic to check support A extended.
by Anonymous Coward (Code Review) 02 Jul '18

02 Jul '18

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/27300 Change subject: use __riscv_atomic to check support A extended. ...................................................................... use __riscv_atomic to check support A extended. GCC pre-defined some macros for detecting ISA extensions. We should use these macros to detect ISA features. Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475 Signed-off-by: XiangWang <wxjstz(a)126.com> --- M src/arch/riscv/include/atomic.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/27300/1 diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h index bc739fb..15702e4 100644 --- a/src/arch/riscv/include/atomic.h +++ b/src/arch/riscv/include/atomic.h @@ -39,7 +39,7 @@ #define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val) #define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr)) -#ifdef PK_ENABLE_ATOMICS +#ifdef __riscv_atomic # define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc) # define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp) # define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp) -- To view, visit https://review.coreboot.org/27300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475 Gerrit-Change-Number: 27300 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664

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Change in coreboot[master]: arch/x86: add SMM caller
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25193 ) Change subject: arch/x86: add SMM caller ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29698/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75643/ : SUCCESS -- To view, visit https://review.coreboot.org/25193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a9cc626dae9a7751034615ef409eebc6035f5c3 Gerrit-Change-Number: 25193 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 08:04:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: smmstore: Add a key/val store facility in flash, mediated through SMM
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25182 ) Change subject: smmstore: Add a key/val store facility in flash, mediated through SMM ...................................................................... Patch Set 10: (5 comments) https://review.coreboot.org/#/c/25182/10/src/drivers/smmstore/store.c File src/drivers/smmstore/store.c: https://review.coreboot.org/#/c/25182/10/src/drivers/smmstore/store.c@185 PS10, Line 185: if (rdev_writeat(&store, &key_sz, end, 4) != 4) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/10/src/drivers/smmstore/store.c@189 PS10, Line 189: if (rdev_writeat(&store, &value_sz, end, 4) != 4) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/10/src/drivers/smmstore/store.c@193 PS10, Line 193: if (rdev_writeat(&store, key, end, key_sz) != key_sz) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/10/src/drivers/smmstore/store.c@197 PS10, Line 197: if (rdev_writeat(&store, value, end, value_sz) != value_sz) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25182/10/src/drivers/smmstore/store.c@202 PS10, Line 202: if (rdev_writeat(&store, &nul, end, 1) != 1) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/25182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5 Gerrit-Change-Number: 25182 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 08:03:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: stoneyridge: Enable legacy IO
by Patrick Georgi (Code Review) 02 Jul '18

02 Jul '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27268 ) Change subject: stoneyridge: Enable legacy IO ...................................................................... stoneyridge: Enable legacy IO Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to function correctly. BUG=b:110817463 TEST=ran firmware_CorruptFwSigB on grunt Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://review.coreboot.org/27268 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9f8a7d2..3127f5c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -34,6 +34,7 @@ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PM_DECODE_EN 0x00 #define CF9_IO_EN BIT(1) +#define LEGACY_IO_EN BIT(0) #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 591a8f7..18e6c6c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -375,6 +375,13 @@ pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); } +static void sb_enable_legacy_io(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + + pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); +} + void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -550,6 +557,7 @@ sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_acpi_mmio_decode(); sb_enable_cf9_io(); + sb_enable_legacy_io(); enable_aoac_devices(); } -- To view, visit https://review.coreboot.org/27268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Gerrit-Change-Number: 27268 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: stoneyridge: Enable IO CF9 in bootblock
by Patrick Georgi (Code Review) 02 Jul '18

02 Jul '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27267 ) Change subject: stoneyridge: Enable IO CF9 in bootblock ...................................................................... stoneyridge: Enable IO CF9 in bootblock If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or verstage. BUG=b:110817463 TEST=built on grunt and made sure that hard_reset() reboots. Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://review.coreboot.org/27267 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 06ef898..9f8a7d2 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -32,6 +32,8 @@ #define PSP_MAILBOX_BAR_EN 0x10 /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PM_DECODE_EN 0x00 +#define CF9_IO_EN BIT(1) #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index c46bcb4..591a8f7 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -368,6 +368,13 @@ outb(byte, PM_DATA); } +static void sb_enable_cf9_io(void) +{ + uint32_t reg = pm_read32(PM_DECODE_EN); + + pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); +} + void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -542,6 +549,7 @@ sb_spibase(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ sb_acpi_mmio_decode(); + sb_enable_cf9_io(); enable_aoac_devices(); } -- To view, visit https://review.coreboot.org/27267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Gerrit-Change-Number: 27267 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nocturne: Do not set 4 LSB of SX9310 CRTL0
by Patrick Georgi (Code Review) 02 Jul '18

02 Jul '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27265 ) Change subject: nocturne: Do not set 4 LSB of SX9310 CRTL0 ...................................................................... nocturne: Do not set 4 LSB of SX9310 CRTL0 These bits start the acquisition process. They should only be set by the driver. BUG=b:74363445 TEST=compile Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Reviewed-on: https://review.coreboot.org/27265 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 09b7ef9..17bd3c0 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -305,7 +305,7 @@ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" register "speed" = "I2C_SPEED_FAST_PLUS" register "uid" = "0" - register "reg_prox_ctrl0" = "0x1a" + register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" register "reg_prox_ctrl2" = "0x84" register "reg_prox_ctrl3" = "0x0e" @@ -346,7 +346,7 @@ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)" register "speed" = "I2C_SPEED_FAST_PLUS" register "uid" = "1" - register "reg_prox_ctrl0" = "0x1a" + register "reg_prox_ctrl0" = "0x10" register "reg_prox_ctrl1" = "0x00" register "reg_prox_ctrl2" = "0x84" register "reg_prox_ctrl3" = "0x0e" -- To view, visit https://review.coreboot.org/27265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Gerrit-Change-Number: 27265 Gerrit-PatchSet: 4 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit July 2018