coreboot-gerrit July 2018

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Change in coreboot[master]: mb/pcengines/apu1: use generic SPD
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27301 ) Change subject: mb/pcengines/apu1: use generic SPD ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29702/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75648/ : SUCCESS -- To view, visit https://review.coreboot.org/27301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e48817c03b4372887bc0ea14209736ae2b4e48f Gerrit-Change-Number: 27301 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 09:36:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/kukui: Update MMU table in romstage
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27304 ) Change subject: google/kukui: Update MMU table in romstage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29704/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75650/ : SUCCESS -- To view, visit https://review.coreboot.org/27304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c Gerrit-Change-Number: 27304 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 09:36:55 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: payloads/iPXE: add iPXE serial enable option
by Patrick Georgi (Code Review) 02 Jul '18

02 Jul '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/27302 ) Change subject: payloads/iPXE: add iPXE serial enable option ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia3c74cfbee4f816782161fcff286a14f46be78c5 Gerrit-Change-Number: 27302 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 09:30:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: payloads/iPXE: add iPXE serial enable option
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27302 ) Change subject: payloads/iPXE: add iPXE serial enable option ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29703/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75649/ : SUCCESS -- To view, visit https://review.coreboot.org/27302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia3c74cfbee4f816782161fcff286a14f46be78c5 Gerrit-Change-Number: 27302 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 09:26:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek: Share PLL code among similar SOCs
by Tristan Hsieh (Code Review) 02 Jul '18

02 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27305 Change subject: mediatek: Share PLL code among similar SOCs ...................................................................... mediatek: Share PLL code among similar SOCs Refactor PLL code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- A src/soc/mediatek/common/include/soc/pll.h A src/soc/mediatek/common/pll.c M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/dramc_pi_basic_api.c R src/soc/mediatek/mt8173/include/soc/mt_pll.h M src/soc/mediatek/mt8173/pll.c 6 files changed, 260 insertions(+), 183 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/27305/1 diff --git a/src/soc/mediatek/common/include/soc/pll.h b/src/soc/mediatek/common/include/soc/pll.h new file mode 100644 index 0000000..d49c3bf --- /dev/null +++ b/src/soc/mediatek/common/include/soc/pll.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_COMMON_PLL_H +#define SOC_MEDIATEK_COMMON_PLL_H + +#include <soc/addressmap.h> +#include <soc/mt_pll.h> +#include <types.h> + +#define MTK_TOPCKGEN ((struct mtk_topckgen_regs *)CKSYS_BASE) +#define MTK_APMIXED ((struct mtk_apmixed_regs *)APMIXED_BASE) + +#define PLL_PWR_ON (1 << 0) +#define PLL_EN (1 << 0) +#define PLL_ISO (1 << 1) +#define PLL_RSTB_SHIFT (24) +#define NO_RSTB_SHIFT (255) +#define PLL_PCW_CHG (1 << 31) +#define PLL_POSTDIV_MASK 0x7 + +struct mux { + void *reg; + void *upd_reg; + u8 mux_shift; + u8 mux_width; + u8 upd_shift; +}; + +struct pll { + void *reg; + void *pwr_reg; + void *div_reg; + void *pcw_reg; + const u32 *div_rate; + u8 rstb_shift; + u8 pcwbits; + u8 div_shift; + u8 pcw_shift; +}; + +#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \ + _pcw_reg, _pcw_shift, _div_rate) \ + [_id] = { \ + .reg = &MTK_APMIXED->_reg, \ + .pwr_reg = &MTK_APMIXED->_pwr_reg, \ + .rstb_shift = _rstb, \ + .pcwbits = _pcwbits, \ + .div_reg = &MTK_APMIXED->_div_reg, \ + .div_shift = _div_shift, \ + .pcw_reg = &MTK_APMIXED->_pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_rate = _div_rate, \ + } + +void pll_set_pcw_change(const struct pll *pll); +void mux_set_sel(const struct mux *mux, u32 sel); +int pll_set_rate(const struct pll *pll, u32 rate); +void mt_pll_init(void); + +#endif /* SOC_MEDIATEK_COMMON_PLL_H */ diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c new file mode 100644 index 0000000..feaf0ea --- /dev/null +++ b/src/soc/mediatek/common/pll.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <assert.h> +#include <soc/pll.h> + +#define GENMASK(h, l) (BIT(h + 1) - BIT(l)) + +void mux_set_sel(const struct mux *mux, u32 sel) +{ + u32 mask = GENMASK(mux->mux_width - 1, 0); + u32 val = read32(mux->reg); + + val &= ~(mask << mux->mux_shift); + val |= (sel & mask) << mux->mux_shift; + write32(mux->reg, val); + if (mux->upd_reg) + write32(mux->upd_reg, 1 << mux->upd_shift); +} + +static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv, + u32 freq) +{ + const u32 fin_hz = CLK26M_HZ; + const u32 *div_rate = pll->div_rate; + u32 val; + + assert(freq <= div_rate[0]); + assert(freq >= 1 * GHz / 16); + + for (val = 1; div_rate[val] != 0; val++) { + if (freq > div_rate[val]) + break; + } + val--; + *postdiv = val; + + /* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */ + val += pll->pcwbits - PCW_INTEGER_BITS; + + *pcw = ((u64)freq << val) / fin_hz; +} + +static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv) +{ + u32 val; + + /* set postdiv */ + val = read32(pll->div_reg); + val &= ~(PLL_POSTDIV_MASK << pll->div_shift); + val |= postdiv << pll->div_shift; + + /* postdiv and pcw need to set at the same time if on same register */ + if (pll->div_reg != pll->pcw_reg) { + write32(pll->div_reg, val); + val = read32(pll->pcw_reg); + } + + /* set pcw */ + val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); + val |= pcw << pll->pcw_shift; + write32(pll->pcw_reg, val); + + /* set pcw change */ + pll_set_pcw_change(pll); +} + +int pll_set_rate(const struct pll *pll, u32 rate) +{ + u32 pcw, postdiv; + + pll_calc_values(pll, &pcw, &postdiv, rate); + pll_set_rate_regs(pll, pcw, postdiv); + + return 0; +} diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 56c966a..78e1a72 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -18,7 +18,7 @@ bootblock-y += bootblock.c bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c bootblock-y += i2c.c -bootblock-y += pll.c +bootblock-y += ../common/pll.c pll.c bootblock-y += spi.c bootblock-y += ../common/timer.c bootblock-y += timer.c @@ -47,7 +47,7 @@ ################################################################################ romstage-$(CONFIG_SPI_FLASH) += flash_controller.c -romstage-y += pll.c +romstage-y += ../common/pll.c pll.c romstage-y += ../common/timer.c romstage-y += timer.c @@ -75,7 +75,7 @@ ramstage-y += da9212.c ramstage-y += gpio.c ramstage-y += ../common/wdt.c -ramstage-y += pll.c +ramstage-y += ../common/pll.c pll.c ramstage-y += rtc.c ramstage-y += usb.c diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index cb6cc2c..21c8308 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -738,7 +738,7 @@ u32 msk; msk = BIT(7) | BIT(11) | BIT(15); - clrbits_le32(&mt8173_apmixed->ap_pll_con3, msk); + clrbits_le32(&MTK_APMIXED->ap_pll_con3, msk); msk = BIT(0) | BIT(4) | BIT(8); clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk); @@ -756,7 +756,7 @@ u32 val; val = BIT(7) | BIT(11) | BIT(15); - setbits_le32(&mt8173_apmixed->ap_pll_con3, val); + setbits_le32(&MTK_APMIXED->ap_pll_con3, val); val = BIT(0) | BIT(4) | BIT(8); setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val); diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/mt_pll.h similarity index 90% rename from src/soc/mediatek/mt8173/include/soc/pll.h rename to src/soc/mediatek/mt8173/include/soc/mt_pll.h index 9b3cca3..25dbe82 100644 --- a/src/soc/mediatek/mt8173/include/soc/pll.h +++ b/src/soc/mediatek/mt8173/include/soc/mt_pll.h @@ -17,9 +17,8 @@ #define SOC_MEDIATEK_MT8173_PLL_H #include <soc/emi.h> -#include <soc/addressmap.h> -struct mt8173_topckgen_regs { +struct mtk_topckgen_regs { u32 clk_mode; u32 dcm_cfg; u32 reserved1[6]; @@ -97,12 +96,12 @@ u32 mbist_cfg_3; /* 0x314 */ }; -check_member(mt8173_topckgen_regs, clk_cfg_0, 0x40); -check_member(mt8173_topckgen_regs, clk_cfg_8, 0x100); -check_member(mt8173_topckgen_regs, clk_scp_cfg_0, 0x200); -check_member(mt8173_topckgen_regs, mbist_cfg_3, 0x314); +check_member(mtk_topckgen_regs, clk_cfg_0, 0x40); +check_member(mtk_topckgen_regs, clk_cfg_8, 0x100); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x200); +check_member(mtk_topckgen_regs, mbist_cfg_3, 0x314); -struct mt8173_apmixed_regs { +struct mtk_apmixed_regs { u32 ap_pll_con0; u32 reserved1[1]; u32 ap_pll_con2; /* 0x008 */ @@ -187,12 +186,19 @@ u32 msdcpll2_pwr_con0; /* 0x2fc */ }; -check_member(mt8173_apmixed_regs, ap_pll_con2, 0x8); -check_member(mt8173_apmixed_regs, armca15pll_con0, 0x200); -check_member(mt8173_apmixed_regs, msdcpll2_pwr_con0, 0x2fc); +check_member(mtk_apmixed_regs, ap_pll_con2, 0x8); +check_member(mtk_apmixed_regs, armca15pll_con0, 0x200); +check_member(mtk_apmixed_regs, msdcpll2_pwr_con0, 0x2fc); -static struct mt8173_topckgen_regs *const mt8173_topckgen = (void *)CKSYS_BASE; -static struct mt8173_apmixed_regs *const mt8173_apmixed = (void *)APMIXED_BASE; +enum { + PLL_PWR_ON_DELAY = 5, + PLL_ISO_DELAY = 0, + PLL_EN_DELAY = 40, +}; + +enum { + PCW_INTEGER_BITS = 7, +}; /* PLL rate */ enum { @@ -283,7 +289,6 @@ }; void mt_pll_post_init(void); -void mt_pll_init(void); void mt_pll_set_aud_div(u32 rate); void mt_pll_enable_ssusb_clk(void); void mt_pll_raise_ca53_freq(u32 freq); diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index d95f769..da00648 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -15,7 +15,6 @@ #include <arch/io.h> #include <assert.h> -#include <console/console.h> #include <delay.h> #include <stddef.h> @@ -23,8 +22,6 @@ #include <soc/infracfg.h> #include <soc/pll.h> -#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l)) - enum mux_id { TOP_AXI_SEL, TOP_MEM_SEL, @@ -68,20 +65,13 @@ TOP_NR_MUX }; -#define TOPCKGEN_REG(x) (CKSYS_BASE + offsetof(struct mt8173_topckgen_regs, x)) -#define APMIXED_REG(x) (APMIXED_BASE + offsetof(struct mt8173_apmixed_regs, x)) - -struct mux { - void *reg; - u8 mux_shift; - u8 mux_width; -}; - #define MUX(_id, _reg, _mux_shift, _mux_width) \ [_id] = { \ - .reg = (void *)TOPCKGEN_REG(_reg), \ + .reg = &MTK_TOPCKGEN->_reg, \ .mux_shift = _mux_shift, \ .mux_width = _mux_width, \ + .upd_reg = NULL, \ + .upd_shift = 0, \ } static const struct mux muxes[] = { @@ -136,24 +126,6 @@ MUX(TOP_RTC_SEL, clk_cfg_13, 24, 2), }; -static void mux_set_sel(const struct mux *mux, u32 sel) -{ - u32 mask = GENMASK(mux->mux_width - 1, 0); - u32 val = read32(mux->reg); - - val &= ~(mask << mux->mux_shift); - val |= (sel & mask) << mux->mux_shift; - write32(mux->reg, val); -} - -#define PLL_PWR_ON (1 << 0) -#define PLL_EN (1 << 0) -#define PLL_ISO (1 << 1) -#define PLL_RSTB (1 << 24) -#define PLL_PCW_CHG (1 << 31) -#define PLL_POSTDIV_MASK 0x7 -#define PCW_INTEGER_BITS 7 - enum pll_id { APMIXED_ARMCA15PLL, APMIXED_ARMCA7PLL, @@ -199,117 +171,54 @@ 0, }; -struct pll { - void *reg; - void *pwr_reg; - u32 rstb; - u8 pcwbits; - void *div_reg; - u8 div_shift; - void *pcw_reg; - u8 pcw_shift; - const u32 *div_rate; -}; - -#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \ - _pcw_reg, _pcw_shift, _div_rate) \ - [_id] = { \ - .reg = (void *)APMIXED_REG(_reg), \ - .pwr_reg = (void *)APMIXED_REG(_pwr_reg), \ - .rstb = _rstb, \ - .pcwbits = _pcwbits, \ - .div_reg = (void *)APMIXED_REG(_div_reg), \ - .div_shift = _div_shift, \ - .pcw_reg = (void *)APMIXED_REG(_pcw_reg), \ - .pcw_shift = _pcw_shift, \ - .div_rate = _div_rate, \ - } - static const struct pll plls[] = { - PLL(APMIXED_ARMCA15PLL, armca15pll_con0, armca15pll_pwr_con0, 0, 21, - armca15pll_con1, 24, armca15pll_con1, 0, pll_div_rate), - PLL(APMIXED_ARMCA7PLL, armca7pll_con0, armca7pll_pwr_con0, PLL_RSTB, 21, - armca7pll_con1, 24, armca7pll_con1, 0, pll_div_rate), - PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0, PLL_RSTB, 21, - mainpll_con0, 4, mainpll_con1, 0, pll_div_rate), - PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0, PLL_RSTB, 7, - univpll_con0, 4, univpll_con1, 14, univpll_div_rate), - PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0, 0, 21, - mmpll_con1, 24, mmpll_con1, 0, mmpll_div_rate), - PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0, 0, 21, - msdcpll_con0, 4, msdcpll_con1, 0, pll_div_rate), - PLL(APMIXED_VENCPLL, vencpll_con0, vencpll_pwr_con0, 0, 21, - vencpll_con0, 4, vencpll_con1, 0, pll_div_rate), - PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0, 0, 21, - tvdpll_con0, 4, tvdpll_con1, 0, pll_div_rate), - PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0, 0, 21, - mpll_con0, 4, mpll_con1, 0, pll_div_rate), - PLL(APMIXED_VCODECPLL, vcodecpll_con0, vcodecpll_pwr_con0, 0, 21, - vcodecpll_con0, 4, vcodecpll_con1, 0, pll_div_rate), - PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0, 0, 31, - apll1_con0, 4, apll1_con1, 0, pll_div_rate), - PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0, 0, 31, - apll2_con0, 4, apll2_con1, 0, pll_div_rate), - PLL(APMIXED_LVDSPLL, lvdspll_con0, lvdspll_pwr_con0, 0, 21, - lvdspll_con0, 4, lvdspll_con1, 0, pll_div_rate), - PLL(APMIXED_MSDCPLL2, msdcpll2_con0, msdcpll2_pwr_con0, 0, 21, - msdcpll2_con0, 4, msdcpll2_con1, 0, pll_div_rate), + PLL(APMIXED_ARMCA15PLL, armca15pll_con0, armca15pll_pwr_con0, + NO_RSTB_SHIFT, 21, armca15pll_con1, 24, armca15pll_con1, 0, + pll_div_rate), + PLL(APMIXED_ARMCA7PLL, armca7pll_con0, armca7pll_pwr_con0, + PLL_RSTB_SHIFT, 21, armca7pll_con1, 24, armca7pll_con1, 0, + pll_div_rate), + PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0, + PLL_RSTB_SHIFT, 21, mainpll_con0, 4, mainpll_con1, 0, + pll_div_rate), + PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0, + PLL_RSTB_SHIFT, 7, univpll_con0, 4, univpll_con1, 14, + univpll_div_rate), + PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0, + NO_RSTB_SHIFT, 21, mmpll_con1, 24, mmpll_con1, 0, + mmpll_div_rate), + PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0, + NO_RSTB_SHIFT, 21, msdcpll_con0, 4, msdcpll_con1, 0, + pll_div_rate), + PLL(APMIXED_VENCPLL, vencpll_con0, vencpll_pwr_con0, + NO_RSTB_SHIFT, 21, vencpll_con0, 4, vencpll_con1, 0, + pll_div_rate), + PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0, + NO_RSTB_SHIFT, 21, tvdpll_con0, 4, tvdpll_con1, 0, + pll_div_rate), + PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0, + NO_RSTB_SHIFT, 21, mpll_con0, 4, mpll_con1, 0, + pll_div_rate), + PLL(APMIXED_VCODECPLL, vcodecpll_con0, vcodecpll_pwr_con0, + NO_RSTB_SHIFT, 21, vcodecpll_con0, 4, vcodecpll_con1, 0, + pll_div_rate), + PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0, + NO_RSTB_SHIFT, 31, apll1_con0, 4, apll1_con1, 0, + pll_div_rate), + PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0, + NO_RSTB_SHIFT, 31, apll2_con0, 4, apll2_con1, 0, + pll_div_rate), + PLL(APMIXED_LVDSPLL, lvdspll_con0, lvdspll_pwr_con0, + NO_RSTB_SHIFT, 21, lvdspll_con0, 4, lvdspll_con1, 0, + pll_div_rate), + PLL(APMIXED_MSDCPLL2, msdcpll2_con0, msdcpll2_pwr_con0, + NO_RSTB_SHIFT, 21, msdcpll2_con0, 4, msdcpll2_con1, 0, + pll_div_rate), }; -static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv) +void pll_set_pcw_change(const struct pll *pll) { - u32 val; - - /* set postdiv */ - val = read32(pll->div_reg); - val &= ~(PLL_POSTDIV_MASK << pll->div_shift); - val |= postdiv << pll->div_shift; - - /* postdiv and pcw need to set at the same time if on same register */ - if (pll->div_reg != pll->pcw_reg) { - write32(pll->div_reg, val); - val = read32(pll->pcw_reg); - } - - /* set pcw */ - val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); - val |= pcw << pll->pcw_shift; - val |= PLL_PCW_CHG; - write32(pll->pcw_reg, val); -} - -static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv, - u32 freq) -{ - const u32 fin_hz = CLK26M_HZ; - const u32 *div_rate = pll->div_rate; - u32 val; - - assert(freq <= div_rate[0]); - assert(freq >= 1 * GHz / 16); - - for (val = 1; div_rate[val] != 0; val++) { - if (freq > div_rate[val]) - break; - } - val--; - *postdiv = val; - - /* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */ - val += pll->pcwbits - PCW_INTEGER_BITS; - - *pcw = ((u64)freq << val) / fin_hz; -} - -static int pll_set_rate(const struct pll *pll, u32 rate) -{ - u32 pcw = 0; - u32 postdiv; - - pll_calc_values(pll, &pcw, &postdiv, rate); - pll_set_rate_regs(pll, pcw, postdiv); - - return 0; + setbits_le32(pll->pcw_reg, PLL_PCW_CHG); } void mt_pll_init(void) @@ -317,10 +226,10 @@ int i; /* reduce CLKSQ disable time */ - write32(&mt8173_apmixed->clksq_stb_con0, (0x05 << 8) | (0x01 << 0)); + write32(&MTK_APMIXED->clksq_stb_con0, (0x05 << 8) | (0x01 << 0)); /* extend PWR/ISO control timing to 1us */ - write32(&mt8173_apmixed->pll_iso_con0, (0x8 << 16) | (0x8 << 0)); - write32(&mt8173_apmixed->ap_pll_con6, 0x00000000); + write32(&MTK_APMIXED->pll_iso_con0, (0x8 << 16) | (0x8 << 0)); + write32(&MTK_APMIXED->ap_pll_con6, 0x00000000); /************* * xPLL PWR ON @@ -328,7 +237,8 @@ for (i = 0; i < APMIXED_NR_PLL; i++) setbits_le32(plls[i].pwr_reg, PLL_PWR_ON); - udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */ + /* wait for xPLL_PWR_ON ready (min delay is 1us) */ + udelay(PLL_PWR_ON_DELAY); /****************** * xPLL ISO Disable @@ -361,14 +271,14 @@ for (i = 0; i < APMIXED_NR_PLL; i++) setbits_le32(plls[i].reg, PLL_EN); - udelay(40); /* wait for PLL stable (min delay is 20us) */ + udelay(PLL_EN_DELAY); /* wait for PLL stable (min delay is 20us) */ /*************** * xPLL DIV RSTB ****************/ for (i = 0; i < APMIXED_NR_PLL; i++) { - if (plls[i].rstb) - setbits_le32(plls[i].reg, plls[i].rstb); + if (plls[i].rstb_shift != NO_RSTB_SHIFT) + setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift); } /************** @@ -378,8 +288,8 @@ /* enable infrasys DCM */ setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1); - write32(&mt8173_topckgen->clk_mode, 0x1); - write32(&mt8173_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */ + write32(&MTK_TOPCKGEN->clk_mode, 0x1); + write32(&MTK_TOPCKGEN->clk_mode, 0x0); /* enable TOPCKGEN */ /************ * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! @@ -436,10 +346,10 @@ mux_set_sel(&muxes[TOP_MSDC30_1_SEL], 2); /* 2: msdcpll_d4 */ /* enable scpsys clock off control */ - write32(&mt8173_topckgen->clk_scp_cfg_0, + write32(&MTK_TOPCKGEN->clk_scp_cfg_0, (1 << 10) | (1 << 9) | (1 << 5) | (1 << 4) | (1 << 2) | (1 << 1) | (1 << 0)); - write32(&mt8173_topckgen->clk_scp_cfg_1, + write32(&MTK_TOPCKGEN->clk_scp_cfg_1, (1 << 4) | (1 << 2) | (1 << 0)); } @@ -447,16 +357,16 @@ void mt_pll_enable_ssusb_clk(void) { /* set RG_LTECLKSQ_EN */ - setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1); + setbits_le32(&MTK_APMIXED->ap_pll_con0, 0x1); udelay(100); /* wait for PLL stable */ /* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */ - setbits_le32(&mt8173_apmixed->ap_pll_con0, 0x1 << 1); - setbits_le32(&mt8173_apmixed->ap_pll_con2, 0x1); + setbits_le32(&MTK_APMIXED->ap_pll_con0, 0x1 << 1); + setbits_le32(&MTK_APMIXED->ap_pll_con2, 0x1); udelay(100); /* wait for PLL stable */ /* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */ - setbits_le32(&mt8173_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); + setbits_le32(&MTK_APMIXED->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); } @@ -487,19 +397,19 @@ if (apll1) { /* mclk */ - clrbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5); - clrsetbits_le32(&mt8173_topckgen->clk_auddiv_1, 0xff << 8, + clrbits_le32(&MTK_TOPCKGEN->clk_auddiv_0, 1 << 5); + clrsetbits_le32(&MTK_TOPCKGEN->clk_auddiv_1, 0xff << 8, mclk_div << 8); /* bclk */ - clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 24, + clrsetbits_le32(&MTK_TOPCKGEN->clk_auddiv_0, 0xf << 24, 7 << 24); } else { /* mclk */ - setbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5); - clrsetbits_le32(&mt8173_topckgen->clk_auddiv_2, 0xff << 8, + setbits_le32(&MTK_TOPCKGEN->clk_auddiv_0, 1 << 5); + clrsetbits_le32(&MTK_TOPCKGEN->clk_auddiv_2, 0xff << 8, mclk_div << 8); /* bclk */ - clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 28, + clrsetbits_le32(&MTK_TOPCKGEN->clk_auddiv_0, 0xf << 28, 7 << 28); } } @@ -513,19 +423,19 @@ u32 mpll_sdm_pcw_20_0 = 0xF13B1; /* disable MPLL for adjusting memory clk frequency */ - clrbits_le32(&mt8173_apmixed->mpll_con0, BIT(0)); + clrbits_le32(&MTK_APMIXED->mpll_con0, BIT(0)); /* MPLL configuration: mode selection */ - setbits_le32(&mt8173_apmixed->mpll_con0, BIT(16)); - clrbits_le32(&mt8173_apmixed->mpll_con0, 0x7 << 4); - clrbits_le32(&mt8173_apmixed->pll_test_con0, 1 << 31); + setbits_le32(&MTK_APMIXED->mpll_con0, BIT(16)); + clrbits_le32(&MTK_APMIXED->mpll_con0, 0x7 << 4); + clrbits_le32(&MTK_APMIXED->pll_test_con0, 1 << 31); /* set RG_MPLL_SDM_PCW for feedback divide ratio */ - clrsetbits_le32(&mt8173_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0); + clrsetbits_le32(&MTK_APMIXED->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0); } void mt_mem_pll_config_post(void) { /* power up sequence starts: enable MPLL */ - setbits_le32(&mt8173_apmixed->mpll_con0, BIT(0)); + setbits_le32(&MTK_APMIXED->mpll_con0, BIT(0)); } void mt_mem_pll_mux(void) -- To view, visit https://review.coreboot.org/27305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c Gerrit-Change-Number: 27305 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: google/kukui: Update MMU table in romstage
by Tristan Hsieh (Code Review) 02 Jul '18

02 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27304 Change subject: google/kukui: Update MMU table in romstage ...................................................................... google/kukui: Update MMU table in romstage Update MMU table in romstage after dram calibration ready. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/27304/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index d63b7c8..a3dc143 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -16,6 +16,7 @@ #include <arch/exception.h> #include <console/console.h> #include <program_loading.h> +#include <soc/mmu_operations.h> #include <timestamp.h> void main(void) @@ -26,5 +27,7 @@ console_init(); exception_init(); + mt8183_mmu_after_dram(); + run_ramstage(); } -- To view, visit https://review.coreboot.org/27304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c Gerrit-Change-Number: 27304 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add MMU operation support
by Tristan Hsieh (Code Review) 02 Jul '18

02 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27303 Change subject: mediatek/mt8183: Add MMU operation support ...................................................................... mediatek/mt8183: Add MMU operation support Enable MMU in bootblock and provide mt8183_mmu_after_dram() for romstage after dram calibration ready. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/bootblock.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/mcucfg.h A src/soc/mediatek/mt8183/include/soc/mmu_operations.h A src/soc/mediatek/mt8183/mmu_operations.c 6 files changed, 489 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/27303/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 74b0ae8..8a9d07e 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y) bootblock-y += bootblock.c +bootblock-y += mmu_operations.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += ../common/timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) @@ -13,6 +14,8 @@ verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c verstage-y += ../common/wdt.c +romstage-y += emi.c +romstage-y += mmu_operations.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += ../common/timer.c romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c diff --git a/src/soc/mediatek/mt8183/bootblock.c b/src/soc/mediatek/mt8183/bootblock.c index 4eca0f1..f92999b 100644 --- a/src/soc/mediatek/mt8183/bootblock.c +++ b/src/soc/mediatek/mt8183/bootblock.c @@ -14,9 +14,11 @@ */ #include <bootblock_common.h> +#include <soc/mmu_operations.h> #include <soc/wdt.h> void bootblock_soc_init(void) { + mt8183_mmu_init(); mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index a0d7f1c..a5c6f21 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -17,6 +17,7 @@ #define __SOC_MEDIATEK_MT8183_INCLUDE_SOC_ADDRESSMAP_H__ enum { + MCUCFG_BASE = 0x0C530000, IO_PHYS = 0x10000000, DDR_BASE = 0x40000000 }; diff --git a/src/soc/mediatek/mt8183/include/soc/mcucfg.h b/src/soc/mediatek/mt8183/include/soc/mcucfg.h new file mode 100644 index 0000000..0a1232a --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/mcucfg.h @@ -0,0 +1,386 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_MCUCFG_H +#define SOC_MEDIATEK_MT8183_MCUCFG_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_mcucfg_regs { + u32 mp0_ca7l_cache_config; + u32 mp0_cpu0_mem_delsel0; + u32 mp0_cpu0_mem_delsel1; + u32 reserved1[6]; + u32 mp0_cache_mem_delsel0; + u32 mp0_cache_mem_delsel1; + u32 mp0_axi_config; + u32 mp0_misc_config0; + u32 reserved2[1]; + u32 mp0_misc_config2; + u32 mp0_misc_config3; + u32 mp0_misc_config4; + u32 mp0_misc_config5; + u32 mp0_misc_config6; + u32 mp0_misc_config7; + u32 mp0_misc_config8; + u32 mp0_misc_config9; + u32 mp0_ca7l_cfg_dis; + u32 mp0_ca7l_clken_ctrl; + u32 mp0_ca7l_rst_ctrl; + u32 mp0_ca7l_misc_config; + u32 mp0_ca7l_dbg_pwr_ctrl; + u32 mp0_rw_rsvd0; + u32 mp0_rw_rsvd1; + u32 mp0_ro_rsvd; + u32 reserved3[1]; + u32 mp0_l2_cache_parity1_rdata; + u32 mp0_l2_cache_parity2_rdata; + u32 reserved4[1]; + u32 mp0_rgu_dcm_config; + u32 mp0_ca53_specific_ctrl; + u32 mp0_esr_case; + u32 mp0_esr_mask; + u32 mp0_esr_trig_en; + u32 reserved5[1]; + u32 mp0_ses_cg_en; + u32 reserved6[216]; + u32 mp_dbg_ctrl; + u32 reserved7[1]; + u32 mp0_ca7l_ir_mon; + u32 reserved8[32]; + u32 mp_dfd_ctrl; + u32 dfd_cnt_l; + u32 dfd_cnt_h; + u32 misccfg_ro_rsvd; + u32 reserved9[1]; + u32 dvm_dbg_monitor_gpu; + u32 dvm_dbg_monitor_psys; + u32 dvm_dbg_monitor_mp1; + u32 dvm_dbg_monitor_mp0; + u32 dvm_dbg_monitor_mp2; + u32 reserved10[2]; + u32 dvm_op_arid_mp0; + u32 dvm_op_arid_mp1; + u32 dvm_op_arid_mp2; + u32 reserved11[5]; + u32 cci_s6_if_debug; + u32 reserved12[7]; + u32 mp1_rst_status; + u32 mp1_dbg_ctrl; + u32 mp1_dbg_flag; + u32 mp1_ca7l_ir_mon; + u32 reserved13[32]; + u32 mcusys_dbg_mon_sel_a; + u32 mcusys_dbg_mon; + u32 misccfg_sec_vio_status0; + u32 misccfg_sec_vio_status1; + u32 cci_top_if_debug; + u32 cci_m0_if_debug; + u32 cci_m1_if_debug; + u32 cci_m2_if_debug; + u32 cci_s1_if_debug; + u32 cci_s2_if_debug; + u32 cci_s3_if_debug; + u32 cci_s4_if_debug; + u32 cci_m0_tra_debug; + u32 cci_m1_tra_debug; + u32 cci_m2_tra_debug; + u32 cci_s1_tra_debug; + u32 cci_s2_tra_debug; + u32 cci_s3_tra_debug; + u32 cci_s4_tra_debug; + u32 cci_tra_dbg_cfg; + u32 cci_s5_if_debug; + u32 cci_s5_tra_debug; + u32 gic500_int_mask; + u32 core_rst_en_latch; + u32 reserved14[3]; + u32 dbg_core_ret; + u32 mcusys_config_a; + u32 mcusys_config1_a; + u32 mcusys_gic_peribase_a; + u32 mcusys_pinmux; + u32 sec_range0_start; + u32 sec_range0_end; + u32 sec_range_enable; + u32 l2c_mm_base; + u32 reserved15[8]; + u32 aclken_div; + u32 pclken_div; + u32 l2c_sram_ctrl; + u32 armpll_jit_ctrl; + u32 cci_addrmap; + u32 cci_config; + u32 cci_periphbase; + u32 cci_nevntcntovfl; + u32 cci_status; + u32 cci_acel_s1_ctrl; + u32 mcusys_bus_fabric_dcm_ctrl; + u32 mcu_misc_dcm_ctrl; + u32 xgpt_ctl; + u32 xgpt_idx; + u32 reserved16[3]; + u32 mcusys_rw_rsvd0; + u32 mcusys_rw_rsvd1; + u32 reserved17[13]; + u32 gic500_delsel_ctl; + u32 etb_delsel_ctl; + u32 etb_rst_ctl; + u32 reserved18[13]; + u32 mp_gen_timer_reset_mask_secur_en; + u32 mp_gen_timer_reset_mask_0; + u32 mp_gen_timer_reset_mask_1; + u32 mp_gen_timer_reset_mask_2; + u32 mp_gen_timer_reset_mask_3; + u32 mp_gen_timer_reset_mask_4; + u32 mp_gen_timer_reset_mask_5; + u32 mp_gen_timer_reset_mask_6; + u32 mp_gen_timer_reset_mask_7; + u32 reserved19[7]; + u32 mp_cci_adb400_dcm_config; + u32 mp_sync_dcm_config; + u32 reserved20[1]; + u32 mp_sync_dcm_cluster_config; + u32 sw_udi; + u32 reserved21[1]; + u32 gic_sync_dcm; + u32 big_dbg_pwr_ctrl; + u32 gic_cpu_periphbase; + u32 axi_cpu_config; + u32 reserved22[2]; + u32 mcsib_sys_ctrl1; + u32 mcsib_sys_ctrl2; + u32 mcsib_sys_ctrl3; + u32 mcsib_sys_ctrl4; + u32 mcsib_dbg_ctrl1; + u32 pwrmcu_apb2to1; + u32 reserved23[1]; + u32 mp1_spmc; + u32 reserved24[1]; + u32 mp1_spmc_sram_ctl; + u32 reserved25[1]; + u32 mp1_sw_rst_wait_cycle; + u32 mp0_pll_divider_cfg; + u32 reserved26[1]; + u32 mp2_pll_divider_cfg; + u32 reserved27[5]; + u32 bus_pll_divider_cfg; + u32 reserved28[7]; + u32 clusterid_aff1; + u32 clusterid_aff2; + u32 hack_ice_rom_table_access; + u32 mp_top_mem_delay_cfg; + u32 l2c_cfg_mp0; + u32 reserved29[1]; + u32 l2c_cfg_mp2; + u32 reserved30[1]; + u32 cci_bw_pmu_ctl; + u32 cci_bw_pmu_cnt0to1_sel; + u32 cci_bw_pmu_cnt2to3_sel; + u32 cci_bw_pmu_cnt4to5_sel; + u32 cci_bw_pmu_cnt6to7_sel; + u32 cci_bw_pmu_cnt0to3_mask; + u32 cci_bw_pmu_cnt4to7_mask; + u32 cci_bw_pmu_ref_cnt; + u32 cci_bw_pmu_acc_cnt0; + u32 cci_bw_pmu_acc_cnt1; + u32 cci_bw_pmu_acc_cnt2; + u32 cci_bw_pmu_acc_cnt3; + u32 cci_bw_pmu_acc_cnt4; + u32 cci_bw_pmu_acc_cnt5; + u32 cci_bw_pmu_acc_cnt6; + u32 cci_bw_pmu_acc_cnt7; + u32 reserved31[8]; + u32 cci_bw_pmu_id_ext_cnt0to3; + u32 cci_bw_pmu_id_ext_cnt4to7; + u32 cci_bw_pmu_mask_ext_cnt0to3; + u32 cci_bw_pmu_mask_ext_cnt4to7; + u32 reserved32[16]; + u32 etb_acc_ctl; + u32 etb_ck_ctl; + u32 reserved33[4]; + u32 mbista_mp1_ocp_con; + u32 reserved34[1]; + u32 mbista_gic_con; + u32 mbista_gic_result; + u32 mbista_mcsib_sf1_con; + u32 mbista_mcsib_sf1_result; + u32 mbista_mcsib_sf2_con; + u32 mbista_mcsib_sf2_result; + u32 reserved35[2]; + u32 mbista_rstb; + u32 mbista_all_result; + u32 reserved36[2]; + u32 mp0_hang_monitor_ctrl0; + u32 mp0_hang_monitor_ctrl1; + u32 reserved37[2]; + u32 mp1_hang_monitor_ctrl0; + u32 mp1_hang_monitor_ctrl1; + u32 reserved38[2]; + u32 mp2_hang_monitor_ctrl0; + u32 mp2_hang_monitor_ctrl1; + u32 reserved39[6]; + u32 gpu_hang_monitor_ctrl0; + u32 gpu_hang_monitor_ctrl1; + u32 reserved40[2]; + u32 psys_hang_monitor_ctrl0; + u32 psys_hang_monitor_ctrl1; + u32 reserved41[42]; + u32 sec_pol_ctl_en0; + u32 sec_pol_ctl_en1; + u32 sec_pol_ctl_en2; + u32 sec_pol_ctl_en3; + u32 sec_pol_ctl_en4; + u32 sec_pol_ctl_en5; + u32 sec_pol_ctl_en6; + u32 sec_pol_ctl_en7; + u32 sec_pol_ctl_en8; + u32 sec_pol_ctl_en9; + u32 sec_pol_ctl_en10; + u32 sec_pol_ctl_en11; + u32 sec_pol_ctl_en12; + u32 sec_pol_ctl_en13; + u32 sec_pol_ctl_en14; + u32 sec_pol_ctl_en15; + u32 sec_pol_ctl_en16; + u32 sec_pol_ctl_en17; + u32 sec_pol_ctl_en18; + u32 sec_pol_ctl_en19; + u32 reserved42[12]; + u32 int_pol_ctl0; + u32 int_pol_ctl1; + u32 int_pol_ctl2; + u32 int_pol_ctl3; + u32 int_pol_ctl4; + u32 int_pol_ctl5; + u32 int_pol_ctl6; + u32 int_pol_ctl7; + u32 int_pol_ctl8; + u32 int_pol_ctl9; + u32 int_pol_ctl10; + u32 int_pol_ctl11; + u32 int_pol_ctl12; + u32 int_pol_ctl13; + u32 int_pol_ctl14; + u32 int_pol_ctl15; + u32 int_pol_ctl16; + u32 int_pol_ctl17; + u32 int_pol_ctl18; + u32 int_pol_ctl19; + u32 reserved43[12]; + u32 dfd_internal_ctl; + u32 dfd_internal_counter; + u32 dfd_internal_pwr_on; + u32 dfd_internal_chain_legth_0; + u32 dfd_internal_shift_clk_ratio; + u32 dfd_internal_counter_return; + u32 dfd_internal_sram_access; + u32 dfd_internal_chain_length_1; + u32 dfd_internal_chain_length_2; + u32 dfd_internal_chain_length_3; + u32 dfd_internal_test_so_0; + u32 dfd_internal_test_so_1; + u32 dfd_internal_num_of_test_so_gp; + u32 dfd_internal_test_so_over_64; + u32 dfd_internal_mask_out; + u32 dfd_internal_sw_ns_trigger; + u32 dfd_internal_mcsib; + u32 dfd_internal_mcsib_sel_status; + u32 dfd_internal_sram_base_addr; + u32 dfd_internal_sram_delsel; + u32 mcsib_iccs_ctrl1; + u32 reserved44[1]; + u32 mcu_all_pwr_on_ctrl; + u32 emi_wfifo; + u32 mcsia_dcm_en; + u32 reserved45[294]; + u32 mcu_apb_base; + u32 reserved46[384]; + u32 mp0_cpu_avg_stall_ratio; + u32 mp0_cpu0_avg_stall_ratio_ctrl; + u32 mp0_cpu1_avg_stall_ratio_ctrl; + u32 mp0_cpu2_avg_stall_ratio_ctrl; + u32 mp0_cpu3_avg_stall_ratio_ctrl; + u32 mp0_avg_stall_ratio_status; + u32 mp0_cpu0_stall_counter; + u32 mp0_cpu1_stall_counter; + u32 mp0_cpu2_stall_counter; + u32 mp0_cpu3_stall_counter; + u32 mp0_cpu0_non_wfi_counter; + u32 mp0_cpu1_non_wfi_counter; + u32 mp0_cpu2_non_wfi_counter; + u32 mp0_cpu3_non_wfi_counter; + u32 reserved47[370]; + u32 cpusys0_sparkvretcntrl; + u32 cpusys0_sparken; + u32 cpusys0_amuxsel; + u32 cpusys0_cg_dis; + u32 cpusys0_cpu0_counter; + u32 cpusys0_cpu1_counter; + u32 cpusys0_cpu2_counter; + u32 cpusys0_cpu3_counter; + u32 cpusys0_spark_debug_overwrite; + u32 reserved48[3]; + u32 cpusys0_cpu0_spmc_ctl; + u32 cpusys0_cpu1_spmc_ctl; + u32 cpusys0_cpu2_spmc_ctl; + u32 cpusys0_cpu3_spmc_ctl; + u32 sesv3_rg_toggle; + u32 reserved49[7]; + u32 mp0_sync_dcm_cgavg_ctrl; + u32 mp0_sync_dcm_cgavg_fact; + u32 mp0_sync_dcm_cgavg_rfact; + u32 mp0_sync_dcm_cgavg; +}; + +check_member(mt8183_mcucfg_regs, mp0_cache_mem_delsel0, 0x0024); +check_member(mt8183_mcucfg_regs, mp_dbg_ctrl, 0x0404); +check_member(mt8183_mcucfg_regs, mp_dfd_ctrl, 0x0490); +check_member(mt8183_mcucfg_regs, dvm_op_arid_mp0, 0x04c0); +check_member(mt8183_mcucfg_regs, cci_s6_if_debug, 0x04e0); +check_member(mt8183_mcucfg_regs, mp1_rst_status, 0x0500); +check_member(mt8183_mcucfg_regs, mcusys_dbg_mon_sel_a, 0x0590); +check_member(mt8183_mcucfg_regs, dbg_core_ret, 0x05fc); +check_member(mt8183_mcucfg_regs, aclken_div, 0x0640); +check_member(mt8183_mcucfg_regs, mcusys_rw_rsvd0, 0x0684); +check_member(mt8183_mcucfg_regs, gic500_delsel_ctl, 0x06c0); +check_member(mt8183_mcucfg_regs, mp_gen_timer_reset_mask_secur_en, 0x0700); +check_member(mt8183_mcucfg_regs, mp_cci_adb400_dcm_config, 0x0740); +check_member(mt8183_mcucfg_regs, mcsib_sys_ctrl1, 0x0770); +check_member(mt8183_mcucfg_regs, bus_pll_divider_cfg, 0x07c0); +check_member(mt8183_mcucfg_regs, clusterid_aff1, 0x07e0); +check_member(mt8183_mcucfg_regs, cci_bw_pmu_id_ext_cnt0to3, 0x0860); +check_member(mt8183_mcucfg_regs, etb_acc_ctl, 0x08b0); +check_member(mt8183_mcucfg_regs, mbista_mp1_ocp_con, 0x08c8); +check_member(mt8183_mcucfg_regs, mbista_rstb, 0x08f0); +check_member(mt8183_mcucfg_regs, mp0_hang_monitor_ctrl0, 0x0900); +check_member(mt8183_mcucfg_regs, mp1_hang_monitor_ctrl0, 0x0910); +check_member(mt8183_mcucfg_regs, mp2_hang_monitor_ctrl0, 0x0920); +check_member(mt8183_mcucfg_regs, gpu_hang_monitor_ctrl0, 0x0940); +check_member(mt8183_mcucfg_regs, psys_hang_monitor_ctrl0, 0x0950); +check_member(mt8183_mcucfg_regs, sec_pol_ctl_en0, 0x0a00); +check_member(mt8183_mcucfg_regs, int_pol_ctl0, 0x0a80); +check_member(mt8183_mcucfg_regs, dfd_internal_ctl, 0x0b00); +check_member(mt8183_mcucfg_regs, mcu_apb_base, 0x0ffc); +check_member(mt8183_mcucfg_regs, mp0_cpu_avg_stall_ratio, 0x1600); +check_member(mt8183_mcucfg_regs, cpusys0_sparkvretcntrl, 0x1c00); +check_member(mt8183_mcucfg_regs, cpusys0_cpu0_spmc_ctl, 0x1c30); +check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg_ctrl, 0x1c60); +check_member(mt8183_mcucfg_regs, mp0_sync_dcm_cgavg, 0x1c6c); + +static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE; + +#endif /* SOC_MEDIATEK_MT8183_MCUCFG_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/mmu_operations.h b/src/soc/mediatek/mt8183/include/soc/mmu_operations.h new file mode 100644 index 0000000..a268089 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/mmu_operations.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT8183_MMU_OPERATIONS_H__ +#define __SOC_MEDIATEK_MT8183_MMU_OPERATIONS_H__ + +#include <arch/mmu.h> + +enum { + DEV_MEM = MA_DEV | MA_S | MA_RW, + CACHED_MEM = MA_MEM | MA_NS | MA_RW, + SECURE_MEM = MA_MEM | MA_S | MA_RW, + UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, +}; + +extern unsigned char _sram_l2c[]; +extern unsigned char _esram_l2c[]; +#define _sram_l2c_size (_esram_l2c - _sram_l2c) + +void mt8183_mmu_init(void); +void mt8183_mmu_after_dram(void); + +#endif //__SOC_MEDIATEK_MT8183_MMU_OPERATIONS_H__ diff --git a/src/soc/mediatek/mt8183/mmu_operations.c b/src/soc/mediatek/mt8183/mmu_operations.c new file mode 100644 index 0000000..94e9f45 --- /dev/null +++ b/src/soc/mediatek/mt8183/mmu_operations.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/mmu.h> +#include <symbols.h> +#include <soc/emi.h> +#include <soc/mcucfg.h> +#include <soc/mmu_operations.h> + +void mt8183_mmu_init(void) +{ + mmu_init(); + + /* Set 0x0 to the end of 2GB dram address as device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM); + + /* SRAM is cached */ + mmu_config_range(_sram, _sram_size, CACHED_MEM); + + /* L2C SRAM is cached */ + mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM); + + /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ + mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + + /* set ttb as secure */ + mmu_config_range(_ttb, _ttb_size, SECURE_MEM); + + mmu_enable(); +} + +void mt8183_mmu_after_dram(void) +{ + /* Map DRAM as cached now that it's up and running */ + mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM); + + /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ + /* TODO: Implement true unmapping, and also use it for the zero-page! */ + mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM); + + /* Careful: changing cache geometry while it's active is a bad idea! */ + mmu_disable(); + + /* Turn off L2C SRAM and return it to L2 cache. */ + write32(&mt8183_mcucfg->l2c_cfg_mp0, 7 << 8); + + /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ + mmu_enable(); +} -- To view, visit https://review.coreboot.org/27303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32 Gerrit-Change-Number: 27303 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: payloads/iPXE: add iPXE serial enable option
by Piotr Król (Code Review) 02 Jul '18

02 Jul '18

Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/27302 to review the following change. Change subject: payloads/iPXE: add iPXE serial enable option ...................................................................... payloads/iPXE: add iPXE serial enable option Since SeaBIOS 1.11.0 implements serial console and etc/sercon-port runtime config file is present in CBFS, SeaBIOS additionally redirects iPXE output to configured IO port. For boards which use the same UART for SeaBIOS and iPXE console it causes doubled output. The option is enabled by default and passes UART configuration to iPXE Makefile as before. When unselected, only SeaBIOS handles printing output from iPXE. Change-Id: Ia3c74cfbee4f816782161fcff286a14f46be78c5 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> --- M payloads/external/Makefile.inc M payloads/external/iPXE/Kconfig 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/27302/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 3943db9..1d3e7a1 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -234,6 +234,12 @@ IPXE_UART=COM$(call int-add,$(CONFIG_UART_FOR_CONSOLE) 1) endif +ifeq ($(CONFIG_PXE_SERIAL_CONSOLE),y) +IPXE_SERIAL_CONSOLE = $(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO) +else +IPXE_SERIAL_CONSOLE = n +endif + cbfs-files-$(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE) += pci$(CONFIG_PXE_ROM_ID).rom pci$(CONFIG_PXE_ROM_ID).rom-file := $(PXE_ROM_FILE) pci$(CONFIG_PXE_ROM_ID).rom-type := raw @@ -244,7 +250,7 @@ PXE_ROM_PCI_ID=$(PXE_ROM_PCI_ID) \ CONFIG_IPXE_MASTER=$(CONFIG_IPXE_MASTER) \ CONFIG_IPXE_STABLE=$(CONFIG_IPXE_STABLE) \ - CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO) \ + CONSOLE_SERIAL=$(IPXE_SERIAL_CONSOLE) \ IPXE_UART=$(IPXE_UART) \ CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \ MFLAGS= MAKEFLAGS= diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index 82114107..ce0a7ae 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -78,5 +78,14 @@ Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices. +config PXE_SERIAL_CONSOLE + bool "Enable iPXE serial console" + def_bool y + help + Enable/disable iPXE serial console. Since SeaBIOS supports serial + console this option might be helpful to avoid duplicated output. + + Unselect to let only SeaBIOS handle printing output. + endmenu endif -- To view, visit https://review.coreboot.org/27302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia3c74cfbee4f816782161fcff286a14f46be78c5 Gerrit-Change-Number: 27302 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>

1 0

Change in coreboot[master]: mb/pcengines/apu1: use generic SPD
by Piotr Król (Code Review) 02 Jul '18

02 Jul '18

Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/27301 to review the following change. Change subject: mb/pcengines/apu1: use generic SPD ...................................................................... mb/pcengines/apu1: use generic SPD Clean up leftovers of old SPD generation and utilize common procedure to produce SPD binary. Change-Id: I4e48817c03b4372887bc0ea14209736ae2b4e48f Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu1/Makefile.inc R src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex R src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex 4 files changed, 3 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/27301/1 diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 5e927cc..19a5de4 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -29,6 +29,7 @@ select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 + select GENERIC_SPD_BIN config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc index 324e4aa..543ac97 100644 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ b/src/mainboard/pcengines/apu1/Makefile.inc @@ -31,22 +31,7 @@ ramstage-y += OemCustomize.c ramstage-y += gpio_ftns.c -## DIMM SPD for on-board memory -SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = HYNIX-H5TQ2G83CFR HYNIX-H5TQ4G83MFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd +SPD_SOURCES = HYNIX-H5TQ2G83CFR +SPD_SOURCES += HYNIX-H5TQ4G83MFR diff --git a/src/mainboard/pcengines/apu1/HYNIX-H5TQ2G83CFR.spd.hex b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex similarity index 100% rename from src/mainboard/pcengines/apu1/HYNIX-H5TQ2G83CFR.spd.hex rename to src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex diff --git a/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex similarity index 100% rename from src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex rename to src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex -- To view, visit https://review.coreboot.org/27301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e48817c03b4372887bc0ea14209736ae2b4e48f Gerrit-Change-Number: 27301 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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Change in coreboot[master]: nb/intel/i945: Programm proper ODT values
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18548 ) Change subject: nb/intel/i945: Programm proper ODT values ...................................................................... Patch Set 15: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29701/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75647/ : SUCCESS -- To view, visit https://review.coreboot.org/18548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Gerrit-Change-Number: 18548 Gerrit-PatchSet: 15 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 08:37:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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