coreboot-gerrit July 2018

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Change in coreboot[master]: mb/google/poppy/variant/atlas: Update PL2 based on CPU sku
by Gaggery Tsai (Code Review) 01 Aug '18

01 Aug '18

Hello Caveh Jalali, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27765 to look at the new patch set (#2). Change subject: mb/google/poppy/variant/atlas: Update PL2 based on CPU sku ...................................................................... mb/google/poppy/variant/atlas: Update PL2 based on CPU sku This patch adds a function to overwrite PL2 setting based on CPU sku. BUG=None BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y and KBL-Y skus. Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/Makefile.inc A src/mainboard/google/poppy/variants/atlas/mainboard.c 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27765/2 -- To view, visit https://review.coreboot.org/27765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26 Gerrit-Change-Number: 27765 Gerrit-PatchSet: 2 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com>

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Change in coreboot[master]: security/tpm: Add TCPA logging functionality
by Philipp Deppenwiese (Code Review) 01 Aug '18

01 Aug '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/22867 ) Change subject: security/tpm: Add TCPA logging functionality ...................................................................... Patch Set 41: Will do a follow up tomorrow -- To view, visit https://review.coreboot.org/22867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a52494f647d21e2587231af26ed13d62b3a72f5 Gerrit-Change-Number: 22867 Gerrit-PatchSet: 41 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 23:54:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/atlas: Update PL2 based on CPU sku
by Gaggery Tsai (Code Review) 01 Aug '18

01 Aug '18

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/27765 Change subject: mb/google/poppy/variant/atlas: Update PL2 based on CPU sku ...................................................................... mb/google/poppy/variant/atlas: Update PL2 based on CPU sku This patch adds a function to overwrite PL2 setting based on CPU sku. BUG=None BRANCH=None TEST=emerge-atlas coreboot chemos-bootimage & test with AML-Y and KBL-Y skus. Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/Makefile.inc A src/mainboard/google/poppy/variants/atlas/mainboard.c 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27765/1 diff --git a/src/mainboard/google/poppy/variants/atlas/Makefile.inc b/src/mainboard/google/poppy/variants/atlas/Makefile.inc index ad40bb0..06776ff 100644 --- a/src/mainboard/google/poppy/variants/atlas/Makefile.inc +++ b/src/mainboard/google/poppy/variants/atlas/Makefile.inc @@ -19,3 +19,4 @@ ramstage-y += gpio.c ramstage-y += nhlt.c +ramstage-y += mainboard.c diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c new file mode 100644 index 0000000..36b703c --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <assert.h> +#include <baseboard/variants.h> +#include <cbfs.h> +#include <chip.h> +#include <commonlib/cbfs_serialized.h> +#include <compiler.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <drivers/intel/gma/opregion.h> +#include <intelblocks/mp_init.h> +#include <smbios.h> +#include <soc/ramstage.h> +#include <string.h> + +#define PL2_AML 18 +#define PL2_KBL 15 + +static uint16_t get_dev_id(struct device *dev) +{ + return pci_read_config16(dev, PCI_DEVICE_ID); +} + +static uint32_t get_pl2(void) +{ + uint16_t id; + id = get_dev_id(SA_DEV_IGD); + if (id == PCI_DEVICE_ID_INTEL_KBL_GT2_ULX_R) + return PL2_AML; + + return PL2_KBL; +} + +/* Override dev tree settings per board */ +void variant_devtree_update(void) +{ + struct device *root = SA_DEV_ROOT; + config_t *cfg = root->chip_info; + + /* Update PL2 based on CPU */ + cfg->tdp_pl2_override = get_pl2(); +} -- To view, visit https://review.coreboot.org/27765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26 Gerrit-Change-Number: 27765 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>

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Change in coreboot[master]: google/banon: Add support for additional RAM types/configs
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27764 to look at the new patch set (#4). Change subject: google/banon: Add support for additional RAM types/configs ...................................................................... google/banon: Add support for additional RAM types/configs Adapted from chromium commits 831a372 and cc96c27 [Banon: board 2nd source DDR memory] Add support for hynix/H9CCNNN8GTALAR-NUD and Nanya/NT6CL256T32CM-H1 Original-Change-Id: Ifd161ba5ade44e71c88655f760ca66668b5c5178 Original-Change-Id: I5cba13701ed8e037e21d34ed55162ee56291a842 Original-Signed-off-by: T.H. Lin <T.H_Lin(a)quantatw.com> Original-Tested-by: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Original-Reviewed-by: Vincent Wang <vwang(a)chromium.org> Original-Reviewed-by: YH Lin <yueherngl(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/banon/Makefile.inc M src/mainboard/google/cyan/variants/banon/spd_util.c 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/27764/4 -- To view, visit https://review.coreboot.org/27764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 Gerrit-Change-Number: 27764 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: drivers/spi: Read Winbond's flash protection bits
by Philipp Deppenwiese (Code Review) 01 Aug '18

01 Aug '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/25082 ) Change subject: drivers/spi: Read Winbond's flash protection bits ...................................................................... Patch Set 11: Julius any idea what's the best solution? -- To view, visit https://review.coreboot.org/25082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5 Gerrit-Change-Number: 25082 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 23:29:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Report Whiskey Lake info
by Furquan Shaikh (Code Review) 01 Aug '18

01 Aug '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27756 ) Change subject: soc/intel/cannonlake: Report Whiskey Lake info ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27756/1/src/soc/intel/cannonlake/bootblock/… File src/soc/intel/cannonlake/bootblock/report_platform.c: https://review.coreboot.org/#/c/27756/1/src/soc/intel/cannonlake/bootblock/… PS1, Line 72: Cannonlake Whiskeylake? -- To view, visit https://review.coreboot.org/27756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Gerrit-Change-Number: 27756 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 22:57:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: google/cyan: do not hardcode virtual interrupt numbers
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27758 to look at the new patch set (#3). Change subject: google/cyan: do not hardcode virtual interrupt numbers ...................................................................... google/cyan: do not hardcode virtual interrupt numbers Adapted from chromium commit ee7a150 [Strago: do not hardcode virtual interrupt numbers] Instead of hardcoding virtual interrupt numbers that may change as the kernel changes, use GpioInt() resources to describe keyboard, touchpad, and touchscreen interrupt lines. TEST=Build and boot several cyan variant boards, verify keyboard, touchpad and touchscreen work with newer kernels (4.14+). Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b Original-Signed-off-by: Dmitry Torokhov <dtor(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894687 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Iecfb45be433249d274532eb746588483fedb3f52 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/touchscreen_elan.asl M src/mainboard/google/cyan/acpi/touchscreen_melfas.asl M src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl M src/mainboard/google/cyan/acpi/trackpad_atmel.asl M src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h M src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h M src/mainboard/google/cyan/variants/reks/include/variant/onboard.h M src/mainboard/google/cyan/variants/relm/include/variant/onboard.h M src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h M src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h M src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h 11 files changed, 20 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27758/3 -- To view, visit https://review.coreboot.org/27758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iecfb45be433249d274532eb746588483fedb3f52 Gerrit-Change-Number: 27758 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/cyan: Switch Touchpad and Touchscreen interrupts to be level-t...
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27759 to look at the new patch set (#2). Change subject: google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggered ...................................................................... google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggered Adapted from chromium commit 126d352 [Strago: switch Touchpad and Touchscreen interrupts to be level-triggered] The Elan and other touch controllers found in this device work much more reliably if used with level-triggered interrupts rather than edge-triggered. TEST=Boot several cyan boards, verify that touchpad and touchscreen work. Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889 Original-Signed-off-by: Dmitry Torokhov <dtor(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894689 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/trackpad_atmel.asl M src/mainboard/google/cyan/variants/banon/gpio.c M src/mainboard/google/cyan/variants/celes/gpio.c M src/mainboard/google/cyan/variants/cyan/gpio.c M src/mainboard/google/cyan/variants/edgar/gpio.c M src/mainboard/google/cyan/variants/kefka/gpio.c M src/mainboard/google/cyan/variants/reks/gpio.c M src/mainboard/google/cyan/variants/relm/gpio.c M src/mainboard/google/cyan/variants/setzer/gpio.c M src/mainboard/google/cyan/variants/terra/gpio.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/cyan/variants/wizpig/gpio.c M src/soc/intel/braswell/include/soc/gpio.h 13 files changed, 25 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/27759/2 -- To view, visit https://review.coreboot.org/27759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8 Gerrit-Change-Number: 27759 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/cyan: do not hardcode virtual interrupt numbers
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27758 to look at the new patch set (#2). Change subject: google/cyan: do not hardcode virtual interrupt numbers ...................................................................... google/cyan: do not hardcode virtual interrupt numbers Adapted from chromium commit ee7a150 [Strago: do not hardcode virtual interrupt numbers] Instead of hardcoding virtual interrupt numbers that may change as the kernel changes, use GpioInt() resources to describe keyboard, touchpad, and touchscreen interrupt lines. TEST=Build and boot several cyan variant boards, verify keyboard, touchpad and touchscreen work with newer kernels (4.14+). Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b Original-Signed-off-by: Dmitry Torokhov <dtor(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894687 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Iecfb45be433249d274532eb746588483fedb3f52 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/touchscreen_elan.asl M src/mainboard/google/cyan/acpi/touchscreen_melfas.asl M src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl M src/mainboard/google/cyan/acpi/trackpad_atmel.asl M src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h M src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h M src/mainboard/google/cyan/variants/reks/include/variant/onboard.h M src/mainboard/google/cyan/variants/relm/include/variant/onboard.h M src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h M src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h M src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h 11 files changed, 18 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27758/2 -- To view, visit https://review.coreboot.org/27758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iecfb45be433249d274532eb746588483fedb3f52 Gerrit-Change-Number: 27758 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/banon: Add support for additional RAM types/configs
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27764 Change subject: google/banon: Add support for additional RAM types/configs ...................................................................... google/banon: Add support for additional RAM types/configs Adapted from chromium commits 831a372 and cc96c27 [Banon: board 2nd source DDR memory] Add support for hynix/H9CCNNN8GTALAR-NUD and Nanya/NT6CL256T32CM-H1 Original-Change-Id: Ifd161ba5ade44e71c88655f760ca66668b5c5178 Original-Change-Id: I5cba13701ed8e037e21d34ed55162ee56291a842 Original-Signed-off-by: T.H. Lin <T.H_Lin(a)quantatw.com> Original-Tested-by: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Original-Reviewed-by: Vincent Wang <vwang(a)chromium.org> Original-Reviewed-by: YH Lin <yueherngl(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/banon/Makefile.inc M src/mainboard/google/cyan/variants/banon/spd_util.c 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/27764/1 diff --git a/src/mainboard/google/cyan/variants/banon/Makefile.inc b/src/mainboard/google/cyan/variants/banon/Makefile.inc index f6a1f46..7210f15 100644 --- a/src/mainboard/google/cyan/variants/banon/Makefile.inc +++ b/src/mainboard/google/cyan/variants/banon/Makefile.inc @@ -26,6 +26,8 @@ SPD_SOURCES += empty SPD_SOURCES += hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF +SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD +SPD_SOURCES += nayna_dimm_NT6CL256T32CM-H1 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/cyan/variants/banon/spd_util.c b/src/mainboard/google/cyan/variants/banon/spd_util.c index 2c9181e..442a5ba 100644 --- a/src/mainboard/google/cyan/variants/banon/spd_util.c +++ b/src/mainboard/google/cyan/variants/banon/spd_util.c @@ -23,11 +23,14 @@ * 0b0001 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF * 0b0011 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8JTBLAR * 0b0100 - 4GiB total - 2 x 2GiB Micron MT52L256M32D1PF - * + * 0b0101 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8GTALAR + * 0b0110 - 4GiB total - 2 x 2GiB NY NT6CL256T32CM-H1 * 0b1000 - 2GiB total - 1 x 2GiB Samsung K4E8E304EE-EGCE * 0b1001 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF * 0b1011 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8JTBLAR * 0b1100 - 2GiB total - 1 x 2GiB Micron MT52L256M32D1PF + * 0b1101 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8GTALAR + * 0b1110 - 2GiB total - 1 x 2GiB NY NT6CL256T32CM-H1 */ int get_variant_spd_index(int ram_id, int *dual) @@ -56,7 +59,13 @@ case 4: printk(BIOS_DEBUG, "Micron MT52L256M32D1PF\n"); break; + case 5: + printk(BIOS_DEBUG, "Hynix H9CCNNN8GTALAR\n"); + break; } + case 6: + printk(BIOS_DEBUG, "Nanya NT6CL256T32CM-H1\n"); + break; return spd_index; } -- To view, visit https://review.coreboot.org/27764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736 Gerrit-Change-Number: 27764 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit July 2018