coreboot-gerrit July 2018

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Change in coreboot[master]: google/cyan: Mask Audio IRQ on boot
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27761 Change subject: google/cyan: Mask Audio IRQ on boot ...................................................................... google/cyan: Mask Audio IRQ on boot Adapted from chromium commit cf18ab6 [Strago: mask Audio IRQ on boot] Do not start with audio interrupt unmasked; this causes interrupt storms on newer kernels that no longer mask all interrupts when initializing Cherryview pincontrol driver. TEST=Boot various cyan boards with kernels 3.18 and 4.14; verify everything works. Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43 Original-Signed-off-by: Dmitry Torokhov <dtor(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894688 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/celes/gpio.c M src/mainboard/google/cyan/variants/cyan/gpio.c M src/mainboard/google/cyan/variants/edgar/gpio.c M src/mainboard/google/cyan/variants/kefka/gpio.c M src/mainboard/google/cyan/variants/reks/gpio.c M src/mainboard/google/cyan/variants/relm/gpio.c M src/mainboard/google/cyan/variants/setzer/gpio.c M src/mainboard/google/cyan/variants/terra/gpio.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/cyan/variants/wizpig/gpio.c 10 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/27761/1 diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index 10ca3b0..d011428 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -140,7 +140,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 62fcb5e..4139f76 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -138,7 +138,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index 97e2dd1..d9d2648 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -137,7 +137,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 8340f1a..76549ba4 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -137,7 +137,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index 74792bd..1a9e540 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -139,7 +139,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 6b75a84..6c1dbdc 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -140,7 +140,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index a1564c1..df1bff1 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -138,7 +138,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 3f5c19d..8328edd 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -136,7 +136,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index 4e4f0f6..c6875b4 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -139,7 +139,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index cadaf02..3611439 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -138,7 +138,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ -- To view, visit https://review.coreboot.org/27761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546 Gerrit-Change-Number: 27761 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/cyan: Configure WLAN_CLKREQ as GPIO and always assert low
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27762 Change subject: google/cyan: Configure WLAN_CLKREQ as GPIO and always assert low ...................................................................... google/cyan: Configure WLAN_CLKREQ as GPIO and always assert low Adapted from chromium commit adcb858 [cyan: Configure WLAN_CLKREQ as GPIO and always assert low] This is a workaround for issue b/35648315 as proposed by Intel to ensure that WLAN_CLKREQ always stays low. BUG=b:35648315 Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1055652 Original-Reviewed-by: Rajat Jain <rajatja(a)chromium.org> Original-Tested-by: Rajat Jain <rajatja(a)chromium.org> Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/variants/cyan/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/27762/1 diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 4139f76..bf869fe 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -136,7 +136,9 @@ Native_M1, /* 90 PCIE_CLKREQ0B */ GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ Native_M1, /* 92 GP_SSP_2_CLK */ - NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + /* Workaround for issue b/35648315: Program this as GPIO and always + assert it low. */ + GPIO_OUT_LOW, /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ -- To view, visit https://review.coreboot.org/27762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938 Gerrit-Change-Number: 27762 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/edgar: Add support for additional RAM types/configs
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27763 Change subject: google/edgar: Add support for additional RAM types/configs ...................................................................... google/edgar: Add support for additional RAM types/configs Adapted from chromium commits 2319742 and 3b59fb2 [Edgar: Add Micron MT52L256M32D1PF-107 SPD data] [Edgar: Add Hynix H9CCNNN8GTALAR-NUD and Nanya NT6CL256T32CM-H1 SPD data] Supported 2nd source Hynix, Micron, and Nanya memory. TEST=Built and used mosys command by "mosys -k memory spd print all" Original-Change-Id: Iec9160b74d2812620d2d28f841d503e2d63c8579 Original-Change-Id: I610f01a0198f835a2038511ff78bf0cfba7812a0 Original-Signed-off-by: Hank2_Lin <Hank2_Lin(a)pegatroncorp.com> Original-Reviewed-by: Vincent Wang <vwang(a)chromium.org> Original-Reviewed-by: YH Lin <yueherngl(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: If2379d6e58425616f49d77b0cdea1cd90f9a8bfa Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- A src/mainboard/google/cyan/spd/nanya_dimm_NT6CL256T32CM-H1.spd.hex M src/mainboard/google/cyan/variants/edgar/Makefile.inc M src/mainboard/google/cyan/variants/edgar/spd_util.c 3 files changed, 46 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/27763/1 diff --git a/src/mainboard/google/cyan/spd/nanya_dimm_NT6CL256T32CM-H1.spd.hex b/src/mainboard/google/cyan/spd/nanya_dimm_NT6CL256T32CM-H1.spd.hex new file mode 100644 index 0000000..d24c980 --- /dev/null +++ b/src/mainboard/google/cyan/spd/nanya_dimm_NT6CL256T32CM-H1.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 00 04 11 05 0B 03 11 01 08 09 00 40 05 +67 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 A0 CA E6 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 1F 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 83 0B 00 00 00 00 00 00 00 63 4D +4E 54 36 43 4C 32 35 36 54 33 32 43 4D 2D 48 31 +20 20 00 00 83 0B 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index e553c88..2e8b02c 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -25,8 +25,13 @@ SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCE SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF -SPD_SOURCES += empty +SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF +SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 +SPD_SOURCES += nanya_dimm_NT6CL256T32CM-H1 +SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD +SPD_SOURCES += nanya_dimm_NT6CL256T32CM-H1 +SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/cyan/variants/edgar/spd_util.c b/src/mainboard/google/cyan/variants/edgar/spd_util.c index 9651c27..f9b3681 100644 --- a/src/mainboard/google/cyan/variants/edgar/spd_util.c +++ b/src/mainboard/google/cyan/variants/edgar/spd_util.c @@ -23,9 +23,14 @@ * 0b0001 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8JTBLAR-NUD * 0b0010 - 2GiB total - 1 x 2GiB Samsung K4E8E304EE-EGCE * 0b0011 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8JTBLAR-NUD - * 0b0100 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF - * 0b0101 - TBD - * 0b0110 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF + * 0b0100 - 8GiB total - 2 x 4GiB Samsung K4E8E324EB-EGCF (dual) + * 0b0101 - 4GiB total - 2 x 2GiB Micron LPDDR3 MT52L256M32D1PF-107 (dual) + * 0b0110 - 4GiB total - 1 x 4GiB Samsung K4E8E324EB-EGCF + * 0b0111 - 2GiB total - 1 x 2GiB Micron LPDDR3 MT52L256M32D1PF-107 + * 0b1000 - 4GiB total - 2 x 2GiB NANYA NT6CL256T32CM-H1 (dual) + * 0b1001 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8GTALAR-NUD (dual) + * 0b1010 - 2GiB total - 1 x 2GiB NANYA NT6CL256T32CM-H1 + * 0b1011 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8GTALAR-NUD */ int get_variant_spd_index(int ram_id, int *dual) @@ -52,11 +57,26 @@ printk(BIOS_DEBUG, "4GiB Samsung K4E8E324EB-EGCF\n"); break; case 5: - printk(BIOS_DEBUG, "empty\n"); + printk(BIOS_DEBUG, "4GiB Micron LPDDR3 MT52L256M32D1PF-107\n"); break; case 6: printk(BIOS_DEBUG, "2GiB Samsung K4E8E324EB-EGCF\n"); break; + case 7: + printk(BIOS_DEBUG, "2GiB Micron LPDDR3 MT52L256M32D1PF-107\n"); + break; + case 8: + printk(BIOS_DEBUG, "4GiB NANYA NT6CL256T32CM-H1\n"); + break; + case 9: + printk(BIOS_DEBUG, "4GiB Hynix H9CCNNN8GTALAR-NUD\n"); + break; + case 10: + printk(BIOS_DEBUG, "2GiB NANYA NT6CL256T32CM-H1\n"); + break; + case 11: + printk(BIOS_DEBUG, "2GiB Hynix H9CCNNN8GTALAR-NUD\n"); + break; } /* 1:1 mapping between ram_id and spd_index for edgar */ -- To view, visit https://review.coreboot.org/27763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If2379d6e58425616f49d77b0cdea1cd90f9a8bfa Gerrit-Change-Number: 27763 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/cyan: Switch Touchpad and Touchscreen interrupts to be level-t...
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27759 Change subject: google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggered ...................................................................... google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggered Adapted from chromium commit 126d352 [Strago: switch Touchpad and Touchscreen interrupts to be level-triggered] The Elan and other touch controllers found in this device work much more reliably if used with level-triggered interrupts rather than edge-triggered. TEST=Boot several cyan boards, verify that touchpad and touchscreen work. Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889 Original-Signed-off-by: Dmitry Torokhov <dtor(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894689 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/trackpad_atmel.asl M src/mainboard/google/cyan/variants/banon/gpio.c M src/mainboard/google/cyan/variants/celes/gpio.c M src/mainboard/google/cyan/variants/cyan/gpio.c M src/mainboard/google/cyan/variants/edgar/gpio.c M src/mainboard/google/cyan/variants/kefka/gpio.c M src/mainboard/google/cyan/variants/reks/gpio.c M src/mainboard/google/cyan/variants/relm/gpio.c M src/mainboard/google/cyan/variants/setzer/gpio.c M src/mainboard/google/cyan/variants/terra/gpio.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/cyan/variants/wizpig/gpio.c 12 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/27759/1 diff --git a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl index 96ec3db..96f3185 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl @@ -33,7 +33,7 @@ AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C6", // ResourceSource ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } }) diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c index e077bcc..92ef836 100644 --- a/src/mainboard/google/cyan/variants/banon/gpio.c +++ b/src/mainboard/google/cyan/variants/banon/gpio.c @@ -161,9 +161,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index ebb7717..10ca3b0 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -164,7 +164,7 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ GPIO_NC, /* 19 GPIO_SUS1 */ diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 340a8af..62fcb5e 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -162,9 +162,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index 779b336..97e2dd1 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -161,7 +161,7 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ GPIO_NC, /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 00a6e26..8340f1a 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -161,9 +161,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index eac413b..74792bd 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -163,9 +163,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 8bd911c..6b75a84 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -164,9 +164,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index 2278200..a1564c1 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -162,9 +162,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 8c87916..3f5c19d 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -160,7 +160,7 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ GPIO_NC, /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index 94e5066..4e4f0f6 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -163,9 +163,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */ diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index ee94ac4..cadaf02 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -162,9 +162,9 @@ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_INPUT_NO_PULL, /* 21 SEC_GPIO_SUS11 */ -- To view, visit https://review.coreboot.org/27759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8 Gerrit-Change-Number: 27759 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/cyan: Mark GpioInt() resources as PullDefault
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27760 Change subject: google/cyan: Mark GpioInt() resources as PullDefault ...................................................................... google/cyan: Mark GpioInt() resources as PullDefault Adapted from chromium commit 3750e09 [Strago: mark GpioInt() resources as PullDefault] coreboot considers GPIO resources first-class citizens and initializes all pads according to their intended use, with necessary pull settings applied. Therefore let's use PullDefault as pull qualifier in AML, letting the kernel know that it shoudl not attempt to alter pull settings when using GPIOs. TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices. Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b Original-Signed-off-by: Dmitry Torokhov <dtor(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/898259 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl M src/mainboard/google/cyan/acpi/mainboard.asl M src/mainboard/google/cyan/acpi/superio.asl M src/mainboard/google/cyan/acpi/touchscreen_elan.asl M src/mainboard/google/cyan/acpi/touchscreen_melfas.asl M src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl M src/mainboard/google/cyan/acpi/trackpad_atmel.asl M src/mainboard/google/cyan/acpi/trackpad_elan.asl 9 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/27760/1 diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index 9abc91e..81bec16 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -47,7 +47,7 @@ "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } } ) Return (SBUF) @@ -91,7 +91,7 @@ "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } } ) @@ -111,7 +111,7 @@ Name (GBUF, ResourceTemplate () { /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } }) } diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl index d3fa84e..4a1d48d 100644 --- a/src/mainboard/google/cyan/acpi/codec_realtek.asl +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -39,7 +39,7 @@ ) /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } } ) Return (SBUF) @@ -57,7 +57,7 @@ Name (GBUF, ResourceTemplate () { /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } }) } diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl index 9f27ac9..af0dc75 100644 --- a/src/mainboard/google/cyan/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -23,7 +23,7 @@ { Name (RBUF, ResourceTemplate () { - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_SCI_GPIO_INDEX } }) Return (RBUF) diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl index ca973d0..b3961c0 100644 --- a/src/mainboard/google/cyan/acpi/superio.asl +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -23,7 +23,7 @@ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ /* Override default IRQ settings */ -#define SIO_EC_PS2K_IRQ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,\ +#define SIO_EC_PS2K_IRQ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,,\ "\\_SB.GPNC") { BOARD_I8042_GPIO_INDEX } /* ACPI code for EC SuperIO functions */ diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl index 7e3c7ae..cd67a0e 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -35,7 +35,7 @@ AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C1", /* ResourceSource */ ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TOUCH_GPIO_INDEX } } ) diff --git a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl index f54f886..905b7b8 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl @@ -35,7 +35,7 @@ AddressingMode7Bit, /* AddressingMode */ "\\_SB.I2C1", /* ResourceSource */ ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TOUCH_GPIO_INDEX } }) Return (BUF0) diff --git a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl index f0db3a3..1b10848 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl @@ -78,7 +78,7 @@ AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C1", /* ResourceSource */ ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TOUCH_GPIO_INDEX } }) Return (BUF0) diff --git a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl index 96f3185..9e63d12 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl @@ -33,7 +33,7 @@ AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C6", // ResourceSource ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } }) diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl index f89e1bc..4a80c19 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_elan.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl @@ -32,7 +32,7 @@ AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C6", /* ResourceSource */ ) - GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } }) -- To view, visit https://review.coreboot.org/27760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783 Gerrit-Change-Number: 27760 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/cyan: do not hardcode virtual interrupt numbers
by Matt DeVillier (Code Review) 01 Aug '18

01 Aug '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27758 Change subject: google/cyan: do not hardcode virtual interrupt numbers ...................................................................... google/cyan: do not hardcode virtual interrupt numbers Adapted from chromium commit ee7a150 [Strago: do not hardcode virtual interrupt numbers] Instead of hardcoding virtual interrupt numbers that may change as the kernel changes, use GpioInt() resources to describe keyboard, touchpad, and touchscreen interrupt lines. TEST=Build and boot several cyan variant boards, verify keyboard, touchpad and touchscreen work with newer kernels (4.14+). Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b Original-Signed-off-by: Dmitry Torokhov <dtor(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894687 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Iecfb45be433249d274532eb746588483fedb3f52 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/touchscreen_elan.asl M src/mainboard/google/cyan/acpi/touchscreen_melfas.asl M src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl M src/mainboard/google/cyan/acpi/trackpad_atmel.asl M src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h M src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h M src/mainboard/google/cyan/variants/reks/include/variant/onboard.h M src/mainboard/google/cyan/variants/relm/include/variant/onboard.h M src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h M src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h M src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h 11 files changed, 8 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27758/1 diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl index 7100120..7e3c7ae 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -35,10 +35,8 @@ AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C1", /* ResourceSource */ ) - Interrupt (ResourceConsumer, Level, ActiveLow) - { - BOARD_TOUCH_IRQ - } + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_TOUCH_GPIO_INDEX } } ) Return (BUF0) diff --git a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl index 8d36649..f54f886 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl @@ -35,10 +35,8 @@ AddressingMode7Bit, /* AddressingMode */ "\\_SB.I2C1", /* ResourceSource */ ) - Interrupt (ResourceConsumer, Level, ActiveLow) - { - BOARD_TOUCH_IRQ - } + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_TOUCH_GPIO_INDEX } }) Return (BUF0) } diff --git a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl index 024e6f1..f0db3a3 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl @@ -78,10 +78,8 @@ AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C1", /* ResourceSource */ ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCH_IRQ - } + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_TOUCH_GPIO_INDEX } }) Return (BUF0) } diff --git a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl index da2cf7a..96ec3db 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl @@ -33,10 +33,8 @@ AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C6", // ResourceSource ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - 183 - } + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } }) Method (_STA) diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h index 883f9b9..9d8cd25 100644 --- a/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h @@ -30,8 +30,6 @@ * GPSE_SIZE = 86 */ -#define BOARD_TOUCH_IRQ 184 - /* KBD: Gpio index in N bank */ #define BOARD_I8042_GPIO_INDEX 17 /* SCI: Gpio index in N bank */ diff --git a/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h b/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h index 4a79806..7702ebe 100644 --- a/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/kefka/include/variant/onboard.h @@ -30,8 +30,6 @@ * GPSE_SIZE = 86 */ -#define BOARD_TOUCH_IRQ 184 - /* KBD: Gpio index in N bank */ #define BOARD_I8042_GPIO_INDEX 17 /* Audio: Gpio index in SW bank */ diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h b/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h index 19c3bc3..4ff771c 100644 --- a/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h @@ -30,8 +30,6 @@ * GPSE_SIZE = 86 */ -#define BOARD_TOUCH_IRQ 184 - /* DPTF */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h b/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h index 2854ee9..55affff 100644 --- a/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/relm/include/variant/onboard.h @@ -30,8 +30,6 @@ * GPSE_SIZE = 86 */ -#define BOARD_TOUCH_IRQ 184 - /* KBD: Gpio index in N bank */ #define BOARD_I8042_GPIO_INDEX 17 /* Audio: Gpio index in SW bank */ diff --git a/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h b/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h index 948d9b9..10ec6be 100644 --- a/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/setzer/include/variant/onboard.h @@ -30,8 +30,6 @@ * GPSE_SIZE = 86 */ -#define BOARD_TOUCH_IRQ 184 - /* KBD: Gpio index in N bank */ #define BOARD_I8042_GPIO_INDEX 17 /* Audio: Gpio index in SW bank */ diff --git a/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h b/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h index e5b503f4..3b8b5b4 100644 --- a/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/ultima/include/variant/onboard.h @@ -30,8 +30,6 @@ * GPSE_SIZE = 86 */ -#define BOARD_TOUCH_IRQ 184 - /* DPTF */ #define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 90 diff --git a/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h b/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h index 5a610e2..4584815 100644 --- a/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h +++ b/src/mainboard/google/cyan/variants/wizpig/include/variant/onboard.h @@ -30,8 +30,6 @@ * GPSE_SIZE = 86 */ -#define BOARD_TOUCH_IRQ 184 - /* KBD: Gpio index in N bank */ #define BOARD_I8042_GPIO_INDEX 17 /* Audio: Gpio index in SW bank */ -- To view, visit https://review.coreboot.org/27758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iecfb45be433249d274532eb746588483fedb3f52 Gerrit-Change-Number: 27758 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void
by Philipp Deppenwiese (Code Review) 31 Jul '18

31 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27757 ) Change subject: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void ...................................................................... security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void Change f849972 (security/vboot: Enable TCPA log extension) enabled support for adding TCPA log to CBMEM. However, if CBMEM is not online, this function doesn't do anything and returns early. This condition is not really a valid error condition as it depends on when the call to tcpa_log_add_table_entry is made. Since tcpa_log_add_table_entry returns -1 when cbmem is not online, tpm_extend_pcr prints an error message with prefix "ERROR:". This can confuse any scripts trying to catch errors in boot flow. This CL makes the following changes: 1. Removes the print in tpm_extend_pcr since tcpa_log_add_table_entry already prints out appropriate ERROR messages in case of failure to add log entry. 2. Since the return value of tcpa_log_add_table_entry is not used anymore, return type for tcpa_log_add_table_entry is changed to void. BUG=b:112030232 Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/27757 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Justin TerAvest <teravest(a)chromium.org> --- M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c 3 files changed, 10 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Justin TerAvest: Looks good to me, approved diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 43254c1..94b53b0 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -28,8 +28,9 @@ /** * Add table entry for cbmem TCPA log. */ -int tcpa_log_add_table_entry(const char *name, const uint32_t pcr, - const uint8_t *digest, const size_t digest_length); +void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, + const uint8_t *digest, + const size_t digest_length); /** * Ask vboot for a digest and extend a TPM PCR with it. diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 6091dfe..8ec4c6d 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -44,24 +44,24 @@ printk(BIOS_DEBUG, "TCPA log created at %p\n", tclt); } -int tcpa_log_add_table_entry(const char *name, const uint32_t pcr, - const uint8_t *digest, const size_t digest_length) +void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, + const uint8_t *digest, const size_t digest_length) { MAYBE_STATIC struct tcpa_table *tclt = NULL; struct tcpa_entry *tce; if (!cbmem_possibly_online()) - return -1; + return; tclt = cbmem_find(CBMEM_ID_TCPA_LOG); if (!tclt) { printk(BIOS_ERR, "ERROR: No TCPA log table found\n"); - return -1; + return; } if (tclt->num_entries == tclt->max_entries) { printk(BIOS_WARNING, "ERROR: TCPA log table is full\n"); - return -1; + return; } tce = &tclt->entries[tclt->num_entries++]; @@ -70,6 +70,4 @@ tce->pcr = pcr; memcpy(tce->digest, digest, digest_length); tce->digest_length = digest_length; - - return 0; } diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 48b6219..950e930 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -190,9 +190,7 @@ if (result != TPM_SUCCESS) return result; - result = tcpa_log_add_table_entry(name, pcr, digest, digest_len); - if (result != 0) - printk(BIOS_ERR, "ERROR: Couldn't create TCPA log entry\n"); + tcpa_log_add_table_entry(name, pcr, digest, digest_len); - return 0; + return TPM_SUCCESS; } -- To view, visit https://review.coreboot.org/27757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Gerrit-Change-Number: 27757 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void
by Philipp Deppenwiese (Code Review) 31 Jul '18

31 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27757 ) Change subject: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void ...................................................................... Patch Set 1: Ah I see if the verstage is loaded from the bootblock. -- To view, visit https://review.coreboot.org/27757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Gerrit-Change-Number: 27757 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 21:58:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void
by Philipp Deppenwiese (Code Review) 31 Jul '18

31 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27757 ) Change subject: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void ...................................................................... Patch Set 1: @Furquan Do we conditions where measurements are done but cbmem isn't available ? -- To view, visit https://review.coreboot.org/27757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Gerrit-Change-Number: 27757 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 21:54:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void
by Philipp Deppenwiese (Code Review) 31 Jul '18

31 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27757 ) Change subject: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Gerrit-Change-Number: 27757 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 21:53:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit July 2018