Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27761
Change subject: google/cyan: Mask Audio IRQ on boot ......................................................................
google/cyan: Mask Audio IRQ on boot
Adapted from chromium commit cf18ab6 [Strago: mask Audio IRQ on boot]
Do not start with audio interrupt unmasked; this causes interrupt storms on newer kernels that no longer mask all interrupts when initializing Cherryview pincontrol driver.
TEST=Boot various cyan boards with kernels 3.18 and 4.14; verify everything works.
Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43 Original-Signed-off-by: Dmitry Torokhov dtor@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/894688 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org
Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/google/cyan/variants/celes/gpio.c M src/mainboard/google/cyan/variants/cyan/gpio.c M src/mainboard/google/cyan/variants/edgar/gpio.c M src/mainboard/google/cyan/variants/kefka/gpio.c M src/mainboard/google/cyan/variants/reks/gpio.c M src/mainboard/google/cyan/variants/relm/gpio.c M src/mainboard/google/cyan/variants/setzer/gpio.c M src/mainboard/google/cyan/variants/terra/gpio.c M src/mainboard/google/cyan/variants/ultima/gpio.c M src/mainboard/google/cyan/variants/wizpig/gpio.c 10 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/27761/1
diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c index 10ca3b0..d011428 100644 --- a/src/mainboard/google/cyan/variants/celes/gpio.c +++ b/src/mainboard/google/cyan/variants/celes/gpio.c @@ -140,7 +140,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c index 62fcb5e..4139f76 100644 --- a/src/mainboard/google/cyan/variants/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -138,7 +138,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c index 97e2dd1..d9d2648 100644 --- a/src/mainboard/google/cyan/variants/edgar/gpio.c +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -137,7 +137,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c index 8340f1a..76549ba4 100644 --- a/src/mainboard/google/cyan/variants/kefka/gpio.c +++ b/src/mainboard/google/cyan/variants/kefka/gpio.c @@ -137,7 +137,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c index 74792bd..1a9e540 100644 --- a/src/mainboard/google/cyan/variants/reks/gpio.c +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -139,7 +139,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c index 6b75a84..6c1dbdc 100644 --- a/src/mainboard/google/cyan/variants/relm/gpio.c +++ b/src/mainboard/google/cyan/variants/relm/gpio.c @@ -140,7 +140,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c index a1564c1..df1bff1 100644 --- a/src/mainboard/google/cyan/variants/setzer/gpio.c +++ b/src/mainboard/google/cyan/variants/setzer/gpio.c @@ -138,7 +138,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c index 3f5c19d..8328edd 100644 --- a/src/mainboard/google/cyan/variants/terra/gpio.c +++ b/src/mainboard/google/cyan/variants/terra/gpio.c @@ -136,7 +136,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c index 4e4f0f6..c6875b4 100644 --- a/src/mainboard/google/cyan/variants/ultima/gpio.c +++ b/src/mainboard/google/cyan/variants/ultima/gpio.c @@ -139,7 +139,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c index cadaf02..3611439 100644 --- a/src/mainboard/google/cyan/variants/wizpig/gpio.c +++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c @@ -138,7 +138,7 @@ Native_M1, /* 92 GP_SSP_2_CLK */ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + GPI(trig_edge_both, L1, P_5K_H, 0, en_edge_detect, NA, NA), /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ Native_M1, /* 96 GP_SSP_2_FS */ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */
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Matt DeVillier (Code Review)