coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sandybridge/raminit_common: use macro for execute command queue register
by Felix Held (Code Review) 31 Jul '18

31 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27750 Change subject: sandybridge/raminit_common: use macro for execute command queue register ...................................................................... sandybridge/raminit_common: use macro for execute command queue register This patch doesn't change the hash of a timeless build. Change-Id: I5d329f65be0eee741fd330c0926881ff4f956624 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 78 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27750/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4de83fb..ca135b4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -62,9 +62,11 @@ * DEFAULT_MCHBAR + 0x4284 + 0x400 * channel: execute command queue * Starts to execute all queued commands * Bit 0 : start DRAM command execution - * Bit 16-20: (number of queued commands - 1) * 4 + * Bit 18-19 : number of queued commands - 1 */ +#define RUN_QUEUE_4284(x) ((((x) - 1) << 18) | 1) // 0 <= x < 4 + static void sfence(void) { asm volatile ("sfence"); @@ -643,12 +645,12 @@ /* DRAM command ZQCS */ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; MCHBAR32(0x4230 + 0x400 * channel) = 0x80c01; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0x400001; + // execute command queue - why is bit 22 set here?! + MCHBAR32(0x4284 + 0x400 * channel) = (1 << 22) | RUN_QUEUE_4284(1); + wait_428c(channel); } @@ -754,7 +756,9 @@ MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | (reg << 20) | val | 0x60000; MCHBAR32(0x4218 + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0x80001; + + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(3); } static u32 make_mr0(ramctr_timing * ctrl, u8 rank) @@ -920,7 +924,9 @@ MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; - MCHBAR32(0x4284 + 0x400 * channel) = 0x1; + + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); // Drain wait_428c(channel); @@ -1109,7 +1115,8 @@ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000; MCHBAR32(0x421c + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1368,7 +1375,9 @@ MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; MCHBAR32(0x4210 + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 1; + + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); MCHBAR32(0x3400) = (slotrank << 2) | 0x8001; @@ -1493,7 +1502,8 @@ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 8; MCHBAR32(0x421c + 0x400 * channel) = 0x3e0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); @@ -1525,7 +1535,10 @@ MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; MCHBAR32(0x421c + 0x400 * channel) = 0x240; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + wait_428c(channel); } @@ -1542,7 +1555,9 @@ MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; MCHBAR32(0x4210 + 0x400 * channel) = 0x240; - MCHBAR32(0x4284 + 0x400 * channel) = 1; + + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); for (timC = 0; timC <= MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. @@ -1661,7 +1676,9 @@ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000; MCHBAR32(0x421c + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -1713,7 +1730,9 @@ (slotrank << 24) | 0x360000; MCHBAR32(0x421c + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + wait_428c(channel); } } @@ -1740,7 +1759,9 @@ MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 4; MCHBAR32(0x4214 + 0x400 * channel) = 0; - MCHBAR32(0x400 * channel + 0x4284) = 0x40001; + // execute command queue + MCHBAR32(0x400 * channel + 0x4284) = RUN_QUEUE_4284(2); + wait_428c(channel); /* disable DQs on this slotrank */ @@ -1859,7 +1880,8 @@ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x8; MCHBAR32(0x421c + 0x400 * channel) = 0x3e0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); @@ -1886,7 +1908,9 @@ MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008; MCHBAR32(0x4218 + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0x80001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(3); + wait_428c(channel); FOR_ALL_LANES { u64 res = MCHBAR32(lane_registers[lane] + @@ -1919,12 +1943,12 @@ /* DRAM command ACT */ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; - MCHBAR32(0x4284 + 0x400 * channel) = 1; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + wait_428c(channel); } @@ -2003,7 +2027,9 @@ MCHBAR32(0x4200 + 0x400 * channel) = 0x60000; MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; - MCHBAR32(0x4284 + 0x400 * channel) = 1; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + wait_428c(channel); } @@ -2096,7 +2122,9 @@ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; MCHBAR32(0x421c + 0x400 * channel) = 0x240; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + wait_428c(channel); FOR_ALL_LANES { u32 r32 = MCHBAR32(0x4340 + 4 * lane + 0x400 * channel); @@ -2159,12 +2187,12 @@ /* DRAM command ZQCS */ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; - MCHBAR32(0x4284 + 0x400 * channel) = 1; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + wait_428c(channel); MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); } @@ -2180,12 +2208,12 @@ /* DRAM command ZQCS */ MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; - MCHBAR32(0x4284 + 0x400 * channel) = 1; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(1); + wait_428c(channel); } @@ -2373,7 +2401,8 @@ (slotrank << 24) | 0x360000; MCHBAR32(0x421c + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); @@ -2467,7 +2496,9 @@ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000; MCHBAR32(0x421c + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); wait_428c(channel); } @@ -2522,7 +2553,9 @@ (slotrank << 24) | 0x360000; MCHBAR32(0x421c + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + wait_428c(channel); } @@ -2655,7 +2688,10 @@ (slotrank << 24) | 0x60400; MCHBAR32(0x421c + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = + RUN_QUEUE_4284(4); + wait_428c(channel); FOR_ALL_LANES { volatile u32 tmp; @@ -2774,7 +2810,9 @@ MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; MCHBAR32(0x421c + 0x400 * channel) = 0; - MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; + // execute command queue + MCHBAR32(0x4284 + 0x400 * channel) = RUN_QUEUE_4284(4); + wait_428c(channel); } @@ -2940,31 +2978,38 @@ MCHBAR32(0x4d40 + 4 * lane) = 0; } wait_428c(channel); + /* DRAM command ACT */ MCHBAR32(0x4220 + (channel << 10)) = 0x0001f006; MCHBAR32(0x4230 + (channel << 10)) = 0x0028a004; MCHBAR32(0x4200 + (channel << 10)) = 0x00060000 | (slotrank << 24); MCHBAR32(0x4210 + (channel << 10)) = 0x00000244; + /* DRAM command WR */ MCHBAR32(0x4224 + (channel << 10)) = 0x0001f201; MCHBAR32(0x4234 + (channel << 10)) = 0x08281064; MCHBAR32(0x4204 + (channel << 10)) = 0x00000000 | (slotrank << 24); MCHBAR32(0x4214 + (channel << 10)) = 0x00000242; + /* DRAM command RD */ MCHBAR32(0x4228 + (channel << 10)) = 0x0001f105; MCHBAR32(0x4238 + (channel << 10)) = 0x04281064; MCHBAR32(0x4208 + (channel << 10)) = 0x00000000 | (slotrank << 24); MCHBAR32(0x4218 + (channel << 10)) = 0x00000242; + /* DRAM command PRE */ MCHBAR32(0x422c + (channel << 10)) = 0x0001f002; MCHBAR32(0x423c + (channel << 10)) = 0x00280c01; MCHBAR32(0x420c + (channel << 10)) = 0x00060400 | (slotrank << 24); MCHBAR32(0x421c + (channel << 10)) = 0x00000240; - MCHBAR32(0x4284 + (channel << 10)) = 0x000c0001; + + // execute command queue + MCHBAR32(0x4284 + (channel << 10)) = RUN_QUEUE_4284(4); + wait_428c(channel); FOR_ALL_LANES if (MCHBAR32(0x4340 + (channel << 10) + 4 * lane)) { -- To view, visit https://review.coreboot.org/27750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5d329f65be0eee741fd330c0926881ff4f956624 Gerrit-Change-Number: 27750 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

1 0

Change in coreboot[master]: payload/LinuxBoot: Fix compilation and clean target
by Philipp Deppenwiese (Code Review) 31 Jul '18

31 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27745 ) Change subject: payload/LinuxBoot: Fix compilation and clean target ...................................................................... payload/LinuxBoot: Fix compilation and clean target * Update kernel version * Add kernel directory removal during clean target * Add x86 and x86_64 default configs Change-Id: I6793bffd2c537a0e9fe7c07abbea99b28defb52e Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/27745 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Makefile A payloads/external/LinuxBoot/x86/defconfig A payloads/external/LinuxBoot/x86_64/defconfig 4 files changed, 329 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved Ronald G. Minnich: Looks good to me, approved diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 24d44cf..14ee895 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -53,10 +53,17 @@ bool "4.15.3" help Stable kernel version + +config LINUXBOOT_KERNEL_LATEST + bool "4.17.11" + help + Latest kernel version + endchoice config LINUXBOOT_KERNEL_VERSION string + default "4.17.11" if LINUXBOOT_KERNEL_LATEST default "4.15.3" if LINUXBOOT_KERNEL_STABLE config LINUXBOOT_KERNEL_CONFIGFILE diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 651e982..f259373 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -21,23 +21,23 @@ XGCCPATH?=$(PWD)/util/crossgcc/xgcc/bin ifeq ($(CONFIG_LINUXBOOT_ARCH),386) -CROSS_COMPILE?=$(XGCCPATH)/i386-linux- +LINUXBOOT_COMPILE?=$(XGCCPATH)/i386-linux- ARCH?=x86 else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64) -CROSS_COMPILE?=$(XGCCPATH)/x86_64-linux- +LINUXBOOT_COMPILE?=$(XGCCPATH)/x86_64-linux- ARCH?=x86_64 else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64) -CROSS_COMPILE?=$(XGCCPATH)/aarch64-linux- +LINUXBOOT_COMPILE?=$(XGCCPATH)/aarch64-linux- ARCH?=arm64 endif -OBJCOPY:=$(CROSS_COMPILE)objcopy +OBJCOPY:=$(LINUXBOOT_COMPILE)objcopy all: payload toolchain: - if [[ ! -x "$(CROSS_COMPILE)gcc" ]]; then \ - echo "Toolchain '$(CROSS_COMPILE)*' is missing."; \ + if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \ + echo "Toolchain '$(LINUXBOOT_COMPILE)*' is missing."; \ exit 1; \ fi @@ -67,8 +67,8 @@ $(kernel_dir)/vmlinux: config toolchain endif echo " MAKE Kernel $(CONFIG_LINUXBOOT_KERNEL_VERSION)" - $(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH) - $(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH) + $(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH) + $(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH) ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64)) $(project_dir)/kernel-image: $(kernel_dir)/arch/x86/boot/bzImage @@ -99,7 +99,7 @@ payload: $(project_dir)/kernel-image $(project_dir)/initramfs.cpio.xz clean: - if [ -d "$(kernel_dir)" ]; then make -C $(kernel_dir) clean; fi + if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi rm -f $(project_dir)/initramfs.cpio.xz distclean: diff --git a/payloads/external/LinuxBoot/x86/defconfig b/payloads/external/LinuxBoot/x86/defconfig new file mode 100644 index 0000000..6c20c14 --- /dev/null +++ b/payloads/external/LinuxBoot/x86/defconfig @@ -0,0 +1,147 @@ +# CONFIG_64BIT is not set +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_XZ=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_USELIB is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_MULTIUSER is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_BUG is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_BASE_FULL is not set +# CONFIG_AIO is not set +# CONFIG_KALLSYMS is not set +CONFIG_BPF_SYSCALL=y +CONFIG_USERFAULTFD=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_GCC_PLUGINS=y +CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y +CONFIG_GCC_PLUGIN_STRUCTLEAK=y +CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y +CONFIG_GCC_PLUGIN_RANDSTRUCT=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_MMAP_RND_BITS=16 +CONFIG_REFCOUNT_FULL=y +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_ZONE_DMA is not set +# CONFIG_X86_FAST_FEATURE_TESTS is not set +# CONFIG_X86_MPPARSE is not set +# CONFIG_X86_EXTENDED_PLATFORM is not set +# CONFIG_SCHED_OMIT_FRAME_POINTER is not set +# CONFIG_DMI is not set +CONFIG_PREEMPT=y +# CONFIG_X86_MCE is not set +# CONFIG_MICROCODE is not set +CONFIG_SPARSEMEM_MANUAL=y +# CONFIG_COMPACTION is not set +# CONFIG_MTRR is not set +# CONFIG_X86_INTEL_UMIP is not set +CONFIG_KEXEC=y +# CONFIG_RELOCATABLE is not set +# CONFIG_MODIFY_LDT_SYSCALL is not set +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_ACPI_REV_OVERRIDE_POSSIBLE is not set +# CONFIG_ACPI_AC is not set +# CONFIG_ACPI_BATTERY is not set +# CONFIG_ACPI_BUTTON is not set +# CONFIG_ACPI_FAN is not set +# CONFIG_ACPI_PROCESSOR is not set +# CONFIG_ACPI_TABLE_UPGRADE is not set +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y +# CONFIG_CPU_IDLE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEASPM_POWER_SUPERSAVE=y +CONFIG_PCI_MSI=y +# CONFIG_BINFMT_SCRIPT is not set +# CONFIG_COREDUMP is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_PNP_DEBUG_MESSAGES is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_HW_RANDOM_TIMERIOMEM=y +# CONFIG_HW_RANDOM_AMD is not set +# CONFIG_HW_RANDOM_VIA is not set +# CONFIG_DEVPORT is not set +CONFIG_I2C=y +CONFIG_POWER_SUPPLY=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_USB_SUPPORT is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_GOOGLE_FIRMWARE=y +CONFIG_GOOGLE_COREBOOT_TABLE_ACPI=y +CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y +CONFIG_GOOGLE_VPD=y +CONFIG_EXT4_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_TMPFS=y +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_ZLIB is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_NETWORK_FILESYSTEMS is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y +# CONFIG_X86_VERBOSE_BOOTUP is not set +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DOUBLEFAULT is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_X86_DEBUG_FPU is not set +CONFIG_UNWINDER_GUESS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_HW is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/payloads/external/LinuxBoot/x86_64/defconfig b/payloads/external/LinuxBoot/x86_64/defconfig new file mode 100644 index 0000000..71c5d77 --- /dev/null +++ b/payloads/external/LinuxBoot/x86_64/defconfig @@ -0,0 +1,166 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_XZ=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_MULTIUSER is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_BUG is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_BASE_FULL is not set +# CONFIG_AIO is not set +# CONFIG_KALLSYMS is not set +CONFIG_BPF_SYSCALL=y +CONFIG_USERFAULTFD=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_GCC_PLUGINS=y +CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y +CONFIG_GCC_PLUGIN_STRUCTLEAK=y +CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y +CONFIG_GCC_PLUGIN_RANDSTRUCT=y +# CONFIG_VMAP_STACK is not set +CONFIG_REFCOUNT_FULL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_ZONE_DMA is not set +# CONFIG_X86_MPPARSE is not set +# CONFIG_X86_EXTENDED_PLATFORM is not set +CONFIG_IOSF_MBI=y +# CONFIG_SCHED_OMIT_FRAME_POINTER is not set +# CONFIG_DMI is not set +CONFIG_PREEMPT=y +# CONFIG_X86_MCE is not set +# CONFIG_MICROCODE is not set +CONFIG_X86_MSR=y +CONFIG_X86_CPUID=y +# CONFIG_SPARSEMEM_VMEMMAP is not set +# CONFIG_COMPACTION is not set +# CONFIG_MTRR is not set +# CONFIG_X86_INTEL_UMIP is not set +# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set +CONFIG_KEXEC=y +# CONFIG_RELOCATABLE is not set +# CONFIG_MODIFY_LDT_SYSCALL is not set +# CONFIG_SUSPEND is not set +# CONFIG_ACPI_REV_OVERRIDE_POSSIBLE is not set +# CONFIG_ACPI_AC is not set +# CONFIG_ACPI_BATTERY is not set +CONFIG_ACPI_VIDEO=y +# CONFIG_ACPI_FAN is not set +# CONFIG_ACPI_PROCESSOR is not set +# CONFIG_ACPI_TABLE_UPGRADE is not set +# CONFIG_X86_PM_TIMER is not set +# CONFIG_CPU_IDLE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEASPM_POWER_SUPERSAVE=y +CONFIG_PCI_MSI=y +# CONFIG_ISA_DMA_API is not set +# CONFIG_BINFMT_SCRIPT is not set +# CONFIG_COREDUMP is not set +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_PNP_DEBUG_MESSAGES is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_HW_RANDOM_TIMERIOMEM=y +# CONFIG_HW_RANDOM_AMD is not set +# CONFIG_HW_RANDOM_VIA is not set +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS=y +# CONFIG_DEVPORT is not set +CONFIG_I2C=y +CONFIG_POWER_SUPPLY=y +# CONFIG_HWMON is not set +# CONFIG_VGA_ARB is not set +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_FOREIGN_ENDIAN=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_USB_SUPPORT is not set +CONFIG_SYNC_FILE=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_GOOGLE_FIRMWARE=y +CONFIG_GOOGLE_COREBOOT_TABLE_ACPI=y +CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y +CONFIG_GOOGLE_VPD=y +CONFIG_EXT4_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +# CONFIG_X86_VERBOSE_BOOTUP is not set +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DOUBLEFAULT is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_X86_DEBUG_FPU is not set +CONFIG_UNWINDER_GUESS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_SHA256_SSSE3=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_HW is not set +# CONFIG_VIRTUALIZATION is not set -- To view, visit https://review.coreboot.org/27745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I6793bffd2c537a0e9fe7c07abbea99b28defb52e Gerrit-Change-Number: 27745 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/pcengines/alix/romstage.c: clean up the transition to RAM
by Michał Żygowski (Code Review) 31 Jul '18

31 Jul '18

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/27749 Change subject: mb/pcengines/alix/romstage.c: clean up the transition to RAM ...................................................................... mb/pcengines/alix/romstage.c: clean up the transition to RAM Clean up the code which implied that return does not work in mainboard_romstage_entry. Doing a wbinvd when CR0 NW and CD bits are set caused the loss of return adress from the function, because it behaved like invd. Remove redundant stack self-copying code and invalidate cache in cache_as_ram.inc as it is sufficient to switch to RAM. Change-Id: I21f2341091d49d105026a12022c52d811d71feeb Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/cpu/amd/geode_lx/cache_as_ram.inc M src/mainboard/pcengines/alix1c/romstage.c M src/mainboard/pcengines/alix2d/romstage.c 3 files changed, 4 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27749/1 diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index 8250d72..1569cc3 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -183,25 +183,11 @@ /* Call romstage.c main function */ call mainboard_romstage_entry -.global done_cache_as_ram_main -done_cache_as_ram_main: + /* Switch from Cache as RAM to real RAM. */ + /* Invalidate the cache since there is nothing on the stack */ + /* Then re-enable the cache */ + invd - /* We now run over the stack-in-cache, - * copying it back to itself to invalidate the cache */ - - push %edi - mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx - push %esi - mov $(CONFIG_DCACHE_RAM_BASE),%edi - mov %edi,%esi - cld - rep movsl %ds:(%esi),%es:(%edi) - pop %esi - pop %edi - - /* Clear the cache out to RAM */ - wbinvd - /* re-enable the cache */ movl %cr0, %eax xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ movl %eax, %cr0 diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 8fe2dc0..e59873f 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -115,35 +115,5 @@ sdram_initialize(1, memctrl); - /* Switch from Cache as RAM to real RAM. - * - * There are two ways we could think about this. - * - * 1. If we are using the romstage.inc ROMCC way, the stack is - * going to be re-setup in the code following this code. Just - * wbinvd the stack to clear the cache tags. We don't care - * where the stack used to be. - * - * 2. This file is built as a normal .c -> .o and linked in - * etc. The stack might be used to return etc. That means we - * care about what is in the stack. If we are smart we set - * the CAR stack to the same location as the rest of - * coreboot. If that is the case we can just do a wbinvd. - * The stack will be written into real RAM that is now setup - * and we continue like nothing happened. If the stack is - * located somewhere other than where LB would like it, you - * need to write some code to do a copy from cache to RAM - * - * We use method 1 on Norwich and on this board too. - */ post_code(0x02); - printk(BIOS_ERR, "POST 02\n"); - __asm__("wbinvd\n"); - printk(BIOS_ERR, "Past wbinvd\n"); - - /* We are finding the return does not work on this board. Explicitly - * call the label that is after the call to us. This is gross, but - * sometimes at this level it is the only way out. - */ - done_cache_as_ram_main(); } diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index da3913d..b05140c 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -138,35 +138,5 @@ sdram_initialize(1, memctrl); - /* Switch from Cache as RAM to real RAM. - * - * There are two ways we could think about this. - * - * 1. If we are using the romstage.inc ROMCC way, the stack is - * going to be re-setup in the code following this code. Just - * wbinvd the stack to clear the cache tags. We don't care - * where the stack used to be. - * - * 2. This file is built as a normal .c -> .o and linked in - * etc. The stack might be used to return etc. That means we - * care about what is in the stack. If we are smart we set - * the CAR stack to the same location as the rest of - * coreboot. If that is the case we can just do a wbinvd. - * The stack will be written into real RAM that is now setup - * and we continue like nothing happened. If the stack is - * located somewhere other than where LB would like it, you - * need to write some code to do a copy from cache to RAM - * - * We use method 1 on Norwich and on this board too. - */ post_code(0x02); - printk(BIOS_ERR, "POST 02\n"); - __asm__("wbinvd\n"); - printk(BIOS_ERR, "Past wbinvd\n"); - - /* We are finding the return does not work on this board. Explicitly - * call the label that is after the call to us. This is gross, but - * sometimes at this level it is the only way out. - */ - done_cache_as_ram_main(); } -- To view, visit https://review.coreboot.org/27749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I21f2341091d49d105026a12022c52d811d71feeb Gerrit-Change-Number: 27749 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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Change in coreboot[master]: sb/intel/i82801gx: Select INTEL_HAS_TOP_SWAP
by Arthur Heymans (Code Review) 31 Jul '18

31 Jul '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27748 Change subject: sb/intel/i82801gx: Select INTEL_HAS_TOP_SWAP ...................................................................... sb/intel/i82801gx: Select INTEL_HAS_TOP_SWAP The i82801gx southbridge has the ability to swap the two top 64K ranges by flipping the BUC.TS bit (RCBA[3414] bit0) This effectively means it is possible to run another bootblock located at top_of_flash - 64K. This allows coreboot to build roms with a bootblock at the top swap offset by selecting CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK. Change-Id: Id96e10aea3e5fd955d45287134eb8643be414de9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27748/1 diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 7e48848..f06ba42 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -28,6 +28,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select INTEL_HAS_TOP_SWAP if SOUTHBRIDGE_INTEL_I82801GX @@ -43,4 +44,8 @@ hex default 0x80 +config INTEL_TOP_SWAP_SIZE + hex + default 0x10000 + endif -- To view, visit https://review.coreboot.org/27748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id96e10aea3e5fd955d45287134eb8643be414de9 Gerrit-Change-Number: 27748 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/google/octopus: add lpddr4 skus for new memory sources
by Nick Chen (Code Review) 31 Jul '18

31 Jul '18

Nick Chen has uploaded this change for review. ( https://review.coreboot.org/27747 Change subject: mb/google/octopus: add lpddr4 skus for new memory sources ...................................................................... mb/google/octopus: add lpddr4 skus for new memory sources Add lpddr4 skus for new memory sources K4F6E3S4HM-MGCJ and MT53E512M32D2NP-046. BUG=b:111964159 BRANCH=master TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Id39a332998b28262e5aa45822078f3c4087f163f Signed-off-by: nickchen <nickchen(a)ami.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/baseboard/memory.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/27747/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index 4c1d359..452d3a9 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -126,6 +126,20 @@ .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "H9HCNNN8KUMLHR", }, + /* K4F6E3S4HM-MGCJ - both logical channels */ + [6] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_16Gb_DENSITY, + .ch1_rank_density = LP4_16Gb_DENSITY, + .part_num = "K4F6E3S4HM-MGCJ", + }, + /* MT53E512M32D2NP-046 - both logical channels */ + [7] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_16Gb_DENSITY, + .ch1_rank_density = LP4_16Gb_DENSITY, + .part_num = "MT53E512M32D2NP", + }, }; static const struct lpddr4_cfg lp4cfg = { -- To view, visit https://review.coreboot.org/27747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id39a332998b28262e5aa45822078f3c4087f163f Gerrit-Change-Number: 27747 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Chen <nickchen(a)ami.corp-partner.google.com>

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Change in coreboot[master]: soc/intel/apollolake: Force USB-C into host mode
by build bot (Jenkins) (Code Review) 30 Jul '18

30 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27746 ) Change subject: soc/intel/apollolake: Force USB-C into host mode ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/27746/2/src/soc/intel/apollolake/chip.c File src/soc/intel/apollolake/chip.c: https://review.coreboot.org/#/c/27746/2/src/soc/intel/apollolake/chip.c@676 PS2, Line 676: if (IS_ENABLED(CONFIG_SOC_INTEL_GLK) && vboot_can_enable_udc()) that open brace { should be on the previous line https://review.coreboot.org/#/c/27746/2/src/soc/intel/apollolake/chip.c@698 PS2, Line 698: while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/27746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Gerrit-Change-Number: 27746 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Jul 2018 21:48:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/apollolake: Force USB-C into host mode
by John Zhao (Code Review) 30 Jul '18

30 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27746 to look at the new patch set (#2). Change subject: soc/intel/apollolake: Force USB-C into host mode ...................................................................... soc/intel/apollolake: Force USB-C into host mode When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures USB-C as device mode. Force USB-C into host mode. BUG=b:111623911 TEST=Verified that USB-C being host mode once USB OTG is set. Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/27746/2 -- To view, visit https://review.coreboot.org/27746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Gerrit-Change-Number: 27746 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: payload/LinuxBoot: Fix compilation and clean target
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27745 to look at the new patch set (#2). Change subject: payload/LinuxBoot: Fix compilation and clean target ...................................................................... payload/LinuxBoot: Fix compilation and clean target * Update kernel version * Add kernel directory removal during clean target * Add x86 and x86_64 default configs Change-Id: I6793bffd2c537a0e9fe7c07abbea99b28defb52e Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Makefile A payloads/external/LinuxBoot/x86/defconfig A payloads/external/LinuxBoot/x86_64/defconfig 4 files changed, 329 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27745/2 -- To view, visit https://review.coreboot.org/27745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6793bffd2c537a0e9fe7c07abbea99b28defb52e Gerrit-Change-Number: 27745 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/intel/apollolake: Force USB-C into host mode
by build bot (Jenkins) (Code Review) 30 Jul '18

30 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27746 ) Change subject: soc/intel/apollolake: Force USB-C into host mode ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/27746/1/src/soc/intel/apollolake/chip.c File src/soc/intel/apollolake/chip.c: https://review.coreboot.org/#/c/27746/1/src/soc/intel/apollolake/chip.c@673 PS1, Line 673: * When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures line over 80 characters https://review.coreboot.org/#/c/27746/1/src/soc/intel/apollolake/chip.c@676 PS1, Line 676: if (IS_ENABLED(CONFIG_SOC_INTEL_GLK) && vboot_can_enable_udc()) { line over 80 characters https://review.coreboot.org/#/c/27746/1/src/soc/intel/apollolake/chip.c@697 PS1, Line 697: while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { line over 80 characters -- To view, visit https://review.coreboot.org/27746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Gerrit-Change-Number: 27746 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Jul 2018 21:16:04 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/intel/apollolake: Force USB-C into host mode
by John Zhao (Code Review) 30 Jul '18

30 Jul '18

John Zhao has uploaded this change for review. ( https://review.coreboot.org/27746 Change subject: soc/intel/apollolake: Force USB-C into host mode ...................................................................... soc/intel/apollolake: Force USB-C into host mode When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures USB-C as device mode. Force USB-C into host mode. BUG=b:111623911 TEST=Verified that USB-C being host mode once USB OTG is set. Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/27746/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 081bba3..347a8e1 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -49,6 +49,8 @@ #include <soc/cpu.h> #include <soc/pm.h> #include <soc/systemagent.h> +#include <security/vboot/vboot_common.h> +#include <timer.h> #include "chip.h" @@ -666,6 +668,42 @@ * security. */ drop_privilege_all(); + + /* + * When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures + * USB-C as device mode. Force USB-C into host mode. + */ + if (IS_ENABLED(CONFIG_SOC_INTEL_GLK) && vboot_can_enable_udc()) { + uint32_t *cfg0; + uint32_t *cfg1; + const struct resource *res; + uint32_t reg; + struct stopwatch sw; + struct device *xhci_dev = PCH_DEV_XHCI; + + printk(BIOS_INFO, "Putting xHCI port 0 into host mode.\n"); + res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); + cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); + cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); + reg = read32(cfg0); + if (reg && SW_IDPIN_EN_MASK) { + reg &= ~SW_IDPIN_MASK; + reg |= SW_IDPIN_HOST; + } + write32(cfg0, reg); + + stopwatch_init_msecs_expire(&sw, 10); + /* Wait for the host mode status bit. */ + while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "Timed out waiting for host mode.\n"); + break; + } + } + + printk(BIOS_INFO, "xHCI port 0 host switch over took %lu ms\n", + stopwatch_duration_msecs(&sw)); + } } } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 61ddeda..508965c 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -33,6 +33,14 @@ #define MAX_PCIE_PORTS 6 #define CLKREQ_DISABLED 0xf +#define DUAL_ROLE_CFG0 0x80d8 +#define SW_IDPIN_EN_MASK (1 << 21) +#define SW_IDPIN_MASK (1 << 20) +#define SW_IDPIN_HOST (0 << 20) +#define DUAL_ROLE_CFG1 0x80dc +#define DRD_MODE_MASK (1 << 29) +#define DRD_MODE_HOST (1 << 29) + enum pnp_settings { PNP_PERF, PNP_POWER, -- To view, visit https://review.coreboot.org/27746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Gerrit-Change-Number: 27746 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com>

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coreboot-gerrit July 2018