coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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877 discussions

Change in coreboot[master]: mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default
by Furquan Shaikh (Code Review) 30 Jul '18

30 Jul '18

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/27661 ) Change subject: mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default ...................................................................... mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means LTE tx power is backoff mode as default. We would set GPP_D21 to high to change LTE tx power to normal mode as default. BUG=None BRANCH=poppy TEST=Verified default LTE tx power mode is normal mode as default Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> Reviewed-on: https://review.coreboot.org/27661 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/nautilus/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Seunghwan Kim: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 8b129d1..75d4ce9 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -395,7 +395,7 @@ /* D16 : ISH_UART0_CTS# ==> LTE3_W_DISABLE# */ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* D21 : SPI1_IO2 ==> LTE3_BODY_SAR */ - PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_CFG_GPO(GPP_D21, 1, DEEP), /* E11 : USB2_OC2# ==> USB2_P2_FAULT# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), }; -- To view, visit https://review.coreboot.org/27661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c Gerrit-Change-Number: 27661 Gerrit-PatchSet: 4 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default
by Seunghwan Kim (Code Review) 30 Jul '18

30 Jul '18

Seunghwan Kim has posted comments on this change. ( https://review.coreboot.org/27661 ) Change subject: mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default ...................................................................... Patch Set 3: > Patch Set 3: Code-Review+2 Can we send it to poppy branch? -- To view, visit https://review.coreboot.org/27661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c Gerrit-Change-Number: 27661 Gerrit-PatchSet: 3 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Jul 2018 05:31:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nami: Enable Slow Slew rate
by Furquan Shaikh (Code Review) 30 Jul '18

30 Jul '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27677 ) Change subject: mb/google/poppy/variant/nami: Enable Slow Slew rate ...................................................................... Patch Set 2: (2 comments) Can you please rebase this on ToT? https://review.coreboot.org/#/c/27677/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/mainboard.c: https://review.coreboot.org/#/c/27677/2/src/mainboard/google/poppy/variants… PS2, Line 90: * space before * https://review.coreboot.org/#/c/27677/2/src/mainboard/google/poppy/variants… PS2, Line 90: * space after * -- To view, visit https://review.coreboot.org/27677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaf3c7ed97696b1d13eb9a2c82e0a8ae09620ede5 Gerrit-Change-Number: 27677 Gerrit-PatchSet: 2 Gerrit-Owner: TH Lin <t.h_lin(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Jul 2018 02:39:21 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/kahlee: Pad SPD serial Number with spaces
by Martin Roth (Code Review) 30 Jul '18

30 Jul '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/27676 ) Change subject: mainboard/google/kahlee: Pad SPD serial Number with spaces ...................................................................... mainboard/google/kahlee: Pad SPD serial Number with spaces All of the other SPDs are padded with spaces to make them use the full size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not, and that seems to be causing problems with some tools. BUG=b:111903749 TEST=Mosys correctly identifies memory on board using that SPD. Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/27676 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz(a)google.com> Reviewed-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kevin Chiu: Looks good to me, approved Daniel Kurtz: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex index 1bcc1f1..3d046a3 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex @@ -20,7 +20,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36 -4E 43 4A 52 2D 56 4B 43 00 00 00 00 00 00 00 00 +4E 43 4A 52 2D 56 4B 43 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/27676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Gerrit-Change-Number: 27676 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/fsp_baytrail: Add VBOOT support
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27728 Change subject: soc/intel/fsp_baytrail: Add VBOOT support ...................................................................... soc/intel/fsp_baytrail: Add VBOOT support * Add vbnv_cmos_failed function to SoC. * Add VBOOT starts in romstage select. Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_baytrail/pmutil.c 3 files changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27728/1 diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 1d7e64a..68084bc 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -47,6 +47,9 @@ # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + config SOC_INTEL_FSP_BAYTRAIL_MD bool default n diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index e01a944..0cf99de 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += ramstage.c ramstage-y += gpio.c romstage-y += gpio.c +romstage-y += pmutil.c ramstage-y += pmutil.c ramstage-y += southcluster.c romstage-y += reset.c diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index 33ecc09..f0b97a6 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -15,18 +15,20 @@ #include <stdint.h> #include <arch/io.h> +#include <cbmem.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pmc.h> +#include <security/vboot/vbnv.h> -#if defined(__SMM__) +#if defined(__SIMPLE_DEVICE__) -static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline pci_devfn_t get_pcu_dev(void) +static inline device_t get_pcu_dev(void) { return pcu_dev; } @@ -358,3 +360,22 @@ write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); } + +int vbnv_cmos_failed(void) +{ + uint32_t gen_pmcon1; + int rtc_fail; + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps != NULL) + gen_pmcon1 = ps->gen_pmcon1; + else + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + + rtc_fail = !!(gen_pmcon1 & RPS); + + if (rtc_fail) + printk(BIOS_DEBUG, "RTC failure.\n"); + + return rtc_fail; +} -- To view, visit https://review.coreboot.org/27728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Gerrit-Change-Number: 27728 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: security/vboot: Enable TCPA log extension
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27727 Change subject: security/vboot: Enable TCPA log extension ...................................................................... security/vboot: Enable TCPA log extension * Implement TCPA log for tspi extend function. * Hook tcpa_log_init into vboot tpm_setup function. Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/security/tpm/tspi.h M src/security/tpm/tspi/tspi.c M src/security/vboot/secdata_tpm.c 3 files changed, 29 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/27727/1 diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 01b2984..2660750 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -33,12 +33,14 @@ /** * Ask vboot for a digest and extend a TPM PCR with it. + * @param name sets additional info where the digest comes from * @param pcr sets the pcr index * @param digest sets the hash to extend into the tpm - * @param out_digest get extended hash + * @param digest_len the length of the digest * @return TPM_SUCCESS on success. If not a tpm error is returned */ -uint32_t tpm_extend_pcr(int pcr, uint8_t *digest, uint8_t *out_digest); +uint32_t tpm_extend_pcr(const char *name, int pcr, uint8_t *digest, + size_t digest_len); /** * Issue a TPM_Clear and reenable/reactivate the TPM. diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 407e1fa..862a286 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -178,13 +178,21 @@ return TPM_SUCCESS; } -uint32_t tpm_extend_pcr(int pcr, uint8_t *digest, uint8_t *out_digest) +uint32_t tpm_extend_pcr(const char *name, int pcr, uint8_t *digest, + size_t digest_len) { + uint32_t result; + if (!digest) return TPM_E_IOERROR; - if (out_digest) - return tlcl_extend(pcr, digest, out_digest); + result = tlcl_extend(pcr, digest, NULL); + if (result != TPM_SUCCESS) + return result; - return tlcl_extend(pcr, digest, NULL); + result = tcpa_log_add_table_entry(name, pcr, digest, digest_len); + if (result != 0) + printk(BIOS_ERR, "ERROR: Couldn't creat TCPA log entry\n"); + + return 0; } diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 57c107b..b443200 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -65,7 +65,7 @@ static uint32_t safe_write(uint32_t index, const void *data, uint32_t length); uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, - enum vb2_pcr_digest which_digest) + enum vb2_pcr_digest which_digest) { uint8_t buffer[VB2_PCR_DIGEST_RECOMMENDED_SIZE]; uint32_t size = sizeof(buffer); @@ -77,7 +77,15 @@ if (size < TPM_PCR_MINIMUM_DIGEST_SIZE) return VB2_ERROR_UNKNOWN; - return tpm_extend_pcr(pcr, buffer, NULL); + + switch (which_digest) { + case BOOT_MODE_PCR: + return tpm_extend_pcr("GBB flags", pcr, buffer, size); + case HWID_DIGEST_PCR: + return tpm_extend_pcr("GBB HWID", pcr, buffer, size); + default: + return VB2_ERROR_UNKNOWN; + } } static uint32_t read_space_firmware(struct vb2_context *ctx) @@ -441,6 +449,9 @@ if (result == TPM_E_MUST_REBOOT) ctx->flags |= VB2_CONTEXT_SECDATA_WANTS_REBOOT; + // TCPA cbmem log + tcpa_log_init(); + return result; } -- To view, visit https://review.coreboot.org/27727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f Gerrit-Change-Number: 27727 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: security/tpm: Fix TCPA log commit
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has uploaded a new patch set (#2). ( https://review.coreboot.org/27726 ) Change subject: security/tpm: Fix TCPA log commit ...................................................................... security/tpm: Fix TCPA log commit * TCPA log overwrites newly generated log in acpi.c of x86/arch. Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/arch/x86/acpi.c M src/commonlib/include/commonlib/cbmem_id.h 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/27726/2 -- To view, visit https://review.coreboot.org/27726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Gerrit-Change-Number: 27726 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: security/tpm: Fix TCPA log commit
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27726 Change subject: security/tpm: Fix TCPA log commit ...................................................................... security/tpm: Fix TCPA log commit * TCPA log overwrites newly generated log in acpi.c of x86/arch. Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/arch/x86/acpi.c M src/commonlib/include/commonlib/cbmem_id.h 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/27726/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 60d2879..8d7579d 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -260,14 +260,14 @@ const struct cbmem_entry *ce; const u32 tcpa_default_log_len = 0x10000; void *lasa; - ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG); + ce = cbmem_entry_find(CBMEM_ID_TCPA_TCG_LOG); if (ce) { lasa = cbmem_entry_start(ce); *size = cbmem_entry_size(ce); printk(BIOS_DEBUG, "TCPA log found at %p\n", lasa); return lasa; } - lasa = cbmem_add(CBMEM_ID_TCPA_LOG, tcpa_default_log_len); + lasa = cbmem_add(CBMEM_ID_TCPA_TCG_LOG, tcpa_default_log_len); if (!lasa) { printk(BIOS_ERR, "TCPA log creation failed\n"); return NULL; diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index cc2fed1..c0c1010 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -64,7 +64,7 @@ #define CBMEM_ID_STAGEx_RAW 0x57a9e200 #define CBMEM_ID_STORAGE_DATA 0x53746f72 #define CBMEM_ID_TCPA_LOG 0x54435041 -#define CBMEM_ID_TCPA_COMPLIANT_LOG 0x54445041 +#define CBMEM_ID_TCPA_TCG_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 @@ -121,7 +121,7 @@ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ { CBMEM_ID_STORAGE_DATA, "SD/MMC/eMMC" }, \ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ - { CBMEM_ID_TCPA_COMPLIANT_LOG, "TCPA COMPLIANT LOG " }, \ + { CBMEM_ID_TCPA_TCG_LOG, "TCPA TCG LOG" }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ -- To view, visit https://review.coreboot.org/27726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Gerrit-Change-Number: 27726 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2]
by Felix Held (Code Review) 29 Jul '18

29 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27725 Change subject: sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2] ...................................................................... sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2] This patch contains the parts that changed the hash of the generated binary; probably due to the compiler optimizing things slightly different. Change-Id: Ide0b3296864e24edb646956e47221bfef8182e3d Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27725/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b21b5ac..6639fd9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1944,7 +1944,6 @@ { int channel, slotrank, lane; int err; - volatile u32 tmp; FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(0x4008 + 0x400 * channel, 0x8000000); @@ -1993,6 +1992,7 @@ MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { + volatile u32 tmp; MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); tmp = MCHBAR32(0x428c + 0x400 * channel); wait_428c(channel); @@ -2014,8 +2014,7 @@ printram("CPF\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - tmp = MCHBAR32(0x4080 + 0x400 * channel + 4 * lane); - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32_AND(0x4080 + 0x400 * channel + 4 * lane, 0); } FOR_ALL_POPULATED_CHANNELS { @@ -2039,8 +2038,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - tmp = MCHBAR32(0x4080 + 0x400 * channel + 4 * lane); - MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; + MCHBAR32_AND(0x4080 + 0x400 * channel + 4 * lane, 0); } return 0; } @@ -2591,7 +2589,6 @@ int lower[NUM_LANES]; int upper[NUM_LANES]; int pat; - volatile u32 tmp; FOR_ALL_LANES { lower[lane] = 0; @@ -2616,6 +2613,7 @@ program_timings(ctrl, channel); FOR_ALL_LANES { + volatile u32 tmp; MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; tmp = MCHBAR32(0x400 * channel + @@ -2660,6 +2658,7 @@ MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); FOR_ALL_LANES { + volatile u32 tmp; tmp = MCHBAR32(0x4340 + 0x400 * channel + lane * 4); } @@ -3153,10 +3152,10 @@ } printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32(0x5d10) = ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | + MCHBAR32_AND_OR(0x5d10, 0xC0C0C0C0, + ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | (encode_5d10(t1_ns) << 8) | ((encode_5d10(t3_ns) + - encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | - (MCHBAR32(0x5d10) & 0xC0C0C0C0) | 0xc; + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | 0xc); } void restore_timings(ramctr_timing * ctrl) -- To view, visit https://review.coreboot.org/27725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide0b3296864e24edb646956e47221bfef8182e3d Gerrit-Change-Number: 27725 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2]
by Felix Held (Code Review) 29 Jul '18

29 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27724 Change subject: sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2] ...................................................................... sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2] When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the resulting binary doesn't change with applying this commit. Change-Id: I2b1dc8befa3381f3edac06704e31e7ef50f86fa4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 26 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/27724/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 8165dc1..b21b5ac 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1947,17 +1947,15 @@ volatile u32 tmp; FOR_ALL_POPULATED_CHANNELS - MCHBAR32(0x4008 + 0x400 * channel) = - MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000; + MCHBAR32_OR(0x4008 + 0x400 * channel, 0x8000000); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32(0x4020 + 0x400 * channel) = - MCHBAR32(0x4020 + 0x400 * channel) | 0x200000; + MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); } /* refresh disable */ - MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8; + MCHBAR32_AND(0x5030, ~8); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -1992,11 +1990,10 @@ wait_428c(channel); /* refresh enable */ - MCHBAR32(0x5030) = MCHBAR32(0x5030) | 8; + MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(0x4020 + 0x400 * channel) = - ~0x00200000 & MCHBAR32(0x4020 + 0x400 * channel); + MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000); tmp = MCHBAR32(0x428c + 0x400 * channel); wait_428c(channel); @@ -2171,12 +2168,11 @@ MCHBAR32(0x4284 + 0x400 * channel) = 1; wait_428c(channel); - MCHBAR32(0x4020 + 0x400 * channel) = - MCHBAR32(0x4020 + 0x400 * channel) | 0x200000; + MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); } /* refresh disable */ - MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8; + MCHBAR32_AND(0x5030, ~8); FOR_ALL_POPULATED_CHANNELS { wait_428c(channel); @@ -2353,8 +2349,7 @@ * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; - MCHBAR32(0x4230 + 0x400 * channel) = - 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x360004; MCHBAR32(0x4210 + 0x400 * channel) = 0; @@ -2803,10 +2798,8 @@ for (i = 0; i < 3; i++) FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(0xe3c + (channel * 0x100)) = - (rege3c_b24[i] << 24) | - (MCHBAR32(0xe3c + (channel * 0x100)) - & ~0x3f000000); + MCHBAR32_AND_OR(0xe3c + (channel * 0x100), ~0x3f000000, + rege3c_b24[i] << 24); udelay(2); for (pat = 0; pat < NUM_PATTERNS; pat++) { FOR_ALL_POPULATED_RANKS { @@ -2862,8 +2855,7 @@ } FOR_ALL_CHANNELS { - MCHBAR32((channel * 0x100) + 0xe3c) = - 0 | (MCHBAR32((channel * 0x100) + 0xe3c) & ~0x3f000000); + MCHBAR32_AND((channel * 0x100) + 0xe3c, ~0x3f000000); udelay(2); } @@ -3060,10 +3052,8 @@ dram_odt_stretch(ctrl, channel); MCHBAR32(0x4008 + (channel << 10)) = - 0x0a000000 - | (b20 << 20) - | ((ctrl->ref_card_offset[channel] + 2) << 16) - | b4_8_12; + 0x0a000000 | (b20 << 20) | + ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; } } @@ -3073,7 +3063,7 @@ FOR_ALL_POPULATED_CHANNELS { MCHBAR32(0x42a0 + 0x400 * channel) = 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK + MCHBAR32_AND(0x4004 + 0x400 * channel, ~0x20000000); } } @@ -3094,8 +3084,8 @@ MCHBAR32(0x4cd4) = 0x00000046; - MCHBAR32(0x400c) = (MCHBAR32(0x400c) & 0xFFFFCFFF) | 0x1000; // OK - MCHBAR32(0x440c) = (MCHBAR32(0x440c) & 0xFFFFCFFF) | 0x1000; // OK + MCHBAR32_AND_OR(0x400c, 0xFFFFCFFF, 0x1000); + MCHBAR32_AND_OR(0x440c, 0xFFFFCFFF, 0x1000); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3129,14 +3119,14 @@ } MCHBAR32(0x5880) = 0xca9171e5; - MCHBAR32(0x5888) = (MCHBAR32(0x5888) & ~0xffffff) | 0xe4d5d0; - MCHBAR32(0x58a8) = MCHBAR32(0x58a8) & ~0x1f; - MCHBAR32(0x4294) = (MCHBAR32(0x4294) & ~0x30000) | (1 << 16); - MCHBAR32(0x4694) = (MCHBAR32(0x4694) & ~0x30000) | (1 << 16); + MCHBAR32_AND_OR(0x5888, ~0xffffff, 0xe4d5d0); + MCHBAR32_AND(0x58a8, ~0x1f); + MCHBAR32_AND_OR(0x4294, ~0x30000, 1 << 16); + MCHBAR32_AND_OR(0x4694, ~0x30000, 1 << 16); - MCHBAR32(0x5030) |= 1; // OK - MCHBAR32(0x5030) |= 0x80; // OK - MCHBAR32(0x5f18) = 0xfa; // OK + MCHBAR32(0x5030) |= 1; + MCHBAR32(0x5030) |= 0x80; + MCHBAR32(0x5f18) = 0xfa; /* Find a populated channel. */ FOR_ALL_POPULATED_CHANNELS @@ -3194,13 +3184,11 @@ } FOR_ALL_POPULATED_CHANNELS - MCHBAR32(0x4008 + 0x400 * channel) = - MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000; + MCHBAR32_OR(0x4008 + 0x400 * channel, 0x8000000); FOR_ALL_POPULATED_CHANNELS { udelay (1); - MCHBAR32(0x4020 + 0x400 * channel) = - MCHBAR32(0x4020 + 0x400 * channel) | 0x200000; + MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000); } printram("CPE\n"); @@ -3253,8 +3241,7 @@ MCHBAR32(0x3000) = 0; FOR_ALL_CHANNELS { - MCHBAR32(channel * 0x100 + 0xe3c) = - 0 | (MCHBAR32(channel * 0x100 + 0xe3c) & ~0x3f000000); + MCHBAR32_AND(channel * 0x100 + 0xe3c, ~0x3f000000); udelay(2); } -- To view, visit https://review.coreboot.org/27724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2b1dc8befa3381f3edac06704e31e7ef50f86fa4 Gerrit-Change-Number: 27724 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit July 2018