coreboot-gerrit July 2018

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Change in coreboot[master]: soc/fsp_baytrail: Fix vboot and TPM support
by Philipp Deppenwiese (Code Review) 29 Jul '18

29 Jul '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/23798 ) Change subject: soc/fsp_baytrail: Fix vboot and TPM support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/23798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Id33b7f2b9269593cd3e62f63752a660a144600da Gerrit-Change-Number: 23798 Gerrit-PatchSet: 13 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: opencellular/supabrckv1: Add LPC TPM to devicetree
by Philipp Deppenwiese (Code Review) 29 Jul '18

29 Jul '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/25705 ) Change subject: opencellular/supabrckv1: Add LPC TPM to devicetree ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/25705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I2ec0fca97f4581a1da35d424ace0526017a8e651 Gerrit-Change-Number: 25705 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/opencellular/rotundu: Add FMAP support
by Philipp Deppenwiese (Code Review) 29 Jul '18

29 Jul '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/25084 ) Change subject: mainboard/opencellular/rotundu: Add FMAP support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/25084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Gerrit-Change-Number: 25084 Gerrit-PatchSet: 11 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: soc/intel/fsp_baytrail: Add VBNV CMOS support
by Philipp Deppenwiese (Code Review) 29 Jul '18

29 Jul '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/25085 ) Change subject: soc/intel/fsp_baytrail: Add VBNV CMOS support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/25085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I2c1075f8e579c546edb4ff0581764a6a6aa7e89a Gerrit-Change-Number: 25085 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: pnp_device: don't treat missing PNP_MSC devicetree entry as error
by Felix Held (Code Review) 29 Jul '18

29 Jul '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/27668 ) Change subject: pnp_device: don't treat missing PNP_MSC devicetree entry as error ...................................................................... pnp_device: don't treat missing PNP_MSC devicetree entry as error Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/27668 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/pnp_device.c 1 file changed, 15 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 09a2748..e56b00d 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -118,9 +118,21 @@ static void pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " - "not assigned\n", dev_path(dev), resource->index, - resource_type(resource), resource->size); + /* The PNP_MSC super IO registers have the IRQ flag set. If no + value is assigned in the devicetree, the corresponding + PNP_MSC register doesn't get written, which should be printed + as warning and not as error. */ + if (resource->flags & IORESOURCE_IRQ && + (resource->index != PNP_IDX_IRQ0) && + (resource->index != PNP_IDX_IRQ1)) + printk(BIOS_WARNING, "WARNING: %s %02lx %s size: " + "0x%010llx not assigned\n", dev_path(dev), + resource->index, resource_type(resource), + resource->size); + else + printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " + "not assigned\n", dev_path(dev), resource->index, + resource_type(resource), resource->size); return; } -- To view, visit https://review.coreboot.org/27668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a Gerrit-Change-Number: 27668 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel: Remove legacy static TPM asl code
by Philipp Deppenwiese (Code Review) 29 Jul '18

29 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27715 ) Change subject: soc/intel: Remove legacy static TPM asl code ...................................................................... soc/intel: Remove legacy static TPM asl code Since the TPM software stack refactoring static TPM ACPI code isn't needed anymore. Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/27715 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/fsp_baytrail/acpi/lpc.asl 4 files changed, 0 insertions(+), 93 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 17d6f43..00aac51 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -135,27 +135,4 @@ // Include mainboard's superio.asl file. #include "acpi/superio.asl" - -#if IS_ENABLED(CONFIG_LPC_TPM) - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - } -#endif } diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index eb4a16a..0a8b8bc 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -137,27 +137,4 @@ /* Include mainboard's superio.asl file. */ #include "acpi/superio.asl" - -#if IS_ENABLED(CONFIG_LPC_TPM) - Device (TPM) /* Trusted Platform Module */ - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - } -#endif } diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index 3167c18..cc36451 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -205,28 +205,4 @@ Return(BUF0) } } - -#ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - IRQ (Edge, Activehigh, Exclusive) { 6 } - }) - } -#endif } diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl index 17d6f43..00aac51 100644 --- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl +++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl @@ -135,27 +135,4 @@ // Include mainboard's superio.asl file. #include "acpi/superio.asl" - -#if IS_ENABLED(CONFIG_LPC_TPM) - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - } -#endif } -- To view, visit https://review.coreboot.org/27715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Gerrit-Change-Number: 27715 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel: Remove legacy static TPM asl code
by Felix Held (Code Review) 29 Jul '18

29 Jul '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27715 ) Change subject: soc/intel: Remove legacy static TPM asl code ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Gerrit-Change-Number: 27715 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 29 Jul 2018 12:29:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel: Remove legacy static TPM asl code
by Philipp Deppenwiese (Code Review) 29 Jul '18

29 Jul '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27715 Change subject: soc/intel: Remove legacy static TPM asl code ...................................................................... soc/intel: Remove legacy static TPM asl code Since the TPM software stack refactoring static TPM ACPI code isn't needed anymore. Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/soc/intel/baytrail/acpi/lpc.asl M src/soc/intel/braswell/acpi/lpc.asl M src/soc/intel/denverton_ns/acpi/lpc.asl M src/soc/intel/fsp_baytrail/acpi/lpc.asl 4 files changed, 0 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/27715/1 diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 17d6f43..00aac51 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -135,27 +135,4 @@ // Include mainboard's superio.asl file. #include "acpi/superio.asl" - -#if IS_ENABLED(CONFIG_LPC_TPM) - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - } -#endif } diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index eb4a16a..0a8b8bc 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -137,27 +137,4 @@ /* Include mainboard's superio.asl file. */ #include "acpi/superio.asl" - -#if IS_ENABLED(CONFIG_LPC_TPM) - Device (TPM) /* Trusted Platform Module */ - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - } -#endif } diff --git a/src/soc/intel/denverton_ns/acpi/lpc.asl b/src/soc/intel/denverton_ns/acpi/lpc.asl index 3167c18..cc36451 100644 --- a/src/soc/intel/denverton_ns/acpi/lpc.asl +++ b/src/soc/intel/denverton_ns/acpi/lpc.asl @@ -205,28 +205,4 @@ Return(BUF0) } } - -#ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - IRQ (Edge, Activehigh, Exclusive) { 6 } - }) - } -#endif } diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl index 17d6f43..00aac51 100644 --- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl +++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl @@ -135,27 +135,4 @@ // Include mainboard's superio.asl file. #include "acpi/superio.asl" - -#if IS_ENABLED(CONFIG_LPC_TPM) - Device (TPM) // Trusted Platform Module - { - Name(_HID, EISAID("IFX0102")) - Name(_CID, 0x310cd041) - Name(_UID, 1) - - Method(_STA, 0) - { - If (TPMP) { - Return (0xf) - } - Return (0x0) - } - - Name(_CRS, ResourceTemplate() { - IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) - IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) - Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) - }) - } -#endif } -- To view, visit https://review.coreboot.org/27715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Gerrit-Change-Number: 27715 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: security/vboot: Add failure safety configurations
by Philipp Deppenwiese (Code Review) 29 Jul '18

29 Jul '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27714 Change subject: security/vboot: Add failure safety configurations ...................................................................... security/vboot: Add failure safety configurations * Make an user interface and board configuration through kconfig available. * 3 modes are now supported: + RO only + RO + RW_A + RO + RW_A + RW_B * The default mode is always RO + RW_A + RW_B Change-Id: I278fc060522b13048b00090b8e5261c14496f56e Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 2 files changed, 84 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/27714/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e13101b..4467c02 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -25,6 +25,59 @@ if VBOOT +config VBOOT_SAFETY_AB + bool + default y if MAINBOARD_HAS_VBOOT_SAFETY_AB || USER_VBOOT_SAFETY_AB + +config VBOOT_SAFETY_A + bool + default y if MAINBOARD_HAS_VBOOT_SAFETY_A || USER_VBOOT_SAFETY_A + +config VBOOT_SAFETY_RO + bool + default y if MAINBOARD_HAS_VBOOT_SAFETY_RO || USER_VBOOT_SAFETY_RO + +config MAINBOARD_HAS_VBOOT_SAFETY_AB + bool + +config MAINBOARD_HAS_VBOOT_SAFETY_A + bool + +config MAINBOARD_HAS_VBOOT_SAFETY_RO + bool + +if !MAINBOARD_HAS_VBOOT_SAFETY_AB && !MAINBOARD_HAS_VBOOT_SAFETY_A && !MAINBOARD_HAS_VBOOT_SAFETY_RO + +choice + +prompt "Failure safety" + default USER_VBOOT_SAFETY_AB + help + Select the failure safety mode in which VBOOT should run. + VBOOT can have up to two recovery partitions for A & B updates + which also provide failure safety. + +config USER_VBOOT_SAFETY_AB + bool "Firmware RO + A & B" + help + Have two update partitions/fallbacks. + +config USER_VBOOT_SAFETY_A + bool "Firmware RO + A" + help + Have one update partition/fallback. + +config USER_VBOOT_SAFETY_RO + bool "Firmware RO only" + help + Have no update partition/fallback. + If the coreboot region is write protected no + updates are possible in this configuration. + +endchoice + +endif + config VBOOT_VBNV_CMOS bool default n diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index b542425..1e8a46f 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -142,6 +142,19 @@ endif endif # CONFIG_VBOOT_SEPARATE_VERSTAGE +# Check safety mode +ifeq ($(CONFIG_VBOOT_SAFETY_AB),y) +VBOOT_PARTITIONS := COREBOOT FW_MAIN_A FW_MAIN_B +endif + +ifeq ($(CONFIG_VBOOT_SAFETY_A),y) +VBOOT_PARTITIONS := COREBOOT FW_MAIN_A +endif + +ifeq ($(CONFIG_VBOOT_SAFETY_RO),y) +VBOOT_PARTITIONS := COREBOOT +endif + # Define a list of files that need to be in RO only. # All other files will be installed into RO and RW regions # Use $(sort) to cut down on extra spaces that would be translated to commas @@ -159,7 +172,7 @@ cmos_layout.bin \ cmos.default \ $(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \ - ,$(1)),COREBOOT,COREBOOT FW_MAIN_A FW_MAIN_B))) + ,$(1)),COREBOOT,$(VBOOT_PARTITIONS)))) CONFIG_GBB_HWID := $(call strip_quotes,$(CONFIG_GBB_HWID)) CONFIG_GBB_BMPFV_FILE := $(call strip_quotes,$(CONFIG_GBB_BMPFV_FILE)) @@ -230,8 +243,13 @@ @printf " WRITE GBB\n" $(CBFSTOOL) $(obj)/coreboot.rom write -u -r GBB -i 0 -f $(obj)/gbb.region $(CBFSTOOL) $(obj)/coreboot.rom write -u -r RO_FRID -i 0 -f $(obj)/fwid.region +ifeq ($(CONFIG_VBOOT_SAFETY_AB),y) $(CBFSTOOL) $(obj)/coreboot.rom write -u -r RW_FWID_A -i 0 -f $(obj)/fwid.region $(CBFSTOOL) $(obj)/coreboot.rom write -u -r RW_FWID_B -i 0 -f $(obj)/fwid.region +endif +ifeq ($(CONFIG_VBOOT_SAFETY_A),y) + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r RW_FWID_A -i 0 -f $(obj)/fwid.region +endif ifneq ($(shell grep "SHARED_DATA" "$(CONFIG_FMDFILE)"),) build_complete:: @@ -263,8 +281,20 @@ --kernelkey "$(CONFIG_VBOOT_KERNEL_KEY)" \ --flags $(CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS) +ifeq ($(CONFIG_VBOOT_SAFETY_AB),y) files_added:: $(obj)/VBLOCK_A.bin $(obj)/VBLOCK_B.bin $(CBFSTOOL) $(obj)/coreboot.rom write -u -r VBLOCK_A -f $(obj)/VBLOCK_A.bin $(CBFSTOOL) $(obj)/coreboot.rom write -u -r VBLOCK_B -f $(obj)/VBLOCK_B.bin + @printf " FLASHMAP Layout generated for RO, A and B partition.\n" +endif +ifeq ($(CONFIG_VBOOT_SAFETY_A),y) +files_added:: $(obj)/VBLOCK_A.bin + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r VBLOCK_A -f $(obj)/VBLOCK_A.bin + @printf " FLASHMAP Layout generated for RO and A partition.\n" +endif +ifeq ($(CONFIG_VBOOT_SAFETY_RO),y) +files_added:: + @printf " FLASHMAP Layout generated for RO partition only, beware no updates possible!\n" +endif endif # CONFIG_VBOOT -- To view, visit https://review.coreboot.org/27714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I278fc060522b13048b00090b8e5261c14496f56e Gerrit-Change-Number: 27714 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: northbridge/nehalem: clean up header file
by Arthur Heymans (Code Review) 29 Jul '18

29 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27713 ) Change subject: northbridge/nehalem: clean up header file ...................................................................... Patch Set 1: Identical with BUILD_TIMELESS=1 -- To view, visit https://review.coreboot.org/27713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f758203afdcb1b18f3c0d786698f9fbf2246e0e Gerrit-Change-Number: 27713 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 29 Jul 2018 11:32:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit July 2018