coreboot-gerrit July 2018

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Change in coreboot[master]: mainboard/opencellular/rotundu: Add supabrck EMMC support
by Felix Held (Code Review) 28 Jul '18

28 Jul '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27684 ) Change subject: mainboard/opencellular/rotundu: Add supabrck EMMC support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43 Gerrit-Change-Number: 27684 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Jul 2018 17:09:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/cbmem: Add cbmem TCPA log support
by Philipp Deppenwiese (Code Review) 28 Jul '18

28 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/26244 ) Change subject: util/cbmem: Add cbmem TCPA log support ...................................................................... util/cbmem: Add cbmem TCPA log support * Read and print the TCPA ACPI log. Change-Id: Ie2253d86cfc675d45b0a728794cc784215401f4a Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/26244 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/coreboot_table.c M util/cbmem/cbmem.c 3 files changed, 73 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index f411ff2..806dfc7 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -310,6 +310,7 @@ #define LB_TAG_CBMEM_CONSOLE 0x0017 #define LB_TAG_MRC_CACHE 0x0018 #define LB_TAG_ACPI_GNVS 0x0024 +#define LB_TAG_TCPA_LOG 0x0034 #define LB_TAG_WIFI_CALIBRATION 0x0027 #define LB_TAG_VPD 0x002c struct lb_cbmem_ref { diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 8fc7b6f..2d74c8e 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -339,7 +339,8 @@ {CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}, {CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS}, {CBMEM_ID_VPD, LB_TAG_VPD}, - {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION} + {CBMEM_ID_WIFI_CALIBRATION, LB_TAG_WIFI_CALIBRATION}, + {CBMEM_ID_TCPA_LOG, LB_TAG_TCPA_LOG} }; int i; diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 42761dc..3435c4c 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -34,6 +34,7 @@ #include <regex.h> #include <commonlib/cbmem_id.h> #include <commonlib/timestamp_serialized.h> +#include <commonlib/tcpa_log_serialized.h> #include <commonlib/coreboot_tables.h> #ifdef __OpenBSD__ @@ -264,6 +265,7 @@ static struct lb_cbmem_ref timestamps; static struct lb_cbmem_ref console; +static struct lb_cbmem_ref tcpa_log; static struct lb_memory_range cbmem; /* This is a work-around for a nasty problem introduced by initially having @@ -308,7 +310,7 @@ static int parse_cbtable_entries(const struct mapping *table_mapping) { size_t i; - const struct lb_record* lbr_p; + const struct lb_record *lbr_p; size_t table_size = mapping_size(table_mapping); const void *lbtable = mapping_virt(table_mapping); int forwarding_table_found = 0; @@ -323,12 +325,19 @@ continue; case LB_TAG_TIMESTAMPS: { debug(" Found timestamp table.\n"); - timestamps = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); + timestamps = + parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p); continue; } case LB_TAG_CBMEM_CONSOLE: { debug(" Found cbmem console.\n"); - console = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); + console = parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p); + continue; + } + case LB_TAG_TCPA_LOG: { + debug(" Found tcpa log table.\n"); + tcpa_log = + parse_cbmem_ref((struct lb_cbmem_ref *)lbr_p); continue; } case LB_TAG_FORWARD: { @@ -338,7 +347,7 @@ * search at the new address. */ struct lb_forward lbf_p = - *(const struct lb_forward *) lbr_p; + *(const struct lb_forward *)lbr_p; debug(" Found forwarding entry.\n"); ret = parse_cbtable(lbf_p.forward, 0); @@ -674,6 +683,51 @@ free(sorted_tst_p); } +/* dump the tcpa log table */ +static void dump_tcpa_log(void) +{ + int i, j; + const struct tcpa_table *tclt_p; + size_t size; + struct mapping tcpa_mapping; + char log_string[TCPA_LOG_STRING_LENGTH]; + char hash[TCPA_FORMAT_HASH_LENGTH]; + + if (tcpa_log.tag != LB_TAG_TCPA_LOG) { + fprintf(stderr, "No tcpa log found in coreboot table.\n"); + return; + } + + size = sizeof(*tclt_p); + tclt_p = map_memory(&tcpa_mapping, tcpa_log.cbmem_addr, size); + if (!tclt_p) + die("Unable to map tcpa log header\n"); + + size += tclt_p->num_entries * sizeof(tclt_p->entries[0]); + + unmap_memory(&tcpa_mapping); + + tclt_p = map_memory(&tcpa_mapping, tcpa_log.cbmem_addr, size); + if (!tclt_p) + die("Unable to map full tcpa log table\n"); + + printf("coreboot TCPA log:\n\n"); + + for (i = 0; i < tclt_p->num_entries; i++) { + const struct tcpa_entry *tce = &tclt_p->entries[i]; + + memset(log_string, 0, TCPA_LOG_STRING_LENGTH); + for (j = 0; j < tce->digest_length; j++) + sprintf((char *)&(hash[j * 2]), "%02x", tce->digest[j]); + + snprintf(log_string, TCPA_LOG_STRING_LENGTH, "%u %s 00 [%s]\n", + tce->pcr, hash, tce->name); + printf("%s", log_string); + } + + unmap_memory(&tcpa_mapping); +} + struct cbmem_console { u32 size; u32 cursor; @@ -1051,7 +1105,7 @@ static void print_usage(const char *name, int exit_code) { - printf("usage: %s [-cCltTxVvh?]\n", name); + printf("usage: %s [-cCltTLxVvh?]\n", name); printf("\n" " -c | --console: print cbmem console\n" " -1 | --oneboot: print cbmem console for last boot only\n" @@ -1061,6 +1115,7 @@ " -r | --rawdump ID: print rawdump of specific ID (in hex) of cbtable\n" " -t | --timestamps: print timestamp information\n" " -T | --parseable-timestamps: print parseable timestamps\n" + " -L | --tcpa-log print TCPA log\n" " -V | --verbose: verbose (debugging) output\n" " -v | --version: print the version\n" " -h | --help: print this help\n" @@ -1192,6 +1247,7 @@ int print_hexdump = 0; int print_rawdump = 0; int print_timestamps = 0; + int print_tcpa_log = 0; int machine_readable_timestamps = 0; int one_boot_only = 0; unsigned int rawdump_id = 0; @@ -1202,6 +1258,7 @@ {"oneboot", 0, 0, '1'}, {"coverage", 0, 0, 'C'}, {"list", 0, 0, 'l'}, + {"tcpa-log", 0, 0, 'L'}, {"timestamps", 0, 0, 't'}, {"parseable-timestamps", 0, 0, 'T'}, {"hexdump", 0, 0, 'x'}, @@ -1211,7 +1268,7 @@ {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "c1CltTxVvh?r:", + while ((opt = getopt_long(argc, argv, "c1CltTLxVvh?r:", long_options, &option_index)) != EOF) { switch (opt) { case 'c': @@ -1231,6 +1288,10 @@ print_list = 1; print_defaults = 0; break; + case 'L': + print_tcpa_log = 1; + print_defaults = 0; + break; case 'x': print_hexdump = 1; print_defaults = 0; @@ -1357,6 +1418,9 @@ if (print_defaults || print_timestamps) dump_timestamps(machine_readable_timestamps); + if (print_tcpa_log) + dump_tcpa_log(); + unmap_memory(&lbtable_mapping); close(mem_fd); -- To view, visit https://review.coreboot.org/26244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ie2253d86cfc675d45b0a728794cc784215401f4a Gerrit-Change-Number: 26244 Gerrit-PatchSet: 16 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: security/tpm: Add TCPA logging functionality
by Philipp Deppenwiese (Code Review) 28 Jul '18

28 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/22867 ) Change subject: security/tpm: Add TCPA logging functionality ...................................................................... security/tpm: Add TCPA logging functionality * TCG spec only applies to BIOS or UEFI. * Therefore implement coreboot TCPA compliant log in CBMEM. * Write CBMEM log into the coreboot table for CBMEM tool access Change-Id: I0a52494f647d21e2587231af26ed13d62b3a72f5 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/22867 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/commonlib/include/commonlib/cbmem_id.h A src/commonlib/include/commonlib/tcpa_log_serialized.h M src/drivers/tpm/tpm.c M src/security/tpm/Makefile.inc M src/security/tpm/tspi.h A src/security/tpm/tspi/log.c 6 files changed, 141 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 3529fef..cc2fed1 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -64,6 +64,7 @@ #define CBMEM_ID_STAGEx_RAW 0x57a9e200 #define CBMEM_ID_STORAGE_DATA 0x53746f72 #define CBMEM_ID_TCPA_LOG 0x54435041 +#define CBMEM_ID_TCPA_COMPLIANT_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 @@ -120,6 +121,7 @@ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ { CBMEM_ID_STORAGE_DATA, "SD/MMC/eMMC" }, \ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ + { CBMEM_ID_TCPA_COMPLIANT_LOG, "TCPA COMPLIANT LOG " }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ diff --git a/src/commonlib/include/commonlib/tcpa_log_serialized.h b/src/commonlib/include/commonlib/tcpa_log_serialized.h new file mode 100644 index 0000000..cd6fbec --- /dev/null +++ b/src/commonlib/include/commonlib/tcpa_log_serialized.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __TCPA_LOG_SERIALIZED_H__ +#define __TCPA_LOG_SERIALIZED_H__ + +#include <compiler.h> +#include <stdint.h> + +#define MAX_TCPA_LOG_ENTRIES 50 +#define TCPA_LOG_STRING_LENGTH 512 +#define TCPA_FORMAT_HASH_LENGTH 128 +#define TCPA_DIGEST_MAX_LENGTH 64 +#define TCPA_PCR_HASH_NAME 256 + +struct tcpa_entry { + uint32_t pcr; + uint8_t digest[TCPA_DIGEST_MAX_LENGTH]; + uint32_t digest_length; + uint8_t name[TCPA_PCR_HASH_NAME]; +} __packed; + +struct tcpa_table { + uint16_t max_entries; + uint16_t num_entries; + struct tcpa_entry entries[0]; /* Variable number of entries */ +} __packed; + +#endif diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index e4a81c3..8c68159 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -30,6 +30,9 @@ #else tpm_setup(false); #endif + + // TCPA cbmem log + tcpa_log_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, init_tpm_dev, NULL); diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index 9157fec..34ead8f 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -12,11 +12,11 @@ ## TSPI -ramstage-y += tspi/tspi.c -romstage-y += tspi/tspi.c +ramstage-y += tspi/tspi.c tspi/log.c +romstage-y += tspi/tspi.c tspi/log.c -verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c +verstage-$(CONFIG_VBOOT) += tspi/tspi.c tspi/log.c +postcar-$(CONFIG_VBOOT) += tspi/tspi.c tspi/log.c endif # CONFIG_TPM1 @@ -36,10 +36,10 @@ ## TSPI -ramstage-y += tspi/tspi.c -romstage-y += tspi/tspi.c +ramstage-y += tspi/tspi.c tspi/log.c +romstage-y += tspi/tspi.c tspi/log.c -verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c +verstage-$(CONFIG_VBOOT) += tspi/tspi.c tspi/log.c +postcar-$(CONFIG_VBOOT) += tspi/tspi.c tspi/log.c endif # CONFIG_TPM2 diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index fdc9e1c..01b2984 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -18,6 +18,18 @@ #define TSPI_H_ #include <security/tpm/tss.h> +#include <commonlib/tcpa_log_serialized.h> + +/** + * Setup TCPA cbmem log. + */ +void tcpa_log_init(void); + +/** + * Add table entry for cbmem TCPA log. + */ +int tcpa_log_add_table_entry(const char *name, const uint32_t pcr, + const uint8_t *digest, const size_t digest_length); /** * Ask vboot for a digest and extend a TPM PCR with it. diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c new file mode 100644 index 0000000..6091dfe --- /dev/null +++ b/src/security/tpm/tspi/log.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <security/tpm/tspi.h> + +void tcpa_log_init(void) +{ + const struct cbmem_entry *ce; + struct tcpa_table *tclt; + + if (!cbmem_possibly_online()) + return; + + ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG); + if (ce) + return; + + tclt = cbmem_add(CBMEM_ID_TCPA_LOG, + sizeof(struct tcpa_table) + + MAX_TCPA_LOG_ENTRIES * + sizeof(struct tcpa_entry)); + + if (!tclt) + return; + + tclt->max_entries = MAX_TCPA_LOG_ENTRIES; + tclt->num_entries = 0; + + printk(BIOS_DEBUG, "TCPA log created at %p\n", tclt); +} + +int tcpa_log_add_table_entry(const char *name, const uint32_t pcr, + const uint8_t *digest, const size_t digest_length) +{ + MAYBE_STATIC struct tcpa_table *tclt = NULL; + struct tcpa_entry *tce; + + if (!cbmem_possibly_online()) + return -1; + + tclt = cbmem_find(CBMEM_ID_TCPA_LOG); + if (!tclt) { + printk(BIOS_ERR, "ERROR: No TCPA log table found\n"); + return -1; + } + + if (tclt->num_entries == tclt->max_entries) { + printk(BIOS_WARNING, "ERROR: TCPA log table is full\n"); + return -1; + } + + tce = &tclt->entries[tclt->num_entries++]; + + memcpy(tce->name, name, TCPA_PCR_HASH_NAME); + tce->pcr = pcr; + memcpy(tce->digest, digest, digest_length); + tce->digest_length = digest_length; + + return 0; +} -- To view, visit https://review.coreboot.org/22867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I0a52494f647d21e2587231af26ed13d62b3a72f5 Gerrit-Change-Number: 22867 Gerrit-PatchSet: 41 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/opencellular/rotundu: Add supabrck EMMC support
by Philipp Deppenwiese (Code Review) 28 Jul '18

28 Jul '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27684 Change subject: mainboard/opencellular/rotundu: Add supabrck EMMC support ...................................................................... mainboard/opencellular/rotundu: Add supabrck EMMC support Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb M src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c 2 files changed, 16 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/27684/1 diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb index a31a001..df08922 100644 --- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb +++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb @@ -26,7 +26,7 @@ register "PcdMrcInitSPDAddr1" = "0xa0" register "PcdMrcInitSPDAddr2" = "0xa2" register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" - register "PcdeMMCBootMode" = "EMMC_DISABLED" + register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" register "PcdGttSize" = "GTT_SIZE_DEFAULT" @@ -53,7 +53,7 @@ device pci 14.0 on end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time device pci 15.0 off end # 8086 0F28 - LP Engine Audio device pci 16.0 off end # 8086 0F37 - OTG controller - device pci 17.0 off end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time + device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time device pci 18.0 on end # 8086 0F40 - SIO - DMA device pci 18.1 on end # 8086 0F41 - I2C Port 1 device pci 18.2 off end # 8086 0F42 - I2C Port 2 diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c index 78d1ad6..c9d5426 100644 --- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c +++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c @@ -19,6 +19,9 @@ #include <soc/gpio.h> #include "../../irqroute.h" +#define GPIO_FUNC3_PULL_UP_20K GPIO_FUNC(3, PULL_UP, 20K) +#define GPIO_FUNC3_PULL_DOWN_20K GPIO_FUNC(3, PULL_DOWN, 20K) + /* NCORE GPIOs */ static const struct soc_gpio_map gpncore_gpio_map[] = { @@ -85,27 +88,27 @@ /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED*/ GPIO_DEFAULT, /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED*/ - GPIO_NC, + GPIO_FUNC3_PULL_DOWN_20K, /* GPIO_S0_SC[016] MMC1_CLK MMC1_45_CLK */ - GPIO_NC, + GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[017] MMC1_D[0] MMC1_45_D[0] */ - GPIO_NC, + GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[018] MMC1_D[1] MMC1_45_D[1] */ - GPIO_NC, + GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[019] MMC1_D[2] MMC1_45_D[2] */ - GPIO_NC, + GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[020] MMC1_D[3] MMC1_45_D[3] */ - GPIO_NC, + GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[021] MMC1_D[4] MMC1_45_D[4] */ - GPIO_NC, + GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[022] MMC1_D[5] MMC1_45_D[5] */ - GPIO_NC, + GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[023] MMC1_D[6] MMC1_45_D[6] */ - GPIO_NC, + GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[024] MMC1_D[7] MMC1_45_D[7] */ - GPIO_NC, + GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[025] MMC1_CMD MMC1_45_CMD */ - GPIO_NC, + GPIO_FUNC3_PULL_DOWN_20K, /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# */ GPIO_NC, /* GPIO_S0_SC[027] SD2_CLK */ -- To view, visit https://review.coreboot.org/27684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icf9feaf6f74cfe33a817bb2f1ecd3d49aa5e9a43 Gerrit-Change-Number: 27684 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: sandybridge/raminit: use MCHBAR32 macro everywhere
by Arthur Heymans (Code Review) 28 Jul '18

28 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27675 ) Change subject: sandybridge/raminit: use MCHBAR32 macro everywhere ...................................................................... Patch Set 1: Code-Review+2 produces identical binary without this patch with BUILD_TIMELESS=1 -- To view, visit https://review.coreboot.org/27675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Gerrit-Change-Number: 27675 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Jul 2018 16:50:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macros
by Patrick Rudolph (Code Review) 28 Jul '18

28 Jul '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/27682 ) Change subject: sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macros ...................................................................... Patch Set 1: Code-Review+2 Tested on HP8200. -- To view, visit https://review.coreboot.org/27682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If8b8fd123e0dd15a0fc9dfe178076f8541e29d56 Gerrit-Change-Number: 27682 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Jul 2018 16:45:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: opencellular/rotundu: Introduce variants for OC
by build bot (Jenkins) (Code Review) 28 Jul '18

28 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22924 ) Change subject: opencellular/rotundu: Introduce variants for OC ...................................................................... Patch Set 23: (146 comments) https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… File src/mainboard/opencellular/rotundu/variants/supabrckv1/gpio.c: https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 60: GPIO_NC, /* GPIO_S0_SC[000] SATA_GP[0] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 61: GPIO_NC, /* GPIO_S0_SC[001] SATA_GP[1] SATA_DEVSLP[0] - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 62: GPIO_FUNC1, /* GPIO_S0_SC[002] SATA_LED# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 63: GPIO_FUNC1, /* GPIO_S0_SC[003] PCIE_CLKREQ[0]# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 64: GPIO_FUNC1, /* GPIO_S0_SC[004] PCIE_CLKREQ[1]# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 65: GPIO_FUNC1, /* GPIO_S0_SC[005] PCIE_CLKREQ[2]# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 66: GPIO_FUNC1, /* GPIO_S0_SC[006] PCIE_CLKREQ[3]# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 67: GPIO_FUNC2, /* GPIO_S0_SC[007] RESERVED SD3_WP - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 68: GPIO_NC, /* GPIO_S0_SC[008] I2S0_CLK HDA_RST# - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 69: GPIO_NC, /* GPIO_S0_SC[009] I2S0_FRM HDA_SYNC - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 70: GPIO_NC, /* GPIO_S0_SC[010] I2S0_DATAOUT HDA_CLK - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 71: GPIO_NC, /* GPIO_S0_SC[011] I2S0_DATAIN HDA_SDO - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 72: GPIO_NC, /* GPIO_S0_SC[012] I2S1_CLK HDA_SDI[0] - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 73: GPIO_NC, /* GPIO_S0_SC[013] I2S1_FRM HDA_SDI[1] - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 74: GPIO_NC, /* GPIO_S0_SC[014] I2S1_DATAOUT RESERVED - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 75: GPIO_DEFAULT, /* GPIO_S0_SC[015] I2S1_DATAIN RESERVED - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 76: GPIO_FUNC3_PULL_DOWN_20K, /* GPIO_S0_SC[016] MMC1_CLK - MMC1_45_CLK - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 77: GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[017] MMC1_D[0] - MMC1_45_D[0] - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 78: GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[018] MMC1_D[1] - MMC1_45_D[1] - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 79: GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[019] MMC1_D[2] - MMC1_45_D[2] - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 80: GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[020] MMC1_D[3] - MMC1_45_D[3] - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 81: GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[021] MMC1_D[4] - MMC1_45_D[4] - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 82: GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[022] MMC1_D[5] - MMC1_45_D[5] - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 83: GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[023] MMC1_D[6] - MMC1_45_D[6] - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 84: GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[024] MMC1_D[7] - MMC1_45_D[7] - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 85: GPIO_FUNC3_PULL_UP_20K, /* GPIO_S0_SC[025] MMC1_CMD - MMC1_45_CMD - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 86: GPIO_FUNC3_PULL_DOWN_20K, /* GPIO_S0_SC[026] MMC1_RST# SATA_DEVSLP[0] MMC1_45_RST# - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 87: GPIO_NC, /* GPIO_S0_SC[027] SD2_CLK - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 88: GPIO_NC, /* GPIO_S0_SC[028] SD2_D[0] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 89: GPIO_NC, /* GPIO_S0_SC[029] SD2_D[1] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 90: GPIO_NC, /* GPIO_S0_SC[030] SD2_D[2] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 91: GPIO_NC, /* GPIO_S0_SC[031] SD2_D[3]_CD# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 92: GPIO_NC, /* GPIO_S0_SC[032] SD2_CMD - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 93: GPIO_NC, /* GPIO_S0_SC[033] SD3_CLK - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 94: GPIO_NC, /* GPIO_S0_SC[034] SD3_D[0] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 95: GPIO_NC, /* GPIO_S0_SC[035] SD3_D[1] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 96: GPIO_NC, /* GPIO_S0_SC[036] SD3_D[2] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 97: GPIO_NC, /* GPIO_S0_SC[037] SD3_D[3] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 98: GPIO_NC, /* GPIO_S0_SC[038] SD3_CD# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 99: GPIO_NC, /* GPIO_S0_SC[039] SD3_CMD - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 100: GPIO_FUNC1, /* GPIO_S0_SC[040] SD3_1P8EN - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 101: GPIO_FUNC1, /* GPIO_S0_SC[041] SD3_PWREN# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 102: GPIO_FUNC1, /* GPIO_S0_SC[042] ILB_LPC_AD[0] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 103: GPIO_FUNC1, /* GPIO_S0_SC[043] ILB_LPC_AD[1] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 104: GPIO_FUNC1, /* GPIO_S0_SC[044] ILB_LPC_AD[2] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 105: GPIO_FUNC1, /* GPIO_S0_SC[045] ILB_LPC_AD[3] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 106: GPIO_FUNC1, /* GPIO_S0_SC[046] ILB_LPC_FRAME# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 107: GPIO_FUNC1, /* GPIO_S0_SC[047] ILB_LPC_CLK[0] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 108: GPIO_NC, /* GPIO_S0_SC[048] ILB_LPC_CLK[1] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 109: GPIO_FUNC1, /* GPIO_S0_SC[049] ILB_LPC_CLKRUN# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 110: GPIO_FUNC1, /* GPIO_S0_SC[050] ILB_LPC_SERIRQ - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 111: GPIO_FUNC1, /* GPIO_S0_SC[051] PCU_SMB_DATA - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 112: GPIO_FUNC1, /* GPIO_S0_SC[052] PCU_SMB_CLK - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 113: GPIO_FUNC1, /* GPIO_S0_SC[053] PCU_SMB_ALERT# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 114: GPIO_NC, /* GPIO_S0_SC[054] ILB_8254_SPKR RESERVED - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 115: GPIO_DEFAULT, /* GPIO_S0_SC[055] RESERVED - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 116: GPIO_DEFAULT, /* GPIO_S0_SC[056] RESERVED - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 117: GPIO_FUNC1, /* GPIO_S0_SC[057] PCU_UART_TXD - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 118: GPIO_DEFAULT, /* GPIO_S0_SC[058] RESERVED - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 119: GPIO_DEFAULT, /* GPIO_S0_SC[059] RESERVED - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 120: GPIO_DEFAULT, /* GPIO_S0_SC[060] RESERVED - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 121: GPIO_FUNC1, /* GPIO_S0_SC[061] PCU_UART_RXD - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 122: GPIO_NC, /* GPIO_S0_SC[062] LPE_I2S2_CLK SATA_DEVSLP[1] RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 123: GPIO_FUNC1, /* GPIO_S0_SC[063] LPE_I2S2_FRM RESERVED - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 124: GPIO_NC, /* GPIO_S0_SC[064] LPE_I2S2_DATAIN - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 125: GPIO_FUNC1, /* GPIO_S0_SC[065] LPE_I2S2_DATAOUT - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 126: GPIO_NC, /* GPIO_S0_SC[066] SIO_SPI_CS# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 127: GPIO_NC, /* GPIO_S0_SC[067] SIO_SPI_MISO - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 128: GPIO_NC, /* GPIO_S0_SC[068] SIO_SPI_MOSI - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 129: GPIO_NC, /* GPIO_S0_SC[069] SIO_SPI_CLK - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 130: GPIO_FUNC1, /* GPIO_S0_SC[070] SIO_UART1_RXD RESERVED - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 131: GPIO_FUNC1, /* GPIO_S0_SC[071] SIO_UART1_TXD RESERVED - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 132: GPIO_NC, /* GPIO_S0_SC[072] SIO_UART1_RTS# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 133: GPIO_DEFAULT, /* GPIO_S0_SC[073] SIO_UART1_CTS# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 134: GPIO_NC, /* GPIO_S0_SC[074] SIO_UART2_RXD - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 135: GPIO_NC, /* GPIO_S0_SC[075] SIO_UART2_TXD - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 136: GPIO_NC, /* GPIO_S0_SC[076] SIO_UART2_RTS# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 137: GPIO_NC, /* GPIO_S0_SC[077] SIO_UART2_CTS# - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 138: GPIO_FUNC1, /* GPIO_S0_SC[078] SIO_I2C0_DATA - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 139: GPIO_FUNC1, /* GPIO_S0_SC[079] SIO_I2C0_CLK - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 140: GPIO_NC, /* GPIO_S0_SC[080] SIO_I2C1_DATA - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 141: GPIO_NC, /* GPIO_S0_SC[081] SIO_I2C1_CLK RESERVED - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 142: GPIO_FUNC1, /* GPIO_S0_SC[082] SIO_I2C2_DATA - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 143: GPIO_FUNC1, /* GPIO_S0_SC[083] SIO_I2C2_CLK - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 144: GPIO_NC, /* GPIO_S0_SC[084] SIO_I2C3_DATA - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 145: GPIO_NC, /* GPIO_S0_SC[085] SIO_I2C3_CLK - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 146: GPIO_NC, /* GPIO_S0_SC[086] SIO_I2C4_DATA - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 147: GPIO_NC, /* GPIO_S0_SC[087] SIO_I2C4_CLK - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 148: GPIO_NC, /* GPIO_S0_SC[088] SIO_I2C5_DATA - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 149: GPIO_NC, /* GPIO_S0_SC[089] SIO_I2C5_CLK - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 150: GPIO_NC, /* GPIO_S0_SC[090] SIO_I2C6_DATA ILB_NMI - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 151: GPIO_NC, /* GPIO_S0_SC[091] SIO_I2C6_CLK SD3_WP - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 152: GPIO_NC, /* RESERVED GPIO_S0_SC[092] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 153: GPIO_NC, /* RESERVED GPIO_S0_SC[093] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 154: GPIO_NC, /* GPIO_S0_SC[094] SIO_PWM[0] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 155: GPIO_NC, /* GPIO_S0_SC[095] SIO_PWM[1] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 156: GPIO_NC, /* GPIO_S0_SC[096] PMC_PLT_CLK[0] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 157: GPIO_NC, /* GPIO_S0_SC[097] PMC_PLT_CLK[1] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 158: GPIO_NC, /* GPIO_S0_SC[098] PMC_PLT_CLK[2] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 159: GPIO_NC, /* GPIO_S0_SC[099] PMC_PLT_CLK[3] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 160: GPIO_NC, /* GPIO_S0_SC[100] PMC_PLT_CLK[4] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 161: GPIO_NC, /* GPIO_S0_SC[101] PMC_PLT_CLK[5] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 167: GPIO_DEFAULT, /* GPIO_S5[00] RESERVED - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 168: GPIO_NC, /* GPIO_S5[01] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[1]# */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 169: GPIO_DEFAULT, /* GPIO_S5[02] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[2]# */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 170: GPIO_DEFAULT, /* GPIO_S5[03] RESERVED RESERVED RESERVED PMC_WAKE_PCIE[3]# */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 171: GPIO_DEFAULT, /* GPIO_S5[04] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 172: GPIO_DEFAULT, /* GPIO_S5[05] PMC_SUSCLK[1] RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 173: GPIO_DEFAULT, /* GPIO_S5[06] PMC_SUSCLK[2] RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 174: GPIO_DEFAULT, /* GPIO_S5[07] PMC_SUSCLK[3] RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 175: GPIO_DEFAULT, /* GPIO_S5[08] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 176: GPIO_NC, /* GPIO_S5[09] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 177: GPIO_NC, /* GPIO_S5[10] RESERVED RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 178: GPIO_DEFAULT, /* PMC_SUSPWRDNACK GPIO_S5[11] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 179: GPIO_NC, /* PMC_SUSCLK[0] GPIO_S5[12] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 180: GPIO_NC, /* RESERVED GPIO_S5[13] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 181: GPIO_FUNC2, /* RESERVED GPIO_S5[14] USB_ULPI_RST# - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 182: GPIO_FUNC0, /* PMC_WAKE_PCIE[0]# GPIO_S5[15] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 183: GPIO_FUNC0, /* PMC_PWRBTN# GPIO_S5[16] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 184: GPIO_FUNC1, /* RESERVED GPIO_S5[17] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 185: GPIO_FUNC0, /* PMC_SUS_STAT# GPIO_S5[18] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 186: GPIO_FUNC0, /* USB_OC[0]# GPIO_S5[19] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 187: GPIO_FUNC0, /* USB_OC[1]# GPIO_S5[20] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 188: GPIO_NC, /* PCU_SPI_CS[1]# GPIO_S5[21] - - - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 189: GPIO_NC, /* GPIO_S5[22] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 190: GPIO_NC, /* GPIO_S5[23] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 191: GPIO_NC, /* GPIO_S5[24] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 192: GPIO_DEFAULT, /* GPIO_S5[25] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 193: GPIO_NC, /* GPIO_S5[26] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 194: GPIO_NC, /* GPIO_S5[27] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 195: GPIO_NC, /* GPIO_S5[28] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 196: GPIO_NC, /* GPIO_S5[29] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 197: GPIO_NC, /* GPIO_S5[30] RESERVED RESERVED RESERVED RESERVED */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 198: GPIO_FUNC1, /* GPIO_S5[31] USB_ULPI_CLK RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 199: GPIO_NC, /* GPIO_S5[32] USB_ULPI_DATA[0] RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 200: GPIO_NC, /* GPIO_S5[33] USB_ULPI_DATA[1] RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 201: GPIO_NC, /* GPIO_S5[34] USB_ULPI_DATA[2] RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 202: GPIO_NC, /* GPIO_S5[35] USB_ULPI_DATA[3] RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 203: GPIO_NC, /* GPIO_S5[36] USB_ULPI_DATA[4] RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 204: GPIO_NC, /* GPIO_S5[37] USB_ULPI_DATA[5] RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 205: GPIO_NC, /* GPIO_S5[38] USB_ULPI_DATA[6] RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 206: GPIO_NC, /* GPIO_S5[39] USB_ULPI_DATA[7] RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 207: GPIO_NC, /* GPIO_S5[40] USB_ULPI_DIR RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 208: GPIO_NC, /* GPIO_S5[41] USB_ULPI_NXT RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 209: GPIO_NC, /* GPIO_S5[42] USB_ULPI_STP RESERVED RESERVED - */ line over 80 characters https://review.coreboot.org/#/c/22924/23/src/mainboard/opencellular/rotundu… PS23, Line 210: GPIO_NC, /* GPIO_S5[43] USB_ULPI_REFCLK RESERVED RESERVED - */ line over 80 characters -- To view, visit https://review.coreboot.org/22924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id20e9d4ed7ac071d25a69eee63c9ec544d2ad152 Gerrit-Change-Number: 22924 Gerrit-PatchSet: 23 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Reg Orton <reg(a)brck.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Jul 2018 16:34:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: opencellular/rotundu: Add LPC TPM support
by Philipp Deppenwiese (Code Review) 28 Jul '18

28 Jul '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/22829 ) Change subject: opencellular/rotundu: Add LPC TPM support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/22829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I4154841de553d198d5a5d113e31b7be14a12dcd0 Gerrit-Change-Number: 22829 Gerrit-PatchSet: 22 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Bernard Adongo <bernard(a)brck.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reg Orton <reg(a)brck.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: nb/intel/sandybridge/report_platform: Move remaining code to sb folder
by Felix Held (Code Review) 28 Jul '18

28 Jul '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/27667 ) Change subject: nb/intel/sandybridge/report_platform: Move remaining code to sb folder ...................................................................... nb/intel/sandybridge/report_platform: Move remaining code to sb folder Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/27667 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/raminit.c D src/northbridge/intel/sandybridge/report_platform.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/lpc.c 5 files changed, 71 insertions(+), 95 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 9673cd1..304ea30 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -46,7 +46,6 @@ romstage-y += romstage.c romstage-y += iommu.c romstage-y += early_init.c -romstage-y += report_platform.c romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c0f9c6f..47474ee 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -323,8 +323,6 @@ MCHBAR32(0x5f00) |= 1; - report_platform_info(); - /* Wait for ME to be ready */ intel_early_me_init(); me_uma_size = intel_early_me_uma_size(); diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c deleted file mode 100644 index 7e647d8..0000000 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "sandybridge.h" - -static struct { - u16 dev_id; - const char *dev_name; -} pch_table [] = { - /* 6-series PCI ids from - * Intel® 6 Series Chipset and - * Intel® C200 Series Chipset - * Specification Update - NDA - * October 2013 - * CDI / IBP#: 440377 - */ - {0x1C41, "SFF Sample"}, - {0x1C42, "Desktop Sample"}, - {0x1C43, "Mobile Sample"}, - {0x1C44, "Z68"}, - {0x1C46, "P67"}, - {0x1C47, "UM67"}, - {0x1C49, "HM65"}, - {0x1C4A, "H67"}, - {0x1C4B, "HM67"}, - {0x1C4C, "Q65"}, - {0x1C4D, "QS67"}, - {0x1C4E, "Q67"}, - {0x1C4F, "QM67"}, - {0x1C50, "B65"}, - {0x1C52, "C202"}, - {0x1C54, "C204"}, - {0x1C56, "C206"}, - {0x1C5C, "H61"}, - /* 7-series PCI ids from Intel document 472178 */ - {0x1E41, "Desktop Sample"}, - {0x1E42, "Mobile Sample"}, - {0x1E43, "SFF Sample"}, - {0x1E44, "Z77"}, - {0x1E45, "H71"}, - {0x1E46, "Z75"}, - {0x1E47, "Q77"}, - {0x1E48, "Q75"}, - {0x1E49, "B75"}, - {0x1E4A, "H77"}, - {0x1E53, "C216"}, - {0x1E55, "QM77"}, - {0x1E56, "QS77"}, - {0x1E58, "UM77"}, - {0x1E57, "HM77"}, - {0x1E59, "HM76"}, - {0x1E5D, "HM75"}, - {0x1E5E, "HM70"}, - {0x1E5F, "NM70"}, -}; - -static void report_pch_info(void) -{ - int i; - u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2); - - - const char *pch_type = "Unknown"; - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].dev_id == dev_id) { - pch_type = pch_table[i].dev_name; - break; - } - } - printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n", - pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8)); -} - -void report_platform_info(void) -{ - report_pch_info(); -} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 3269605..693bfb7 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -217,7 +217,6 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); -void report_platform_info(void); #endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 611b08f..d9e72b4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> @@ -500,10 +501,80 @@ RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */ } +static const struct { + u16 dev_id; + const char *dev_name; +} pch_table[] = { + /* 6-series PCI ids from + * Intel® 6 Series Chipset and + * Intel® C200 Series Chipset + * Specification Update - NDA + * October 2013 + * CDI / IBP#: 440377 + */ + {0x1C41, "SFF Sample"}, + {0x1C42, "Desktop Sample"}, + {0x1C43, "Mobile Sample"}, + {0x1C44, "Z68"}, + {0x1C46, "P67"}, + {0x1C47, "UM67"}, + {0x1C49, "HM65"}, + {0x1C4A, "H67"}, + {0x1C4B, "HM67"}, + {0x1C4C, "Q65"}, + {0x1C4D, "QS67"}, + {0x1C4E, "Q67"}, + {0x1C4F, "QM67"}, + {0x1C50, "B65"}, + {0x1C52, "C202"}, + {0x1C54, "C204"}, + {0x1C56, "C206"}, + {0x1C5C, "H61"}, + /* 7-series PCI ids from Intel document 472178 */ + {0x1E41, "Desktop Sample"}, + {0x1E42, "Mobile Sample"}, + {0x1E43, "SFF Sample"}, + {0x1E44, "Z77"}, + {0x1E45, "H71"}, + {0x1E46, "Z75"}, + {0x1E47, "Q77"}, + {0x1E48, "Q75"}, + {0x1E49, "B75"}, + {0x1E4A, "H77"}, + {0x1E53, "C216"}, + {0x1E55, "QM77"}, + {0x1E56, "QS77"}, + {0x1E58, "UM77"}, + {0x1E57, "HM77"}, + {0x1E59, "HM76"}, + {0x1E5D, "HM75"}, + {0x1E5E, "HM70"}, + {0x1E5F, "NM70"}, +}; + +static void report_pch_info(struct device *dev) +{ + const u16 dev_id = pci_read_config16(dev, PCI_DEVICE_ID); + int i; + + const char *pch_type = "Unknown"; + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].dev_id == dev_id) { + pch_type = pch_table[i].dev_name; + break; + } + } + printk(BIOS_INFO, "PCH: detected %s, device id: 0x%x, rev id 0x%x\n", + pch_type, dev_id, pci_read_config8(dev, PCI_CLASS_REVISION)); +} + static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); + /* Print detected platform */ + report_pch_info(dev); + /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); -- To view, visit https://review.coreboot.org/27667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Gerrit-Change-Number: 27667 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/sandybridge: Move CPU report to cpu folder
by Felix Held (Code Review) 28 Jul '18

28 Jul '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/27666 ) Change subject: nb/intel/sandybridge: Move CPU report to cpu folder ...................................................................... nb/intel/sandybridge: Move CPU report to cpu folder Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/27666 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/intel/model_206ax/model_206ax_init.c M src/northbridge/intel/sandybridge/report_platform.c 2 files changed, 27 insertions(+), 46 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 4be3d87..75631c1 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -498,9 +498,33 @@ } } +static void model_206ax_report(void) +{ + static const char *const mode[] = {"NOT ", ""}; + struct cpuid_result cpuidr; + char processor_name[49]; + int vt, txt, aes; + + /* Print processor name */ + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); + + /* Print platform ID */ + printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id()); + + /* CPUID and features */ + cpuidr = cpuid(1); + printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpuidr.eax); + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + printk(BIOS_INFO, "CPU: AES %ssupported\n", mode[aes]); + printk(BIOS_INFO, "CPU: TXT %ssupported\n", mode[txt]); + printk(BIOS_INFO, "CPU: VT %ssupported\n", mode[vt]); +} + static void model_206ax_init(struct device *cpu) { - char processor_name[49]; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -510,12 +534,8 @@ /* Clear out pending MCEs */ configure_mca(); - /* Print processor name */ - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - - /* Print platform ID */ - printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id()); + /* Print infos */ + model_206ax_report(); /* Setup MTRRs based on physical address size */ x86_setup_mtrrs_with_detect(); diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 6dd760d..7e647d8 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -14,47 +14,9 @@ */ #include <console/console.h> -#include <arch/cpu.h> -#include <string.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <arch/io.h> #include "sandybridge.h" -static void report_cpu_info(void) -{ - struct cpuid_result cpuidr; - u32 i, index; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ - int vt, txt, aes; - const char *mode[] = {"NOT ", ""}; - - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - u32 *p = (u32*) cpu_string; - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - *p++ = cpuidr.eax; - *p++ = cpuidr.ebx; - *p++ = cpuidr.ecx; - *p++ = cpuidr.edx; - } - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; - - cpuidr = cpuid(1); - printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_name); - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; - printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); -} - static struct { u16 dev_id; const char *dev_name; @@ -125,6 +87,5 @@ void report_platform_info(void) { - report_cpu_info(); report_pch_info(); } -- To view, visit https://review.coreboot.org/27666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Gerrit-Change-Number: 27666 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit July 2018