coreboot-gerrit July 2018

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Change in coreboot[master]: sandybridge/raminit_common: use MCHBAR32 macro everywhere
by Patrick Rudolph (Code Review) 28 Jul '18

28 Jul '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/27674 ) Change subject: sandybridge/raminit_common: use MCHBAR32 macro everywhere ...................................................................... Patch Set 3: Code-Review+2 Tested on HP8200, still boots and shows all memory DIMMs. -- To view, visit https://review.coreboot.org/27674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Gerrit-Change-Number: 27674 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Jul 2018 15:25:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Add TCPA logging functionality
by build bot (Jenkins) (Code Review) 28 Jul '18

28 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22867 ) Change subject: security/tpm: Add TCPA logging functionality ...................................................................... Patch Set 36: (2 comments) https://review.coreboot.org/#/c/22867/36/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/22867/36/src/security/tpm/tspi/log.c@61 PS36, Line 61: trailing whitespace https://review.coreboot.org/#/c/22867/36/src/security/tpm/tspi/log.c@61 PS36, Line 61: please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/22867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a52494f647d21e2587231af26ed13d62b3a72f5 Gerrit-Change-Number: 22867 Gerrit-PatchSet: 36 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Jul 2018 15:23:23 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: sandybridge/raminit_common: use MCHBAR32 macro everywhere
by Felix Held (Code Review) 28 Jul '18

28 Jul '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27674 ) Change subject: sandybridge/raminit_common: use MCHBAR32 macro everywhere ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/27674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Gerrit-Change-Number: 27674 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Jul 2018 15:05:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Tuning of Fan speed
by Sumeet R Pawnikar (Code Review) 28 Jul '18

28 Jul '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/27683 Change subject: mb/google/poppy/variants/nami: Tuning of Fan speed ...................................................................... mb/google/poppy/variants/nami: Tuning of Fan speed Tuning of Fan speed for different Temperature values BUG=None. TEST=Verified on Nami Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/27683/1 diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl index a83fe17..614865a 100644 --- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl @@ -62,10 +62,15 @@ */ /* Control, Trip Point, Speed, NoiseLevel, Power */ Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {69, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {56, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {46, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {36, 0xFFFFFFFF, 3900, 90, 900} + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} }) Name (DART, Package () { -- To view, visit https://review.coreboot.org/27683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876 Gerrit-Change-Number: 27683 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: sandybridge/raminit: use MCHBAR32 macro everywhere
by Felix Held (Code Review) 28 Jul '18

28 Jul '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27675 ) Change subject: sandybridge/raminit: use MCHBAR32 macro everywhere ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/27675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Gerrit-Change-Number: 27675 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Jul 2018 14:07:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/parrot/smihandler: Use new PMBASE API
by Arthur Heymans (Code Review) 28 Jul '18

28 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27679 ) Change subject: mb/google/parrot/smihandler: Use new PMBASE API ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e Gerrit-Change-Number: 27679 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 28 Jul 2018 13:12:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macros
by Felix Held (Code Review) 28 Jul '18

28 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27682 Change subject: sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macros ...................................................................... sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macros Change-Id: If8b8fd123e0dd15a0fc9dfe178076f8541e29d56 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/sandybridge.h 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/27682/1 diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 5772962..6ab9491 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -120,9 +120,9 @@ * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) #define SSKPD 0x5d14 /* 16bit (scratchpad) */ @@ -132,9 +132,9 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) -#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) -#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -163,9 +163,9 @@ * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) -#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ -- To view, visit https://review.coreboot.org/27682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If8b8fd123e0dd15a0fc9dfe178076f8541e29d56 Gerrit-Change-Number: 27682 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp
by Charles Marslett (Code Review) 28 Jul '18

28 Jul '18

Hello Charles Marslett, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27681 to look at the new patch set (#3). Change subject: Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp ...................................................................... Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp Eliminate the last references to PspBaseLib.c, PspBaseLib.h and agesa_wrapper.h in psp.c and move definitions used in coreboot/src/soc/amd/common/block/psp/psp.c to a new file, coreboot/src/soc/amd/common/block/psp/psp.h. The removal of the files' usage, and potentially the removal of the PspBaseLib.* files themselves will be in a second patch. BUG=b:78514564 TEST=Build and boot grunt/ChromeOS and restore an image from the internet. Change-Id: Ib21954a82827b5bb5854fa9a6672376c9bbb6539 Signed-off-by: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/psp/psp.c A src/soc/amd/common/block/psp/psp.h 2 files changed, 173 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/27681/3 -- To view, visit https://review.coreboot.org/27681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib21954a82827b5bb5854fa9a6672376c9bbb6539 Gerrit-Change-Number: 27681 Gerrit-PatchSet: 3 Gerrit-Owner: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> Gerrit-Reviewer: Charles Marslett <charles.marslett(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp
by Charles Marslett (Code Review) 28 Jul '18

28 Jul '18

Hello Charles Marslett, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27681 to look at the new patch set (#2). Change subject: Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp ...................................................................... Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp Eliminate the last references to PspBaseLib.c, PspBaseLib.h and agesa_wrapper.h in psp.c and move definitions used in coreboot/src/soc/amd/common/block/psp/psp.c to a new file, coreboot/src/soc/amd/common/block/psp/psp.h. The removal of the files' usage, and potentially the removal of the PspBaseLib.* files themselves will be in a second patch. BUG=b:78514564 TEST=Build and boot grunt/ChromeOS and restore an image from the internet. Change-Id: Ib21954a82827b5bb5854fa9a6672376c9bbb6539 Signed-off-by: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/psp/psp.c A src/soc/amd/common/block/psp/psp.h 2 files changed, 170 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/27681/2 -- To view, visit https://review.coreboot.org/27681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib21954a82827b5bb5854fa9a6672376c9bbb6539 Gerrit-Change-Number: 27681 Gerrit-PatchSet: 2 Gerrit-Owner: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> Gerrit-Reviewer: Charles Marslett <charles.marslett(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp
by Charles Marslett (Code Review) 28 Jul '18

28 Jul '18

Charles Marslett has uploaded this change for review. ( https://review.coreboot.org/27681 Change subject: Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp ...................................................................... Remove use of coreboot/src/vendorcode/amd/pi/00670F00/Proc/Psp Eliminate the last references to PspBaseLib.c, PspBaseLib.h and agesa_wrapper.h in psp.c and move definitions used in coreboot/src/soc/amd/common/block/psp/psp.c to a new file, coreboot/src/soc/amd/common/block/psp/psp.h. The removal of the files' usage, and potentially the removal of the PspBaseLib.* files themselves will be in a second patch. BUG=b:78514564 TEST=Build and boot grunt/ChromeOS and restore an image from the internet. Change-Id: Ib21954a82827b5bb5854fa9a6672376c9bbb6539 Signed-off-by: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/psp/psp.c A src/soc/amd/common/block/psp/psp.h 2 files changed, 171 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/27681/1 diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index a1a0e5b..b94fb67 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -9,7 +9,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ @@ -20,7 +20,10 @@ #include <device/pci_def.h> #include <bootstate.h> #include <console/console.h> +#include <device/pci_ops.h> #include <amdblocks/psp.h> +#include <soc/iomap.h> +#include "psp.h" static const char *psp_status_nobase = "error: PSP BAR3 not assigned"; static const char *psp_status_halted = "error: PSP in halted state"; @@ -30,6 +33,121 @@ static const char *psp_status_cmd_timeout = "error: PSP command timeout"; static const char *psp_status_noerror = ""; +//static bool psp_bar_init_early(VOID); + +/** + Attempt to perform a very early initialization of the PSP device + BAR3 register. + + @retval bool 0: Error, 1 Success +**/ +static bool +psp_bar_init_early(VOID) +{ + u32 psp_mmio_size; + u32 value32; + PCI_ADDR pci_addr; + + printk(BIOS_DEBUG, "PSP: %s() called...\n", __func__); + + value32 = pci_read_config32(SOC_PSP_DEV, PSP_PCI_DEVID_REG); + if (value32 == 0xffffffff) { + printk(BIOS_DEBUG, "PSP: No device at PSP Seg/Bus/Dev/FUNC...\n"); + return FALSE; + } + + /* + * Check if PSP BAR has been assigned, + * if not do the PSP BAR initialization + */ + value32 = pci_read_config32(SOC_PSP_DEV, PSP_PCI_BAR3_REG); + if ((value32 & ~0x0F) == 0) { + printk(BIOS_DEBUG, "PSP: BAR3 value is zero...\n"); + /// Get PSP BAR3 Size + pci_write_config32(SOC_PSP_DEV, PSP_PCI_BAR3_REG, + (u32)0xFFFFFFFF); + psp_mmio_size = ~pci_read_config32(SOC_PSP_DEV, + PSP_PCI_BAR3_REG) + 1; + printk(BIOS_DEBUG, "PSP: BAR3 size is 0x%x...\n", + psp_mmio_size); + /// Assign BAR3 Temporary Address + pci_write_config32(SOC_PSP_DEV, PSP_PCI_BAR3_REG, + PSP_MAILBOX_BAR3_BASE); + /// Enable Access + pci_write_config32(SOC_PSP_DEV, PSP_PCI_CMD_REG, 0x06); + printk(BIOS_DEBUG, "PSP: BAR3 set to 0x%x, CMD=0x%x zero...\n", + (unsigned int)pci_read_config32(SOC_PSP_DEV, + PSP_PCI_BAR3_REG), + (unsigned int)pci_read_config32(SOC_PSP_DEV, + PSP_PCI_CMD_REG)); + + /* + * Enable GNB redirection to this space + * @todo use equate & also find proper fix + */ + pci_addr.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xBC); + value32 = ((PSP_MAILBOX_BAR3_BASE + psp_mmio_size - 1) >> 8) + & ~0xFF; + LibAmdPciWrite(AccessWidth32, pci_addr, &value32, NULL); + + pci_addr.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8); + value32 = (PSP_MAILBOX_BAR3_BASE >> 8) | 3; + LibAmdPciWrite(AccessWidth32, pci_addr, &value32, NULL); + + /// Enable MsixBarEn, Bar1En, Bar3En + pci_write_config32(SOC_PSP_DEV, PSP_PCI_EXTRAPCIHDR_REG, + 0x34); + + /// Capability chain update + value32 = pci_read_config32(SOC_PSP_DEV, + PSP_PCI_MIRRORCTRL1_REG); + value32 &= ~D8F0x44_PmNxtPtrW_MASK; + value32 |= 0xA4; + pci_write_config32(SOC_PSP_DEV, PSP_PCI_MIRRORCTRL1_REG, + value32); + } + return TRUE; +} + +/** + * Return the psp MMIO buffer location + * + * @param[in] psp_mmio Pointer to Psp MMIO address + * + * @retval bool 0: Error, 1 Success +**/ +static bool get_psp_bar3_addr(u32 *psp_mmio) +{ + u32 value32; + + pci_write_config32(SOC_PSP_DEV, PCI_CONFIG_SMU_INDIRECT_INDEX, + SMU_CC_PSP_FUSES_STATUS); + value32 = pci_read_config32(SOC_PSP_DEV, PCI_CONFIG_SMU_INDIRECT_DATA); + if ((value32 & SMU_CC_PSP_FUSES_PROTO) != 0) { + printk(BIOS_DEBUG, "PSP: %s(): SMU_CC_PSP_FUSES_PROTO = 0 - FALSE...\n", + __func__); + return FALSE; + } + + // D8F0x48[12] Bar3Hide + if (pci_read_config32(SOC_PSP_DEV, PSP_PCI_EXTRAPCIHDR_REG) + & BAR3HIDEBIT) { + printk(BIOS_DEBUG, "PSP: D8F0x48[12]/Bar3Hidden...\n"); + *psp_mmio = (u32)__readmsr(MSR_CU_CBBCFG); + if (*psp_mmio == 0xFFFFFFFF) { + printk(BIOS_DEBUG, + "PSP: Msr psp_mmio = 0xFFFFFFFF - ret. FALSE...\n"); + return FALSE; + } + printk(BIOS_DEBUG, "PSP: BAR3 = 0x%x ...\n", *psp_mmio); + } else { + *psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_PCI_BAR3_REG) & + 0xFFF00000; + printk(BIOS_DEBUG, "PSP: Read BAR3 = 0x%x ...\n", *psp_mmio); + } + return TRUE; +} + static const char *status_to_string(int err) { switch (err) { @@ -52,20 +170,25 @@ static struct psp_mbox *get_mbox_address(void) { - UINT32 base; /* UINT32 for compatibility with PspBaseLib */ - BOOLEAN bar3_status; + u32 base; /* u32 for compatibility with PspBaseLib */ uintptr_t baseptr; - bar3_status = GetPspBar3Addr(&base); - if (!bar3_status) { - PspBarInitEarly(); - bar3_status = GetPspBar3Addr(&base); + if (!get_psp_bar3_addr(&base)) { + printk(BIOS_DEBUG, + "PSP: %s(), get_psp_bar3_addr() returned FALSE, base=0x%x...\n", + __func__, base); + psp_bar_init_early(); + if (!get_psp_bar3_addr(&base)) { + printk(BIOS_DEBUG, + "PSP: %s(), get_psp_bar3_addr returned FALSE, base=0x%x...\n", + __func__, base); + return NULL; + } } - if (!bar3_status) - return NULL; - - baseptr = base; - return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE); + baseptr = (uintptr_t)base + PSP_MAILBOX_BASE; + printk(BIOS_DEBUG, "PSP: %s() = 0x%p...\n", + __func__, (struct psp_mbox *)baseptr); + return ((struct psp_mbox *)baseptr); } static u32 rd_mbox_sts(struct psp_mbox *mbox) @@ -157,7 +280,7 @@ } /* - * Notify the PSP that DRAM is present. Upon receiving this command, the PSP + * Notify the PSP that DRAM is present. Upon receiving this command, the PSP * will load its OS into fenced DRAM that is not accessible to the x86 cores. */ int psp_notify_dram(void) diff --git a/src/soc/amd/common/block/psp/psp.h b/src/soc/amd/common/block/psp/psp.h new file mode 100644 index 0000000..dd6159b --- /dev/null +++ b/src/soc/amd/common/block/psp/psp.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Registers in the PSP PCI Config Space + +#define PSP_PCI_DEVID_REG 0x00 ///< Standard Pci Device ID +#define PSP_PCI_CMD_REG 0x04 ///< CmdReg +#define PSP_PCI_BAR3_REG 0x20 ///< Pci Bar3 +#define PSP_PCI_MIRRORCTRL1_REG 0x44 ///< PSP Mirror Reg Ctrl +#define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr +#define PCI_CONFIG_SMU_INDIRECT_INDEX 0xB8 ///< Gnb index for SMU mbox +#define PCI_CONFIG_SMU_INDIRECT_DATA 0xBC ///< Gnb data for SMU mbox + +// GNB related offsets and bit specifications + +#define SMU_CC_PSP_FUSES_STATUS 0xC0018000ul ///< GNB offset to find PSP fusing +#define SMU_CC_PSP_FUSES_PROTO BIT2 ///< BIT2 + +// PSP Mailbox definitions +#define PSP_MAILBOX_BASE 0x70 ///< Mailbox offset from PCIe BAR + +#define MSR_CU_CBBCFG 0xC00110A2ul ///< PSP Private Blk Base Addr + -- To view, visit https://review.coreboot.org/27681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib21954a82827b5bb5854fa9a6672376c9bbb6539 Gerrit-Change-Number: 27681 Gerrit-PatchSet: 1 Gerrit-Owner: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> Gerrit-Reviewer: Charles Marslett <charles.marslett(a)silverbackltd.com>

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coreboot-gerrit July 2018