coreboot-gerrit July 2018

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Change in coreboot[master]: pnp_device: don't treat missing PNP_MSC devicetree entry as error
by Patrick Rudolph (Code Review) 27 Jul '18

27 Jul '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/27668 ) Change subject: pnp_device: don't treat missing PNP_MSC devicetree entry as error ...................................................................... Patch Set 1: Code-Review+2 Tested on HP8200. -- To view, visit https://review.coreboot.org/27668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a Gerrit-Change-Number: 27668 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Jul 2018 17:31:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/bd82x6x: Fix watchdog
by Felix Held (Code Review) 27 Jul '18

27 Jul '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27669 ) Change subject: sb/intel/bd82x6x: Fix watchdog ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512 Gerrit-Change-Number: 27669 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Jul 2018 17:07:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/bd82x6x: Fix watchdog
by Patrick Rudolph (Code Review) 27 Jul '18

27 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27669 Change subject: sb/intel/bd82x6x: Fix watchdog ...................................................................... sb/intel/bd82x6x: Fix watchdog * Fix comments * Use defines instead of magic values * Use new PMBASE API to modify registers Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/watchdog.c 2 files changed, 24 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27669/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7c7e0ed..65aac55 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -503,9 +503,12 @@ #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 +#define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +#define SECOND_TO_STS (1 << 1) #define TCO1_CNT 0x68 +#define TCO_TMR_HLT (1 << 11) #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c index 9a867e4..eb4d38c 100644 --- a/src/southbridge/intel/bd82x6x/watchdog.c +++ b/src/southbridge/intel/bd82x6x/watchdog.c @@ -19,37 +19,38 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> +#include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/bd82x6x/pch.h> + #include <watchdog.h> - // - // Disable PCH Watchdog timer at SB_RCBA+0x3410 - // - // Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20; - // +/* + * Disable PCH watchdog timer + */ void watchdog_off(void) { + unsigned int value; struct device *dev; - unsigned long value, base; - /* Turn off the ICH7 watchdog. */ + /* Get LPC device. */ dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + /* Disable interrupt. */ + value = pci_read_config16(dev, PCI_COMMAND); + value |= PCI_COMMAND_INT_DISABLE; + pci_write_config16(dev, PCI_COMMAND, value); /* Disable the watchdog timer. */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); + value = read_pmbase16(TCO1_CNT); + value |= TCO_TMR_HLT; + write_pmbase16(TCO1_CNT, value); /* Clear TCO timeout status. */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); + write_pmbase16(TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(TCO2_STS, SECOND_TO_STS); - printk(BIOS_DEBUG, "PCH watchdog disabled\n"); + /* FIXME: Set RCBA GCS Bit5 "No Reboot" ? */ + + printk(BIOS_DEBUG, "PCH: watchdog disabled\n"); } -- To view, visit https://review.coreboot.org/27669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idd2ded19e528427db29fa87d87481b91bae2b512 Gerrit-Change-Number: 27669 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: nb/intel/sandybridge/report_platform: Move remaining code to sb folder
by Felix Held (Code Review) 27 Jul '18

27 Jul '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27667 ) Change subject: nb/intel/sandybridge/report_platform: Move remaining code to sb folder ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Gerrit-Change-Number: 27667 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Jul 2018 16:14:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/sandybridge: Move CPU report to cpu folder
by Felix Held (Code Review) 27 Jul '18

27 Jul '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/27666 ) Change subject: nb/intel/sandybridge: Move CPU report to cpu folder ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Gerrit-Change-Number: 27666 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Jul 2018 16:12:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: pnp_device: don't treat missing PNP_MSC devicetree entry as error
by Felix Held (Code Review) 27 Jul '18

27 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27668 Change subject: pnp_device: don't treat missing PNP_MSC devicetree entry as error ...................................................................... pnp_device: don't treat missing PNP_MSC devicetree entry as error Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/pnp_device.c 1 file changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27668/1 diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 09a2748..e56b00d 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -118,9 +118,21 @@ static void pnp_set_resource(struct device *dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " - "not assigned\n", dev_path(dev), resource->index, - resource_type(resource), resource->size); + /* The PNP_MSC super IO registers have the IRQ flag set. If no + value is assigned in the devicetree, the corresponding + PNP_MSC register doesn't get written, which should be printed + as warning and not as error. */ + if (resource->flags & IORESOURCE_IRQ && + (resource->index != PNP_IDX_IRQ0) && + (resource->index != PNP_IDX_IRQ1)) + printk(BIOS_WARNING, "WARNING: %s %02lx %s size: " + "0x%010llx not assigned\n", dev_path(dev), + resource->index, resource_type(resource), + resource->size); + else + printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " + "not assigned\n", dev_path(dev), resource->index, + resource_type(resource), resource->size); return; } -- To view, visit https://review.coreboot.org/27668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a Gerrit-Change-Number: 27668 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: nb/intel/sandybridge: Move CPU report to cpu folder
by Patrick Rudolph (Code Review) 27 Jul '18

27 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27666 Change subject: nb/intel/sandybridge: Move CPU report to cpu folder ...................................................................... nb/intel/sandybridge: Move CPU report to cpu folder Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/model_206ax/model_206ax_init.c M src/northbridge/intel/sandybridge/report_platform.c 2 files changed, 27 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27666/1 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 4be3d87..75631c1 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -498,9 +498,33 @@ } } +static void model_206ax_report(void) +{ + static const char *const mode[] = {"NOT ", ""}; + struct cpuid_result cpuidr; + char processor_name[49]; + int vt, txt, aes; + + /* Print processor name */ + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); + + /* Print platform ID */ + printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id()); + + /* CPUID and features */ + cpuidr = cpuid(1); + printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpuidr.eax); + aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; + txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; + vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; + printk(BIOS_INFO, "CPU: AES %ssupported\n", mode[aes]); + printk(BIOS_INFO, "CPU: TXT %ssupported\n", mode[txt]); + printk(BIOS_INFO, "CPU: VT %ssupported\n", mode[vt]); +} + static void model_206ax_init(struct device *cpu) { - char processor_name[49]; /* Turn on caching if we haven't already */ x86_enable_cache(); @@ -510,12 +534,8 @@ /* Clear out pending MCEs */ configure_mca(); - /* Print processor name */ - fill_processor_name(processor_name); - printk(BIOS_INFO, "CPU: %s.\n", processor_name); - - /* Print platform ID */ - printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id()); + /* Print infos */ + model_206ax_report(); /* Setup MTRRs based on physical address size */ x86_setup_mtrrs_with_detect(); diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 6dd760d..7e647d8 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -14,47 +14,9 @@ */ #include <console/console.h> -#include <arch/cpu.h> -#include <string.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <arch/io.h> #include "sandybridge.h" -static void report_cpu_info(void) -{ - struct cpuid_result cpuidr; - u32 i, index; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ - int vt, txt, aes; - const char *mode[] = {"NOT ", ""}; - - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - u32 *p = (u32*) cpu_string; - for (i = 2; i <= 4; i++) { - cpuidr = cpuid(index + i); - *p++ = cpuidr.eax; - *p++ = cpuidr.ebx; - *p++ = cpuidr.ecx; - *p++ = cpuidr.edx; - } - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; - - cpuidr = cpuid(1); - printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_name); - aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; - txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; - vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; - printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); -} - static struct { u16 dev_id; const char *dev_name; @@ -125,6 +87,5 @@ void report_platform_info(void) { - report_cpu_info(); report_pch_info(); } -- To view, visit https://review.coreboot.org/27666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie973923b90eca0bfabd474fed85a6cc33fce7e19 Gerrit-Change-Number: 27666 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: nb/intel/sandybridge/report_platform: Move remaining code to sb folder
by Patrick Rudolph (Code Review) 27 Jul '18

27 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27667 Change subject: nb/intel/sandybridge/report_platform: Move remaining code to sb folder ...................................................................... nb/intel/sandybridge/report_platform: Move remaining code to sb folder Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/raminit.c D src/northbridge/intel/sandybridge/report_platform.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/lpc.c 5 files changed, 71 insertions(+), 95 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/27667/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 9673cd1..304ea30 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -46,7 +46,6 @@ romstage-y += romstage.c romstage-y += iommu.c romstage-y += early_init.c -romstage-y += report_platform.c romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c0f9c6f..47474ee 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -323,8 +323,6 @@ MCHBAR32(0x5f00) |= 1; - report_platform_info(); - /* Wait for ME to be ready */ intel_early_me_init(); me_uma_size = intel_early_me_uma_size(); diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c deleted file mode 100644 index 7e647d8..0000000 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include "sandybridge.h" - -static struct { - u16 dev_id; - const char *dev_name; -} pch_table [] = { - /* 6-series PCI ids from - * Intel® 6 Series Chipset and - * Intel® C200 Series Chipset - * Specification Update - NDA - * October 2013 - * CDI / IBP#: 440377 - */ - {0x1C41, "SFF Sample"}, - {0x1C42, "Desktop Sample"}, - {0x1C43, "Mobile Sample"}, - {0x1C44, "Z68"}, - {0x1C46, "P67"}, - {0x1C47, "UM67"}, - {0x1C49, "HM65"}, - {0x1C4A, "H67"}, - {0x1C4B, "HM67"}, - {0x1C4C, "Q65"}, - {0x1C4D, "QS67"}, - {0x1C4E, "Q67"}, - {0x1C4F, "QM67"}, - {0x1C50, "B65"}, - {0x1C52, "C202"}, - {0x1C54, "C204"}, - {0x1C56, "C206"}, - {0x1C5C, "H61"}, - /* 7-series PCI ids from Intel document 472178 */ - {0x1E41, "Desktop Sample"}, - {0x1E42, "Mobile Sample"}, - {0x1E43, "SFF Sample"}, - {0x1E44, "Z77"}, - {0x1E45, "H71"}, - {0x1E46, "Z75"}, - {0x1E47, "Q77"}, - {0x1E48, "Q75"}, - {0x1E49, "B75"}, - {0x1E4A, "H77"}, - {0x1E53, "C216"}, - {0x1E55, "QM77"}, - {0x1E56, "QS77"}, - {0x1E58, "UM77"}, - {0x1E57, "HM77"}, - {0x1E59, "HM76"}, - {0x1E5D, "HM75"}, - {0x1E5E, "HM70"}, - {0x1E5F, "NM70"}, -}; - -static void report_pch_info(void) -{ - int i; - u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2); - - - const char *pch_type = "Unknown"; - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].dev_id == dev_id) { - pch_type = pch_table[i].dev_name; - break; - } - } - printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n", - pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8)); -} - -void report_platform_info(void) -{ - report_pch_info(); -} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 3269605..693bfb7 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -217,7 +217,6 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); -void report_platform_info(void); #endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 611b08f..d9e72b4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> @@ -500,10 +501,80 @@ RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */ } +static const struct { + u16 dev_id; + const char *dev_name; +} pch_table[] = { + /* 6-series PCI ids from + * Intel® 6 Series Chipset and + * Intel® C200 Series Chipset + * Specification Update - NDA + * October 2013 + * CDI / IBP#: 440377 + */ + {0x1C41, "SFF Sample"}, + {0x1C42, "Desktop Sample"}, + {0x1C43, "Mobile Sample"}, + {0x1C44, "Z68"}, + {0x1C46, "P67"}, + {0x1C47, "UM67"}, + {0x1C49, "HM65"}, + {0x1C4A, "H67"}, + {0x1C4B, "HM67"}, + {0x1C4C, "Q65"}, + {0x1C4D, "QS67"}, + {0x1C4E, "Q67"}, + {0x1C4F, "QM67"}, + {0x1C50, "B65"}, + {0x1C52, "C202"}, + {0x1C54, "C204"}, + {0x1C56, "C206"}, + {0x1C5C, "H61"}, + /* 7-series PCI ids from Intel document 472178 */ + {0x1E41, "Desktop Sample"}, + {0x1E42, "Mobile Sample"}, + {0x1E43, "SFF Sample"}, + {0x1E44, "Z77"}, + {0x1E45, "H71"}, + {0x1E46, "Z75"}, + {0x1E47, "Q77"}, + {0x1E48, "Q75"}, + {0x1E49, "B75"}, + {0x1E4A, "H77"}, + {0x1E53, "C216"}, + {0x1E55, "QM77"}, + {0x1E56, "QS77"}, + {0x1E58, "UM77"}, + {0x1E57, "HM77"}, + {0x1E59, "HM76"}, + {0x1E5D, "HM75"}, + {0x1E5E, "HM70"}, + {0x1E5F, "NM70"}, +}; + +static void report_pch_info(struct device *dev) +{ + const u16 dev_id = pci_read_config16(dev, PCI_DEVICE_ID); + int i; + + const char *pch_type = "Unknown"; + for (i = 0; i < ARRAY_SIZE(pch_table); i++) { + if (pch_table[i].dev_id == dev_id) { + pch_type = pch_table[i].dev_name; + break; + } + } + printk(BIOS_INFO, "PCH: detected %s, device id: 0x%x, rev id 0x%x\n", + pch_type, dev_id, pci_read_config8(dev, PCI_CLASS_REVISION)); +} + static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); + /* Print detected platform */ + report_pch_info(dev); + /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); -- To view, visit https://review.coreboot.org/27667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Gerrit-Change-Number: 27667 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: mb/pcengines/apu2: correct GPIO and LED setting
by build bot (Jenkins) (Code Review) 27 Jul '18

27 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27665 ) Change subject: mb/pcengines/apu2: correct GPIO and LED setting ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/27665/2/src/mainboard/pcengines/apu2/romsta… File src/mainboard/pcengines/apu2/romstage.c: https://review.coreboot.org/#/c/27665/2/src/mainboard/pcengines/apu2/romsta… PS2, Line 116: if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Gerrit-Change-Number: 27665 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Jul 2018 14:22:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/pcengines/apu2: correct GPIO and LED setting
by Michał Żygowski (Code Review) 27 Jul '18

27 Jul '18

Hello Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27665 to look at the new patch set (#2). Change subject: mb/pcengines/apu2: correct GPIO and LED setting ...................................................................... mb/pcengines/apu2: correct GPIO and LED setting Due to vendor's requirements LED 2 and LED3 should be turned off in late boot process. Add appropriate functions to read status. Change GPIO setting to use IOMUX to refer to GPIO by IOMUX register as in BKDG. Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/gpio_ftns.h M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/pcengines/apu2/romstage.c 4 files changed, 71 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27665/2 -- To view, visit https://review.coreboot.org/27665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Gerrit-Change-Number: 27665 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit July 2018