coreboot-gerrit July 2018

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Change in coreboot[master]: mainboard/google/kahlee: Pad SPD serial Number with spaces
by Martin Roth (Code Review) 28 Jul '18

28 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27676 Change subject: mainboard/google/kahlee: Pad SPD serial Number with spaces ...................................................................... mainboard/google/kahlee: Pad SPD serial Number with spaces All of the other SPDs are padded with spaces to make them use the full size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not, and that seems to be causing problems with some tools. BUG=b:111903749 TEST=Mosys correctly identifies memory on board using that SPD. Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/27676/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex index 1bcc1f1..3d046a3 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5AN8G6NCJR-VKC.spd.hex @@ -20,7 +20,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36 -4E 43 4A 52 2D 56 4B 43 00 00 00 00 00 00 00 00 +4E 43 4A 52 2D 56 4B 43 20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/27676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12 Gerrit-Change-Number: 27676 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: sandybridge/raminit: use MCHBAR32 macro everywhere
by Felix Held (Code Review) 28 Jul '18

28 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27675 Change subject: sandybridge/raminit: use MCHBAR32 macro everywhere ...................................................................... sandybridge/raminit: use MCHBAR32 macro everywhere Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/27675/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index e566057..05efa47 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -337,10 +337,10 @@ wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); - reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000 + reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000 if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ && reg_5d10 && !s3resume) { - write32(DEFAULT_MCHBAR + 0x5d10, 0); + MCHBAR32(0x5d10) = 0; /* Need reset. */ outb(0x6, 0xcf9); @@ -442,7 +442,7 @@ die("raminit failed"); /* FIXME: should be hardware revision-dependent. */ - write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce); + MCHBAR32(0x5024) = 0x00a030ce; set_scrambling_seed(&ctrl); -- To view, visit https://review.coreboot.org/27675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I42d97d278c81ce2cfd0010830c2e0bacddd947d6 Gerrit-Change-Number: 27675 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

1 0

Change in coreboot[master]: andybridge/raminit_common: use MCHBAR32 macro consistently
by Felix Held (Code Review) 28 Jul '18

28 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27674 Change subject: andybridge/raminit_common: use MCHBAR32 macro consistently ...................................................................... andybridge/raminit_common: use MCHBAR32 macro consistently Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 542 insertions(+), 662 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27674/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 44f7f6d..2a5f09c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -72,10 +72,10 @@ static void toggle_io_reset(void) { /* toggle IO reset bit */ - u32 r32 = read32(DEFAULT_MCHBAR + 0x5030); - write32(DEFAULT_MCHBAR + 0x5030, r32 | 0x20); + u32 r32 = MCHBAR32(0x5030); + MCHBAR32(0x5030) = r32 | 0x20; udelay(1); - write32(DEFAULT_MCHBAR + 0x5030, r32 & ~0x20); + MCHBAR32(0x5030) = r32 & ~0x20; udelay(1); } @@ -623,7 +623,7 @@ static void wait_428c(int channel) { while (1) { - if (read32(DEFAULT_MCHBAR + 0x428c + (channel << 10)) & 0x50) + if (MCHBAR32(0x428c + (channel << 10)) & 0x50) return; } } @@ -641,15 +641,14 @@ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; /* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x80c01); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x80c01; - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4210 + 0x400 * channel) = 0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x400001); + MCHBAR32(0x4284 + 0x400 * channel) = 0x400001; wait_428c(channel); } @@ -736,27 +735,26 @@ } /* DRAM command MRS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | (reg << 20) | val | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f000; + MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | (reg << 20) | val | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0; /* DRAM command MRS */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x41001); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | (reg << 20) | val | 0x60000); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4234 + 0x400 * channel) = 0x41001; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | (reg << 20) | val | 0x60000; + MCHBAR32(0x4214 + 0x400 * channel) = 0; /* DRAM command MRS */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x0f000); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | (reg << 20) | val | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001); + MCHBAR32(0x4228 + 0x400 * channel) = 0x0f000; + MCHBAR32(0x4238 + 0x400 * channel) = 0x1001 | (ctrl->tMOD << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | (reg << 20) | val | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0; + MCHBAR32(0x4284 + 0x400 * channel) = 0x80001; } static u32 make_mr0(ramctr_timing * ctrl, u8 rank) @@ -789,8 +787,7 @@ static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) { - write_mrreg(ctrl, channel, rank, 0, - make_mr0(ctrl, rank)); + write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); } static u32 encode_odt(u32 odt) @@ -880,19 +877,19 @@ } /* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4e20, 0x7); - write32(DEFAULT_MCHBAR + 0x4e30, 0xf1001); - write32(DEFAULT_MCHBAR + 0x4e00, 0x60002); - write32(DEFAULT_MCHBAR + 0x4e10, 0); + MCHBAR32(0x4e20) = 0x7; + MCHBAR32(0x4e30) = 0xf1001; + MCHBAR32(0x4e00) = 0x60002; + MCHBAR32(0x4e10) = 0; /* DRAM command ZQCL */ - write32(DEFAULT_MCHBAR + 0x4e24, 0x1f003); - write32(DEFAULT_MCHBAR + 0x4e34, 0x1901001); - write32(DEFAULT_MCHBAR + 0x4e04, 0x60400); - write32(DEFAULT_MCHBAR + 0x4e14, 0x288); + MCHBAR32(0x4e24) = 0x1f003; + MCHBAR32(0x4e34) = 0x1901001; + MCHBAR32(0x4e04) = 0x60400; + MCHBAR32(0x4e14) = 0x288; /* execute command queue on all channels ? */ - write32(DEFAULT_MCHBAR + 0x4e84, 0x40004); + MCHBAR32(0x4e84) = 0x40004; // Drain FOR_ALL_CHANNELS { @@ -917,12 +914,12 @@ wait_428c(channel); /* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x1); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x659001; + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; + MCHBAR32(0x4284 + 0x400 * channel) = 0x1; // Drain wait_428c(channel); @@ -967,8 +964,7 @@ case 3: slot320c[slot] = (ctrl->timings[channel][2 * slot].val_320c + - ctrl->timings[channel][2 * slot + - 1].val_320c) / 2 + + ctrl->timings[channel][2 * slot + 1].val_320c) / 2 + full_shift; break; } @@ -1088,37 +1084,31 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - (0xc01 | (ctrl->tMOD << 16))); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = (0xc01 | (ctrl->tMOD << 16)); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x4040c01); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4040c01; + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4214 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x100f | ((ctrl->CAS + 36) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = 0x100f | ((ctrl->CAS + 36) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0; /* DRAM command MRS * write MR3 MPR disable */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - (0xc01 | (ctrl->tMOD << 16))); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); } @@ -1127,8 +1117,7 @@ int lane) { u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; - return ((read32 - (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + + return ((MCHBAR32(lane_registers[lane] + channel * 0x100 + 4 + ((timA / 32) & 1) * 4) >> (timA % 32)) & 1); } @@ -1200,7 +1189,7 @@ if (upperA[lane] < rn.middle) upperA[lane] += 128; printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, slotrank, lane, rn.start, rn.middle, rn.end); } } @@ -1222,8 +1211,8 @@ test_timA(ctrl, channel, slotrank); FOR_ALL_LANES { statistics[lane][timA_delta + 25] += - does_lane_work(ctrl, channel, slotrank, - lane); + does_lane_work(ctrl, channel, slotrank, + lane); } } } @@ -1371,34 +1360,32 @@ int upperA[NUM_LANES]; struct timA_minmax mnmx; - wait_428c(channel); + wait_428c(channel); - /* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + /* DRAM command PREA */ + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; + MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + 0x400 * channel) = 0; + MCHBAR32(0x4284 + 0x400 * channel) = 1; - write32(DEFAULT_MCHBAR + 0x3400, (slotrank << 2) | 0x8001); + MCHBAR32(0x3400) = (slotrank << 2) | 0x8001; - ctrl->timings[channel][slotrank].val_4028 = 4; - ctrl->timings[channel][slotrank].val_4024 = 55; - program_timings(ctrl, channel); + ctrl->timings[channel][slotrank].val_4028 = 4; + ctrl->timings[channel][slotrank].val_4024 = 55; + program_timings(ctrl, channel); - discover_timA_coarse(ctrl, channel, slotrank, upperA); + discover_timA_coarse(ctrl, channel, slotrank, upperA); - all_high = 1; - some_high = 0; - FOR_ALL_LANES { - if (ctrl->timings[channel][slotrank].lanes[lane]. - timA >= 0x40) - some_high = 1; - else - all_high = 0; - } + all_high = 1; + some_high = 0; + FOR_ALL_LANES { + if (ctrl->timings[channel][slotrank].lanes[lane].timA >= + 0x40) + some_high = 1; + else + all_high = 0; + } if (all_high) { ctrl->timings[channel][slotrank].val_4028--; @@ -1446,11 +1433,11 @@ printram("final results:\n"); FOR_ALL_LANES - printram("Aval: %d, %d, %d: %x\n", channel, slotrank, - lane, - ctrl->timings[channel][slotrank].lanes[lane].timA); + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, + lane, + ctrl->timings[channel][slotrank].lanes[lane].timA); - write32(DEFAULT_MCHBAR + 0x3400, 0); + MCHBAR32(0x3400) = 0; toggle_io_reset(); } @@ -1459,8 +1446,7 @@ program_timings(ctrl, channel); } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel - + 4 * lane, 0); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -1470,82 +1456,75 @@ int lane; FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + 4 * lane, 0); - read32(DEFAULT_MCHBAR + 0x4140 + 0x400 * channel + 4 * lane); + volatile u32 tmp; + MCHBAR32(0x4340 + 0x400 * channel + 4 * lane) = 0; + tmp = MCHBAR32(0x4140 + 0x400 * channel + 4 * lane); } wait_428c(channel); /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) - | 4 | (ctrl->tRCD << 16)); + | 4 | (ctrl->tRCD << 16); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | (6 << 16)); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); + MCHBAR32(0x4210 + 0x400 * channel) = 0x244; /* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8041001); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 8); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207; + MCHBAR32(0x4234 + 0x400 * channel) = 0x8041001; + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 8; + MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0; /* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x80411f4); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4238 + 0x400 * channel) = 0x80411f4; + MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; + MCHBAR32(0x4218 + 0x400 * channel) = 0x242; /* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 8); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f207; + MCHBAR32(0x423c + 0x400 * channel) = + 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 8; + MCHBAR32(0x421c + 0x400 * channel) = 0x3e0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); /* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; + MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + 0x400 * channel) = 0x240; /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4234 + 0x400 * channel) = (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) - | 8 | (ctrl->CAS << 16)); + | 8 | (ctrl->CAS << 16); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x244); + MCHBAR32(0x4214 + 0x400 * channel) = 0x244; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x40011f4 | (max(ctrl->tRTP, 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x242); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x40011f4 | (max(ctrl->tRTP, 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4218 + 0x400 * channel) = 0x242; /* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; + MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + 0x400 * channel) = 0x240; + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); } @@ -1558,13 +1537,11 @@ wait_428c(channel); /* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; + MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + 0x400 * channel) = 0x240; + MCHBAR32(0x4284 + 0x400 * channel) = 1; for (timC = 0; timC <= MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. @@ -1575,8 +1552,7 @@ FOR_ALL_LANES { statistics[lane][timC] = - read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane + - 0x400 * channel); + MCHBAR32(0x4340 + 4 * lane + 0x400 * channel); } } FOR_ALL_LANES { @@ -1589,7 +1565,7 @@ return MAKE_ERR; } printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", - channel, slotrank, lane, rn.start, rn.middle, rn.end); + channel, slotrank, lane, rn.start, rn.middle, rn.end); } return 0; } @@ -1654,43 +1630,37 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4041003); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | 0; + MCHBAR32(0x4214 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0; /* DRAM command MRS * write MR3 MPR disable */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); } @@ -1710,45 +1680,39 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4041003); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | 0; + MCHBAR32(0x4214 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0; /* DRAM command MRS * write MR3 MPR disable */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); } } @@ -1762,22 +1726,20 @@ wait_428c(channel); /* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - 8 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f207; + MCHBAR32(0x4230 + 0x400 * channel) = + 0x8000c01 | ((ctrl->CWL + ctrl->tWLO) << 16); + MCHBAR32(0x4200 + 0x400 * channel) = 8 | (slotrank << 24); + MCHBAR32(0x4210 + 0x400 * channel) = 0; /* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f107); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4000c01 | ((ctrl->CAS + 38) << 16)); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 4); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f107; + MCHBAR32(0x4234 + 0x400 * channel) = + 0x4000c01 | ((ctrl->CAS + 38) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 4; + MCHBAR32(0x4214 + 0x400 * channel) = 0; - write32(DEFAULT_MCHBAR + 0x400 * channel + 0x4284, 0x40001); + MCHBAR32(0x400 * channel + 0x4284) = 0x40001; wait_428c(channel); /* disable DQs on this slotrank */ @@ -1791,7 +1753,7 @@ int statistics[NUM_LANES][128]; int lane; - write32(DEFAULT_MCHBAR + 0x3400, 0x108052 | (slotrank << 2)); + MCHBAR32(0x3400) = 0x108052 | (slotrank << 2); for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { @@ -1803,8 +1765,7 @@ FOR_ALL_LANES { statistics[lane][timB] = - !((read32 - (DEFAULT_MCHBAR + lane_registers[lane] + + !((MCHBAR32(lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); } @@ -1861,87 +1822,76 @@ static void adjust_high_timB(ramctr_timing * ctrl) { int channel, slotrank, lane, old; - write32(DEFAULT_MCHBAR + 0x3400, 0x200); + MCHBAR32(0x3400) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); - write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 1); + MCHBAR32(0x4288 + (channel << 10)) = 1; } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x10001); + MCHBAR32(x4288 + 0x400 * channel) = 0x10001; wait_428c(channel); /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tRCD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRCD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0; /* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x8040c01); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0x8); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f207; + MCHBAR32(0x4234 + 0x400 * channel) = 0x8040c01; + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x8; + MCHBAR32(0x4214 + 0x400 * channel) = 0x3e0; /* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f201); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, 0x8041003); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x3e2); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4238 + 0x400 * channel) = 0x8041003; + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4218 + 0x400 * channel) = 0x3e2; /* DRAM command NOP */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f207); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x8); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x3e0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f207; + MCHBAR32(0x423c + 0x400 * channel) = + 0x8000c01 | ((ctrl->CWL + ctrl->tWTR + 5) << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x8; + MCHBAR32(0x421c + 0x400 * channel) = 0x3e0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); /* DRAM command PREA */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | ((ctrl->tRP) << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x240); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | ((ctrl->tRP) << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(0x4210 + 0x400 * channel) = 0x240; /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0xc01 | ((ctrl->tRCD) << 16)); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4234 + 0x400 * channel) = + 0xc01 | ((ctrl->tRCD) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4214 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x3f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x4000c01 | - ((ctrl->tRP + + MCHBAR32(0x4228 + 0x400 * channel) = 0x3f105; + MCHBAR32(0x4238 + 0x400 * channel) = 0x4000c01 | ((ctrl->tRP + ctrl->timings[channel][slotrank].val_4024 + - ctrl->timings[channel][slotrank].val_4028) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60008); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + ctrl->timings[channel][slotrank].val_4028) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60008; + MCHBAR32(0x4218 + 0x400 * channel) = 0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0x80001); + MCHBAR32(0x4284 + 0x400 * channel) = 0x80001; wait_428c(channel); FOR_ALL_LANES { - u64 res = - read32(DEFAULT_MCHBAR + lane_registers[lane] + - 0x100 * channel + 4); - res |= - ((u64) read32(DEFAULT_MCHBAR + lane_registers[lane] + - 0x100 * channel + 8)) << 32; + u64 res = MCHBAR32(lane_registers[lane] + + 0x100 * channel + 4); + res |= ((u64) MCHBAR32(lane_registers[lane] + + 0x100 * channel + 8)) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].timB; ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; @@ -1953,7 +1903,7 @@ timB); } } - write32(DEFAULT_MCHBAR + 0x3400, 0); + MCHBAR32(0x3400) = 0; } static void write_op(ramctr_timing * ctrl, int channel) @@ -1966,15 +1916,14 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4284 + 0x400 * channel) = 1; wait_428c(channel); } @@ -1994,21 +1943,20 @@ { int channel, slotrank, lane; int err; + volatile u32 tmp; FOR_ALL_POPULATED_CHANNELS - write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4008 + - 0x400 * channel) | 0x8000000); + MCHBAR32(0x4008 + 0x400 * channel) = + MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000; FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4020 + - 0x400 * channel) | 0x200000); + MCHBAR32(0x4020 + 0x400 * channel) = + MCHBAR32(0x4020 + 0x400 * channel) | 0x200000; } /* refresh disable */ - write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8); + MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8; FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -2017,11 +1965,11 @@ * disable all DQ outputs * only NOP is allowed in this mode */ FOR_ALL_CHANNELS - FOR_ALL_POPULATED_RANKS - write_mrreg(ctrl, channel, slotrank, 1, - make_mr1(ctrl, slotrank, channel) | 0x1080); + FOR_ALL_POPULATED_RANKS + write_mrreg(ctrl, channel, slotrank, 1, + make_mr1(ctrl, slotrank, channel) | 0x1080); - write32(DEFAULT_MCHBAR + 0x3400, 0x108052); + MCHBAR32(0x3400) = 0x108052; toggle_io_reset(); @@ -2035,30 +1983,29 @@ /* disable write leveling on all ranks */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS write_mrreg(ctrl, channel, - slotrank, 1, make_mr1(ctrl, slotrank, channel)); + slotrank, 1, make_mr1(ctrl, slotrank, channel)); - write32(DEFAULT_MCHBAR + 0x3400, 0); + MCHBAR32(0x3400) = 0; FOR_ALL_POPULATED_CHANNELS wait_428c(channel); /* refresh enable */ - write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) | 8); + MCHBAR32(0x5030) = MCHBAR32(0x5030) | 8; FOR_ALL_POPULATED_CHANNELS { - write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, - ~0x00200000 & read32(DEFAULT_MCHBAR + 0x4020 + - 0x400 * channel)); - read32(DEFAULT_MCHBAR + 0x428c + 0x400 * channel); + MCHBAR32(0x4020 + 0x400 * channel) = + ~0x00200000 & MCHBAR32(0x4020 + 0x400 * channel); + tmp = MCHBAR32(0x428c + 0x400 * channel); wait_428c(channel); /* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x659001); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x659001; + MCHBAR32(0x4200 + 0x400 * channel) = 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4284 + 0x400 * channel) = 1; wait_428c(channel); } @@ -2069,14 +2016,13 @@ printram("CPF\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane); - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, - 0); + tmp = MCHBAR32(0x4080 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); - write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); + MCHBAR32(0x4288 + (channel << 10)) = 0; } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2095,9 +2041,8 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane); - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, - 0); + tmp = MCHBAR32(0x4080 + 0x400 * channel + 4 * lane); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -2117,53 +2062,48 @@ } program_timings(ctrl, channel); FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 4 * lane + 0x4f40, 0); + MCHBAR32(4 * lane + 0x4f40) = 0; } - write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); + MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; wait_428c(channel); /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) - | 8 | (ctrl->tRCD << 16)); + | 8 | (ctrl->tRCD << 16); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | ctr | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | ctr | 0x60000; - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); + MCHBAR32(0x4210 + 0x400 * channel) = 0x244; /* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4244 + 0x400 * channel, 0x389abcd); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0x20e42); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4234 + 0x400 * channel) = + 0x8001020 | ((ctrl->CWL + ctrl->tWTR + 8) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4244 + 0x400 * channel) = 0x389abcd; + MCHBAR32(0x4214 + 0x400 * channel) = 0x20e42; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x4001020 | (max(ctrl->tRTP, 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4248 + 0x400 * channel, 0x389abcd); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0x20e42); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x4001020 | (max(ctrl->tRTP, 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24); + MCHBAR32(0x4248 + 0x400 * channel) = 0x389abcd; + MCHBAR32(0x4218 + 0x400 * channel) = 0x20e42; /* DRAM command PRE */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, 0xf1001); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0x240); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; + MCHBAR32(0x423c + 0x400 * channel) = 0xf1001; + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + 0x400 * channel) = 0x240; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); FOR_ALL_LANES { - u32 r32 = - read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane + - 0x400 * channel); + u32 r32 = MCHBAR32(0x4340 + 4 * lane + 0x400 * channel); if (r32 == 0) lanes_ok |= 1 << lane; @@ -2221,23 +2161,21 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4284 + 0x400 * channel) = 1; wait_428c(channel); - write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4020 + - 0x400 * channel) | 0x200000); + MCHBAR32(0x4020 + 0x400 * channel) = + MCHBAR32(0x4020 + 0x400 * channel) | 0x200000; } /* refresh disable */ - write32(DEFAULT_MCHBAR + 0x5030, read32(DEFAULT_MCHBAR + 0x5030) & ~8); + MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8; FOR_ALL_POPULATED_CHANNELS { wait_428c(channel); @@ -2245,15 +2183,14 @@ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; /* DRAM command ZQCS */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f003); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); + MCHBAR32(0x4220 + 0x400 * channel) = 0x0f003; + MCHBAR32(0x4230 + 0x400 * channel) = 0x41001; - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60000; - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x3e0); + MCHBAR32(0x4210 + 0x400 * channel) = 0x3e0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 1); + MCHBAR32(0x4284 + 0x400 * channel) = 1; wait_428c(channel); } @@ -2316,8 +2253,7 @@ FOR_ALL_POPULATED_RANKS { struct run rn = get_longest_zero_run(stat[slotrank], 255); - ctrl->timings[channel][slotrank].val_320c = - rn.middle - 127; + ctrl->timings[channel][slotrank].val_320c = rn.middle - 127; printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, rn.start, rn.middle, rn.end); if (rn.all || rn.length < MIN_C320C_LEN) { @@ -2341,7 +2277,7 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern5(ctrl, channel, 0); - write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); + MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; } FOR_ALL_POPULATED_CHANNELS { @@ -2405,10 +2341,9 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + - 4 * lane, 0); - read32(DEFAULT_MCHBAR + 0x400 * channel + 4 * lane + - 0x4140); + volatile u32 tmp; + MCHBAR32(0x4340 + 0x400 * channel + 4 * lane = 0; + tmp = MCHBAR32(0x400 * channel + 4 * lane + 0x4140); } wait_428c(channel); @@ -2416,45 +2351,41 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - (0xc01 | (ctrl->tMOD << 16))); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, 0x40411f4); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x40411f4; + MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24; + MCHBAR32(0x4214 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0; /* DRAM command MRS * MR3 disable MPR */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - (0xc01 | (ctrl->tMOD << 16))); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); FOR_ALL_LANES { statistics[lane][edge] = - read32(DEFAULT_MCHBAR + 0x4340 + 0x400 * channel + - lane * 4); + MCHBAR32(0x4340 + 0x400 * channel + lane * 4); } } FOR_ALL_LANES { @@ -2479,21 +2410,20 @@ int channel, slotrank, lane; int err; - write32(DEFAULT_MCHBAR + 0x3400, 0); + MCHBAR32(0x3400) = 0; toggle_io_reset(); FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 4 * lane + - 0x400 * channel + 0x4080, 0); + MCHBAR32(4 * lane + 0x400 * channel + 0x4080) = 0; } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0, 0); - write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); + MCHBAR32(0x4288 + (channel << 10)) = 0; FOR_ALL_LANES { - read32(DEFAULT_MCHBAR + 0x400 * channel + - lane * 4 + 0x4140); + volatile u32 tmp; + tmp = MCHBAR32(0x400 * channel + lane * 4 + 0x4140); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2513,43 +2443,37 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4041003); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | 0; + MCHBAR32(0x4214 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0; /* DRAM command MRS * MR3 disable MPR */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0; + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); } @@ -2573,72 +2497,65 @@ * write MR3 MPR enable * in this mode only RD and RDA are allowed * all reads return a predefined pattern */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x360004); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000; + MCHBAR32(0x4230 + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x360004; + MCHBAR32(0x4210 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x4041003); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24) | 0); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, 0); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4234 + 0x400 * channel) = 0x4041003; + MCHBAR32(0x4204 + 0x400 * channel) = + (slotrank << 24) | 0; + MCHBAR32(0x4214 + 0x400 * channel) = 0; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x1001 | ((ctrl->CAS + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, 0); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4218 + 0x400 * channel) = 0; /* DRAM command MRS * MR3 disable MPR */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f000); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tMOD << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x360000); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tMOD << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x360000; + MCHBAR32(0x421c + 0x400 * channel) = 0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); } /* XXX: check any measured value ? */ FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + - lane * 4, - ~read32(DEFAULT_MCHBAR + 0x4040 + - 0x400 * channel + lane * 4) & 0xff); + MCHBAR32(0x4080 + 0x400 * channel + lane * 4) = + MCHBAR32(0x4040 + 0x400 * channel + lane * 4) + & 0xff; } fill_pattern0(ctrl, channel, 0, 0xffffffff); - write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); + MCHBAR32(0x4288 + (channel << 10)) = 0; } /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ - write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + MCHBAR32(0x4eb0) = 0x300; printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { err = discover_edges_real(ctrl, channel, slotrank, - falling_edges[channel][slotrank]); + falling_edges[channel][slotrank]); if (err) return err; } - write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + MCHBAR32(0x4eb0) = 0x200; printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2648,7 +2565,7 @@ return err; } - write32(DEFAULT_MCHBAR + 0x4eb0, 0); + MCHBAR32(0x4eb0) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = @@ -2662,8 +2579,7 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, - 0); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -2679,6 +2595,7 @@ int lower[NUM_LANES]; int upper[NUM_LANES]; int pat; + volatile u32 tmp; FOR_ALL_LANES { lower[lane] = 0; @@ -2686,13 +2603,12 @@ } for (i = 0; i < 3; i++) { - write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel, - reg3000b24[i] << 24); + MCHBAR32(0x3000 + 0x100 * channel) = reg3000b24[i] << 24; printram("[%x] = 0x%08x\n", 0x3000 + 0x100 * channel, reg3000b24[i] << 24); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); - write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); + MCHBAR32(0x4288 + 0x400 * channel) = 0x1f; printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { @@ -2704,60 +2620,51 @@ program_timings(ctrl, channel); FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4340 + - 0x400 * channel + 4 * lane, 0); - read32(DEFAULT_MCHBAR + 0x400 * channel + - 4 * lane + 0x4140); + MCHBAR32(0x4340 + 0x400 * channel + + 4 * lane) = 0; + tmp = MCHBAR32(0x400 * channel + + 4 * lane + 0x4140); } wait_428c(channel); /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, - 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, - 0x4 | (ctrl->tRCD << 16) - | (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << - 10)); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, - 0x240); + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = + 0x4 | (ctrl->tRCD << 16) | + (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) + << 10); + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0x240; /* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, - 0x1f201); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x8005020 | ((ctrl->tWTR + ctrl->CWL + 8) << - 16)); - write32(DEFAULT_MCHBAR + 0x4204 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + 0x400 * channel, - 0x242); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4234 + 0x400 * channel) = 0x8005020 | + ((ctrl->tWTR + ctrl->CWL + 8) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = + slotrank << 24; + MCHBAR32(0x4214 + 0x400 * channel) = 0x242; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + 0x400 * channel, - 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + 0x400 * channel, - 0x4005020 | (max(ctrl->tRTP, 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + 0x400 * channel, - (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + 0x400 * channel, - 0x242); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x4005020 | (max(ctrl->tRTP, 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = + slotrank << 24; + MCHBAR32(0x4218 + 0x400 * channel) = 0x242; /* DRAM command PRE */ - write32(DEFAULT_MCHBAR + 0x422c + 0x400 * channel, - 0x1f002); - write32(DEFAULT_MCHBAR + 0x423c + 0x400 * channel, - 0xc01 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x420c + 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x421c + 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; + MCHBAR32(0x423c + 0x400 * channel) = + 0xc01 | (ctrl->tRP << 16); + MCHBAR32(0x420c + 0x400 * channel) = + (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + 0x400 * channel) = 0; - write32(DEFAULT_MCHBAR + 0x4284 + 0x400 * channel, - 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); FOR_ALL_LANES { - read32(DEFAULT_MCHBAR + 0x4340 + + tmp = MCHBAR32(0x4340 + 0x400 * channel + lane * 4); } @@ -2789,7 +2696,7 @@ } } - write32(DEFAULT_MCHBAR + 0x3000, 0); + MCHBAR32(0x3000) = 0; printram("CPA\n"); return 0; } @@ -2802,7 +2709,7 @@ int err; /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ - write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + MCHBAR32(0x4eb0) = 0x300; printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2812,7 +2719,7 @@ return err; } - write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + MCHBAR32(0x4eb0) = 0x200; printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2822,7 +2729,7 @@ return err; } - write32(DEFAULT_MCHBAR + 0x4eb0, 0); + MCHBAR32(0x4eb0) = 0; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].falling = @@ -2835,8 +2742,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane, - 0); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } return 0; } @@ -2845,49 +2751,35 @@ { wait_428c(channel); /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x1f006); - write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, + MCHBAR32(0x4220 + 0x400 * channel) = 0x1f006; + MCHBAR32(0x4230 + 0x400 * channel) = (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) - << 10) | (ctrl->tRCD << 16) | 4); - write32(DEFAULT_MCHBAR + 0x4200 + 0x400 * channel, - (slotrank << 24) | 0x60000); - write32(DEFAULT_MCHBAR + 0x4210 + 0x400 * channel, 0x244); + << 10) | (ctrl->tRCD << 16) | 4; + MCHBAR32(0x4200 + 0x400 * channel) = + (slotrank << 24) | 0x60000; + MCHBAR32(0x4210 + 0x400 * channel) = 0x244; /* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4224 + 0x400 * channel, 0x1f201); - write32(DEFAULT_MCHBAR + 0x4234 + 0x400 * channel, - 0x80011e0 | - ((ctrl->tWTR + ctrl->CWL + 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4204 + - 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + - 0x400 * channel, 0x242); + MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; + MCHBAR32(0x4234 + 0x400 * channel) = + 0x80011e0 | ((ctrl->tWTR + ctrl->CWL + 8) << 16); + MCHBAR32(0x4204 + 0x400 * channel) = slotrank << 24; + MCHBAR32(0x4214 + 0x400 * channel) = 0x242; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + - 0x400 * channel, 0x1f105); - write32(DEFAULT_MCHBAR + 0x4238 + - 0x400 * channel, - 0x40011e0 | (max(ctrl->tRTP, 8) << 16)); - write32(DEFAULT_MCHBAR + 0x4208 + - 0x400 * channel, (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + - 0x400 * channel, 0x242); + MCHBAR32(0x4228 + 0x400 * channel) = 0x1f105; + MCHBAR32(0x4238 + 0x400 * channel) = + 0x40011e0 | (max(ctrl->tRTP, 8) << 16); + MCHBAR32(0x4208 + 0x400 * channel) = slotrank << 24; + MCHBAR32(0x4218 + 0x400 * channel) = 0x242; /* DRAM command PRE */ - write32(DEFAULT_MCHBAR + 0x422c + - 0x400 * channel, 0x1f002); - write32(DEFAULT_MCHBAR + 0x423c + - 0x400 * channel, - 0x1001 | (ctrl->tRP << 16)); - write32(DEFAULT_MCHBAR + 0x420c + - 0x400 * channel, - (slotrank << 24) | 0x60400); - write32(DEFAULT_MCHBAR + 0x421c + - 0x400 * channel, 0); + MCHBAR32(0x422c + 0x400 * channel) = 0x1f002; + MCHBAR32(0x423c + 0x400 * channel) = 0x1001 | (ctrl->tRP << 16); + MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x421c + 0x400 * channel) = 0; - write32(DEFAULT_MCHBAR + 0x4284 + - 0x400 * channel, 0xc0001); + MCHBAR32(0x4284 + 0x400 * channel) = 0xc0001; wait_428c(channel); } @@ -2905,15 +2797,15 @@ upper[channel][slotrank][lane] = MAX_TIMC; } - write32(DEFAULT_MCHBAR + 0x4ea8, 1); + MCHBAR32(0x4ea8) = 1; printram("discover timC write:\n"); for (i = 0; i < 3; i++) FOR_ALL_POPULATED_CHANNELS { - write32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100), - (rege3c_b24[i] << 24) - | (read32(DEFAULT_MCHBAR + 0xe3c + (channel * 0x100)) - & ~0x3f000000)); + MCHBAR32(0xe3c + (channel * 0x100)) = + (rege3c_b24[i] << 24) | + (MCHBAR32(0xe3c + (channel * 0x100)) + & ~0x3f000000) udelay(2); for (pat = 0; pat < NUM_PATTERNS; pat++) { FOR_ALL_POPULATED_RANKS { @@ -2925,7 +2817,8 @@ statistics[MAX_TIMC] = 1; fill_pattern5(ctrl, channel, pat); - write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); + MCHBAR32(0x4288 + 0x400 * channel) = + 0x1f; for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; @@ -2968,13 +2861,12 @@ } FOR_ALL_CHANNELS { - write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c, - 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) & - ~0x3f000000)); + MCHBAR32((channel * 0x100) + 0xe3c) = + 0 | (MCHBAR32((channel * 0x100) + 0xe3c) & ~0x3f000000); udelay(2); } - write32(DEFAULT_MCHBAR + 0x4ea8, 0); + MCHBAR32(0x4ea8) = 0; printram("CPB\n"); @@ -3024,11 +2916,10 @@ int channel, slotrank; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - write32(DEFAULT_MCHBAR + 0x0004 + (channel << 8) + - lane_registers[slotrank], make_mr0(ctrl, slotrank)); - write32(DEFAULT_MCHBAR + 0x0008 + (channel << 8) + - lane_registers[slotrank], - make_mr1(ctrl, slotrank, channel)); + MCHBAR32(0x0004 + (channel << 8) + lane_registers[slotrank]) = + make_mr0(ctrl, slotrank); + MCHBAR32(0x0008 + (channel << 8) + lane_registers[slotrank]) = + make_mr1(ctrl, slotrank, channel); } } @@ -3038,7 +2929,7 @@ slotrank = 0; FOR_ALL_POPULATED_CHANNELS - if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) { + if (MCHBAR32(0x42a0 + (channel << 10)) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); return MAKE_ERR; @@ -3046,45 +2937,45 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); - write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0); + MCHBAR32(0x4288 + (channel << 10)) = 0; } for (slotrank = 0; slotrank < 4; slotrank++) FOR_ALL_CHANNELS if (ctrl->rankmap[channel] & (1 << slotrank)) { FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + (0x4f40 + 4 * lane), 0); - write32(DEFAULT_MCHBAR + (0x4d40 + 4 * lane), 0); + MCHBAR32(0x4f40 + 4 * lane) = 0; + MCHBAR32(0x4d40 + 4 * lane) = 0; } wait_428c(channel); /* DRAM command ACT */ - write32(DEFAULT_MCHBAR + 0x4220 + (channel << 10), 0x0001f006); - write32(DEFAULT_MCHBAR + 0x4230 + (channel << 10), 0x0028a004); - write32(DEFAULT_MCHBAR + 0x4200 + (channel << 10), - 0x00060000 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4210 + (channel << 10), 0x00000244); + MCHBAR32(0x4220 + (channel << 10)) = 0x0001f006; + MCHBAR32(0x4230 + (channel << 10)) = 0x0028a004; + MCHBAR32(0x4200 + (channel << 10)) = + 0x00060000 | (slotrank << 24); + MCHBAR32(0x4210 + (channel << 10)) = 0x00000244; /* DRAM command WR */ - write32(DEFAULT_MCHBAR + 0x4224 + (channel << 10), 0x0001f201); - write32(DEFAULT_MCHBAR + 0x4234 + (channel << 10), 0x08281064); - write32(DEFAULT_MCHBAR + 0x4204 + (channel << 10), - 0x00000000 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4214 + (channel << 10), 0x00000242); + MCHBAR32(0x4224 + (channel << 10)) = 0x0001f201; + MCHBAR32(0x4234 + (channel << 10)) = 0x08281064; + MCHBAR32(0x4204 + (channel << 10)) = + 0x00000000 | (slotrank << 24); + MCHBAR32(0x4214 + (channel << 10)) = 0x00000242; /* DRAM command RD */ - write32(DEFAULT_MCHBAR + 0x4228 + (channel << 10), 0x0001f105); - write32(DEFAULT_MCHBAR + 0x4238 + (channel << 10), 0x04281064); - write32(DEFAULT_MCHBAR + 0x4208 + (channel << 10), - 0x00000000 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x4218 + (channel << 10), 0x00000242); + MCHBAR32(0x4228 + (channel << 10)) = 0x0001f105; + MCHBAR32(0x4238 + (channel << 10)) = 0x04281064; + MCHBAR32(0x4208 + (channel << 10)) = + 0x00000000 | (slotrank << 24); + MCHBAR32(0x4218 + (channel << 10)) = 0x00000242; /* DRAM command PRE */ - write32(DEFAULT_MCHBAR + 0x422c + (channel << 10), 0x0001f002); - write32(DEFAULT_MCHBAR + 0x423c + (channel << 10), 0x00280c01); - write32(DEFAULT_MCHBAR + 0x420c + (channel << 10), - 0x00060400 | (slotrank << 24)); - write32(DEFAULT_MCHBAR + 0x421c + (channel << 10), 0x00000240); - write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001); + MCHBAR32(0x422c + (channel << 10)) = 0x0001f002; + MCHBAR32(0x423c + (channel << 10)) = 0x00280c01; + MCHBAR32(0x420c + (channel << 10)) = + 0x00060400 | (slotrank << 24); + MCHBAR32(0x421c + (channel << 10)) = 0x00000240; + MCHBAR32(0x4284 + (channel << 10)) = 0x000c0001; wait_428c(channel); FOR_ALL_LANES - if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) { + if (MCHBAR32(0x4340 + (channel << 10) + 4 * lane)) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; @@ -3167,11 +3058,11 @@ dram_odt_stretch(ctrl, channel); - write32(DEFAULT_MCHBAR + 0x4008 + (channel << 10), + MCHBAR32(0x4008 + (channel << 10)) = 0x0a000000 | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) - | b4_8_12); + | b4_8_12; } } @@ -3179,8 +3070,8 @@ { int channel; FOR_ALL_POPULATED_CHANNELS { - write32(DEFAULT_MCHBAR + (0x42a0 + 0x400 * channel), - 0x00001000 | ctrl->rankmap[channel]); + MCHBAR32(0x42a0 + 0x400 * channel) = + 0x00001000 | ctrl->rankmap[channel]; MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK } } @@ -3198,10 +3089,10 @@ int t3_ns; u32 r32; - write32(DEFAULT_MCHBAR + 0x4cd4, 0x00000046); + MCHBAR32(0x4cd4) = 0x00000046; - write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK - write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK + MCHBAR32(0x400c) = (MCHBAR32(0x400c) & 0xFFFFCFFF) | 0x1000; // OK + MCHBAR32(0x440c) = (MCHBAR32(0x440c) & 0xFFFFCFFF) | 0x1000; // OK if (ctrl->mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3210,40 +3101,35 @@ /* APD - PPD, 64 DCLKs until idle, decision per rank */ MCHBAR32(PM_PDWN_Config) = 0x00000340; - write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK - write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK - write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK - write32(DEFAULT_MCHBAR + 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK + MCHBAR32(0x4380) = 0x00000aaa; // OK + MCHBAR32(0x4780) = 0x00000aaa; // OK + MCHBAR32(0x4f88) = 0x5f7003ff; // OK + MCHBAR32(0x5064) = 0x00073000 | ctrl->reg_5064b0; // OK FOR_ALL_CHANNELS { switch (ctrl->rankmap[channel]) { /* Unpopulated channel. */ case 0: - write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0); + MCHBAR32(0x4384 + channel * 0x400) = 0; break; /* Only single-ranked dimms. */ case 1: case 4: case 5: - write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x373131); + MCHBAR32(0x4384 + channel * 0x400) = 0x373131; break; /* Dual-ranked dimms present. */ default: - write32(DEFAULT_MCHBAR + 0x4384 + channel * 0x400, 0x9b6ea1); + MCHBAR32(0x4384 + channel * 0x400) = 0x9b6ea1; break; } } - write32 (DEFAULT_MCHBAR + 0x5880, 0xca9171e5); - write32 (DEFAULT_MCHBAR + 0x5888, - (read32 (DEFAULT_MCHBAR + 0x5888) & ~0xffffff) | 0xe4d5d0); - write32 (DEFAULT_MCHBAR + 0x58a8, read32 (DEFAULT_MCHBAR + 0x58a8) & ~0x1f); - write32 (DEFAULT_MCHBAR + 0x4294, - (read32 (DEFAULT_MCHBAR + 0x4294) & ~0x30000) - | (1 << 16)); - write32 (DEFAULT_MCHBAR + 0x4694, - (read32 (DEFAULT_MCHBAR + 0x4694) & ~0x30000) - | (1 << 16)); + MCHBAR32(0x5880) = 0xca9171e5; + MCHBAR32(0x5888) = MCHBAR32(0x5888) & ~0xffffff) | 0xe4d5d0; + MCHBAR32(0x58a8) = MCHBAR32(0x58a8) & ~0x1f; + MCHBAR32(0x4294) = MCHBAR32(0x4294) & ~0x30000 | (1 << 16); + MCHBAR32(0x4694) = MCHBAR32(0x4694) & ~0x30000 | (1 << 16); MCHBAR32(0x5030) |= 1; // OK MCHBAR32(0x5030) |= 0x80; // OK @@ -3253,20 +3139,20 @@ FOR_ALL_POPULATED_CHANNELS break; - t1_cycles = ((read32(DEFAULT_MCHBAR + 0x4290 + channel * 0x400) >> 8) & 0xff); - r32 = read32(DEFAULT_MCHBAR + 0x5064); + t1_cycles = (MCHBAR32(0x4290 + channel * 0x400) >> 8) & 0xff; + r32 = MCHBAR32(0x5064); if (r32 & 0x20000) t1_cycles += (r32 & 0xfff); - t1_cycles += (read32(DEFAULT_MCHBAR + channel * 0x400 + 0x42a4) & 0xfff); + t1_cycles += MCHBAR32(channel * 0x400 + 0x42a4) & 0xfff; t1_ns = t1_cycles * ctrl->tCK / 256 + 544; if (!(r32 & 0x20000)) t1_ns += 500; - t2_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f10) >> 8) & 0xfff); - if ( read32(DEFAULT_MCHBAR + 0x5f00) & 8 ) + t2_ns = 10 * ((MCHBAR32(0x5f10) >> 8) & 0xfff); + if (MCHBAR32(0x5f00) & 8) { - t3_ns = 10 * ((read32(DEFAULT_MCHBAR + 0x5f20) >> 8) & 0xfff); - t3_ns += 10 * (read32(DEFAULT_MCHBAR + 0x5f18) & 0xff); + t3_ns = 10 * ((MCHBAR32(0x5f20) >> 8) & 0xfff); + t3_ns += 10 * (MCHBAR32(0x5f18) & 0xff); } else { @@ -3274,12 +3160,10 @@ } printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - write32 (DEFAULT_MCHBAR + 0x5d10, - ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) - | (encode_5d10(t1_ns) << 8) - | ((encode_5d10(t3_ns) + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) - | (read32(DEFAULT_MCHBAR + 0x5d10) & 0xC0C0C0C0) - | 0xc); + MCHBAR32(0x5d10) = ((encode_5d10(t1_ns) + encode_5d10(t2_ns)) << 16) | + (encode_5d10(t1_ns) << 8) | ((encode_5d10(t3_ns) + + encode_5d10(t2_ns) + encode_5d10(t1_ns)) << 24) | + (MCHBAR32(0x5d10) & 0xC0C0C0C0) | 0xc; } void restore_timings(ramctr_timing * ctrl) @@ -3303,26 +3187,23 @@ } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel - + 4 * lane, 0); + MCHBAR32(0x4080 + 0x400 * channel + 4 * lane) = 0; } FOR_ALL_POPULATED_CHANNELS - write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4008 + - 0x400 * channel) | 0x8000000); + MCHBAR32(0x4008 + 0x400 * channel) = + MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000; FOR_ALL_POPULATED_CHANNELS { udelay (1); - write32(DEFAULT_MCHBAR + 0x4020 + 0x400 * channel, - read32(DEFAULT_MCHBAR + 0x4020 + - 0x400 * channel) | 0x200000); + MCHBAR32(0x4020 + 0x400 * channel) = + MCHBAR32(0x4020 + 0x400 * channel) | 0x200000; } printram("CPE\n"); - write32(DEFAULT_MCHBAR + 0x3400, 0); - write32(DEFAULT_MCHBAR + 0x4eb0, 0); + MCHBAR32(0x3400) = 0; + MCHBAR32(0x4eb0) = 0; printram("CP5b\n"); @@ -3366,14 +3247,13 @@ printram("CP5c\n"); - write32(DEFAULT_MCHBAR + 0x3000, 0); + MCHBAR32(0x3000) = 0; FOR_ALL_CHANNELS { - write32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c, - 0 | (read32(DEFAULT_MCHBAR + (channel * 0x100) + 0xe3c) & - ~0x3f000000)); + MCHBAR32(channel * 0x100 + 0xe3c) = + 0 | (MCHBAR32(channel * 0x100 + 0xe3c) & ~0x3f000000); udelay(2); } - write32(DEFAULT_MCHBAR + 0x4ea8, 0); + MCHBAR32(0x4ea8) = 0; } -- To view, visit https://review.coreboot.org/27674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I22f1c7dbdaf42722115d9e5913d47aa2c9dc7e9a Gerrit-Change-Number: 27674 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Add Whiskey Lake rvp board
by Lijian Zhao (Code Review) 27 Jul '18

27 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27628 to look at the new patch set (#4). Change subject: mb/intel/coffeelake_rvp: Add Whiskey Lake rvp board ...................................................................... mb/intel/coffeelake_rvp: Add Whiskey Lake rvp board Add new mainboard variant for Whiskey Lake rvp, it will include change to read SPD from SMBUS slave address directly instead of pass bin file pointer. Also fsp memory upd will use the setting fit the board. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskeylake rvp platform. Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c A src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h 6 files changed, 191 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27628/4 -- To view, visit https://review.coreboot.org/27628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Gerrit-Change-Number: 27628 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: add CPPC support
by Matt Delco (Code Review) 27 Jul '18

27 Jul '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/27673 Change subject: soc/intel/skylake: add CPPC support ...................................................................... soc/intel/skylake: add CPPC support ACPI defines a method _CPC for "Continuous Performance Control" (CPPC). Linux has a driver that enables features like speed shift without consulting ACPI. Other OSes instead rely on this information and need a _CPC present. Prior to this change performance in Win10 never exceeds 80% and MSR 0x770 is 0, while with this change higher speeds can be achieved and the MSR value is now 1. Rather than add a large package to each processor I have the code add one global instance and each processor has a method that references that instance. I'm open to suggestions on a different place to place the package. Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/soc/intel/skylake/acpi.c 1 file changed, 152 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27673/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 5bed118..d2d41c9 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -501,6 +501,151 @@ acpigen_pop_len(); } +#define CPPC_PACKAGE_NAME "\\GCPC" + +static void generate_CPPC_method(void) +{ + acpigen_write_method("_CPC", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(CPPC_PACKAGE_NAME); + acpigen_pop_len(); +} + +static void generate_CPPC_package(bool version2) +{ + acpi_addr_t msr = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 8, + .bit_offset = 0, + { + .access_size = 4 + }, + .addrl = 0, + .addrh = 0, + }; + static const acpi_addr_t unsupported = { + .space_id = ACPI_ADDRESS_SPACE_MEMORY, + .bit_width = 0, + .bit_offset = 0, + { + .resv = 0 + }, + .addrl = 0, + .addrh = 0, + }; + + acpigen_write_name(CPPC_PACKAGE_NAME); + acpigen_write_package(version2 ? 21 : 17); + + acpigen_write_dword(version2 ? 21 : 17); + acpigen_write_byte(version2 ? 2 : 1); + + // 0x771 is IA32_HWP_CAPABILITIES (RO) + msr.addrl = 0x771; + + // Highest Performance: + // ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x771, 0x04,)}, + acpigen_write_register_resource(&msr); + + // Nominal Performance -> Guaranteed Performance: + // ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, + msr.bit_offset = 8; + acpigen_write_register_resource(&msr); + + // Lowest Nonlinear Performance -> Most Efficient Performance: + // ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)}, + msr.bit_offset = 16; + acpigen_write_register_resource(&msr); + + // Lowest Performance: + // ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x771, 0x04,)}, + msr.bit_offset = 24; + acpigen_write_register_resource(&msr); + + // Guaranteed Performance Register: + // ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)}, + msr.bit_offset = 8; + acpigen_write_register_resource(&msr); + + // 0x774 is IA32_HWP_REQUEST (RW) + msr.addrl = 0x774; + + // Desired Performance Register: + // ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x774, 0x04,)}, + msr.bit_offset = 16; + acpigen_write_register_resource(&msr); + + // Minimum Performance Register: + // ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x774, 0x04,)}, + msr.bit_offset = 0; + acpigen_write_register_resource(&msr); + + // Maximum Performance Register: + // ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x774, 0x04,)}, + msr.bit_offset = 8; + acpigen_write_register_resource(&msr); + + // Performance Reduction Tolerance Register: + // ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + acpigen_write_register_resource(&unsupported); + + // Time Window Register: + // ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + acpigen_write_register_resource(&unsupported); + + // Counter Wraparound Time: + // ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)}, + acpigen_write_register_resource(&unsupported); + + // 0xE7 is IA32_MPERF + msr.addrl = 0xe7; + + // Reference Performance Counter Register: + // ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E7, 0x04,)}, + msr.bit_width = 64; + msr.bit_offset = 0; + acpigen_write_register_resource(&msr); + + // 0xE8 is IA32_APERF + msr.addrl = 0xe8; + + // Delivered Performance Counter Register: + // ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E8, 0x04,)}, + acpigen_write_register_resource(&msr); + + // 0x777 is IA32_HWP_STATUS + msr.addrl = 0x777; + + // Performance Limited Register: + // ResourceTemplate(){Register(FFixedHW, 0x01, 0x02, 0x777, 0x04,)}, + msr.bit_width = 1; + msr.bit_offset = 2; + acpigen_write_register_resource(&msr); + + // 0x770 is IA32_PM_ENABLE + msr.addrl = 0x770; + + // CPPC Enable Register: + // ResourceTemplate(){Register(FFixedHW, 0x01, 0x00, 0x770, 0x04,)}, + msr.bit_offset = 0; + acpigen_write_register_resource(&msr); + + if (version2) { + // Autonomous Selection Enable = 1 + acpigen_write_dword(1); + + // Autonomous Activity Window Register + acpigen_write_register_resource(&unsupported); + + // Energy Performance Preference Register + acpigen_write_register_resource(&unsupported); + + // Reference Performance + acpigen_write_register_resource(&unsupported); + } + acpigen_pop_len(); +} + void generate_cpu_entries(struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; @@ -520,6 +665,9 @@ printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); + if (config->eist_enable && config->speed_shift_enable) + generate_CPPC_package(TRUE); + for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { for (core_id = 0; core_id < cores_per_package; core_id++) { if (core_id > 0) { @@ -535,11 +683,13 @@ generate_c_state_entries(is_s0ix_enable, max_c_state); - if (config->eist_enable) + if (config->eist_enable) { /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); - + if (config->speed_shift_enable) + generate_CPPC_method(); + } acpigen_pop_len(); } } -- To view, visit https://review.coreboot.org/27673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062 Gerrit-Change-Number: 27673 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: arch/x86/acpigen: refactor calls to acpigen_write_register
by Matt Delco (Code Review) 27 Jul '18

27 Jul '18

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/27672 Change subject: arch/x86/acpigen: refactor calls to acpigen_write_register ...................................................................... arch/x86/acpigen: refactor calls to acpigen_write_register All of the callers to acpigen_write_register() also make calls to acpigen_write_resourcetemplate_[header|footer](). This change introduces acpigen_write_register_resource() to unify all of those trio of calls into one. I also made the input parameter const. Change-Id: I10b336acf9f03c423bee9dc38955b1617e11c025 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h 2 files changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/27672/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 732f749..a614efb 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -578,14 +578,10 @@ acpigen_write_package(2); /* ControlRegister */ - acpigen_write_resourcetemplate_header(); - acpigen_write_register(&addr); - acpigen_write_resourcetemplate_footer(); + acpigen_write_register_resource(&addr); /* StatusRegister */ - acpigen_write_resourcetemplate_header(); - acpigen_write_register(&addr); - acpigen_write_resourcetemplate_footer(); + acpigen_write_register_resource(&addr); acpigen_pop_len(); } @@ -725,9 +721,7 @@ void acpigen_write_CST_package_entry(acpi_cstate_t *cstate) { acpigen_write_package(4); - acpigen_write_resourcetemplate_header(); - acpigen_write_register(&cstate->resource); - acpigen_write_resourcetemplate_footer(); + acpigen_write_register_resource(&cstate->resource); acpigen_write_dword(cstate->ctype); acpigen_write_dword(cstate->latency); acpigen_write_dword(cstate->power); @@ -827,7 +821,7 @@ acpigen_emit_dword(size); } -void acpigen_write_register(acpi_addr_t *addr) +static void acpigen_write_register(const acpi_addr_t *addr) { acpigen_emit_byte(0x82); /* Register Descriptor */ acpigen_emit_byte(0x0c); /* Register Length 7:0 */ @@ -840,6 +834,13 @@ acpigen_emit_dword(addr->addrh); /* Register Address High */ } +void acpigen_write_register_resource(const acpi_addr_t *addr) +{ + acpigen_write_resourcetemplate_header(); + acpigen_write_register(addr); + acpigen_write_resourcetemplate_footer(); +} + void acpigen_write_irq(u16 mask) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 52aa55b..042c797 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -228,7 +228,7 @@ void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); -void acpigen_write_register(acpi_addr_t *addr); +void acpigen_write_register_resource(const acpi_addr_t *addr); void acpigen_write_resourcetemplate_header(void); void acpigen_write_resourcetemplate_footer(void); void acpigen_write_mainboard_resource_template(void); -- To view, visit https://review.coreboot.org/27672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I10b336acf9f03c423bee9dc38955b1617e11c025 Gerrit-Change-Number: 27672 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org>

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Change in coreboot[master]: mb/google/octopus: Perform EC init before bootblock gpio configuration
by Furquan Shaikh (Code Review) 27 Jul '18

27 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27671 Change subject: mb/google/octopus: Perform EC init before bootblock gpio configuration ...................................................................... mb/google/octopus: Perform EC init before bootblock gpio configuration A variant might talk to the EC to get board id in order to identify the right GPIO configuration. Thus it is important to ensure that the LPC IO windows are configured before this. This change moves the call to perform EC init before configuring bootblock GPIOs. BUG=b:111933657 TEST=Verified that reading board id does not fail on phaser. Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/bootblock.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27671/1 diff --git a/src/mainboard/google/octopus/bootblock.c b/src/mainboard/google/octopus/bootblock.c index 6826e5d..0c239db 100644 --- a/src/mainboard/google/octopus/bootblock.c +++ b/src/mainboard/google/octopus/bootblock.c @@ -25,7 +25,14 @@ size_t num; lpc_configure_pads(); + + /* + * Perform EC init before configuring GPIOs. This is because variant + * might talk to the EC to get board id and hence it will require EC + * init to have already performed. + */ + mainboard_ec_init(); + pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); - mainboard_ec_init(); } -- To view, visit https://review.coreboot.org/27671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567 Gerrit-Change-Number: 27671 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFF
by Richard Spiegel (Code Review) 27 Jul '18

27 Jul '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27670 Change subject: mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFF ...................................................................... mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFF The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/OemCustomize.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27670/1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 6e6992d..d78f784 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -51,3 +51,8 @@ */ PostParams->MemConfig.EnableBankIntlv = FALSE; } + +void set_board_env_params(GNB_ENV_CONFIGURATION *params) +{ + params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE; +} -- To view, visit https://review.coreboot.org/27670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Gerrit-Change-Number: 27670 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Add whiskey lake rvp board
by Lijian Zhao (Code Review) 27 Jul '18

27 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27628 to look at the new patch set (#3). Change subject: mb/intel/coffeelake_rvp: Add whiskey lake rvp board ...................................................................... mb/intel/coffeelake_rvp: Add whiskey lake rvp board Add new mainboard variant for whiskey lake rvp, it will include change to read SPD from SMBUS slave address directly instead of pass bin file pointer. Also fsp memory upd will use the setting fit the board. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskeylake rvp platform. Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c A src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h 6 files changed, 191 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27628/3 -- To view, visit https://review.coreboot.org/27628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Gerrit-Change-Number: 27628 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Add whiskeylake rvp board
by Lijian Zhao (Code Review) 27 Jul '18

27 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27628 to look at the new patch set (#2). Change subject: mb/intel/coffeelake_rvp: Add whiskeylake rvp board ...................................................................... mb/intel/coffeelake_rvp: Add whiskeylake rvp board Add new mainboard variant for whiskeylake rvp, which will include change to read SPD from SMBUS slave address directly instead of pass bin file pointer. Also fsp memory upd will use the setting fit the board. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskeylake rvp platform. Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c A src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h 6 files changed, 191 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27628/2 -- To view, visit https://review.coreboot.org/27628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Gerrit-Change-Number: 27628 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit July 2018