Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27661 )
Change subject: mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default
......................................................................
Patch Set 3: Code-Review+2
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Seunghwan Kim has posted comments on this change. ( https://review.coreboot.org/27661 )
Change subject: mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default
......................................................................
Patch Set 3: Code-Review+1
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Change subject: mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default
......................................................................
Removed Code-Review+1 by Seunghwan Kim <sh_.kim(a)samsung.com>
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Change subject: mb/google/poppy/variants/nautilus: Set GPP_D21 to high as default
......................................................................
Patch Set 3:
This change is ready for review.
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27659
Change subject: google/caroline: Change debounce time for jack insertion and ejection
......................................................................
google/caroline: Change debounce time for jack insertion and ejection
Adapted from chromium commit 7633daa
[caroline: Change debounce time for jack insertion and ejection]
We are using max debounce time. During this time line, MICBIAS will be
zero because of jack chasis. At the moment we got 0 button(PLAY/PAUSE)
We need to reduce this time within 100ms for caroline device.
BUG=b:79559096
TEST=see there is no more irq before jack insertion/ejection irq
complete
Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a
Original-Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1143109
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Wonjoon Lee <woojoo.lee(a)samsung.com>
Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/glados/variants/caroline/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/27659/1
diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb
index a040714..0c3c861 100644
--- a/src/mainboard/google/glados/variants/caroline/devicetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb
@@ -244,8 +244,8 @@
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms
- register "jack_insert_debounce" = "7" # 512ms
- register "jack_eject_debounce" = "7" # 512ms
+ register "jack_insert_debounce" = "4" # 64ms
+ register "jack_eject_debounce" = "4" # 64ms
device i2c 1a on end
end
chip drivers/i2c/generic
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27523 )
Change subject: soc/intel/cannonlake: Update PMC base address for CNP H and LP
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/27523/2/src/soc/intel/cannonlake/bootblock/…
File src/soc/intel/cannonlake/bootblock/pch.c:
https://review.coreboot.org/#/c/27523/2/src/soc/intel/cannonlake/bootblock/…
PS2, Line 37: #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980
please, no space before tabs
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Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/27657 )
Change subject: mainboard/google/kahlee: Fix Micron MT40A512M16LY-075:E POST CRC error
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/27657/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/27657/1//COMMIT_MSG@7
PS1, Line 7: mainboard/go
> mainboard/google/kahlee would probably be better here
Done.
thanks.
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Hello build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/27657
to look at the new patch set (#2).
Change subject: mainboard/google/kahlee: Fix Micron MT40A512M16LY-075:E POST CRC error
......................................................................
mainboard/google/kahlee: Fix Micron MT40A512M16LY-075:E POST CRC error
Fix Micron MT40A512M16LY-075:E DRAM SPD CRC error in AGESA MemSPDChecking:
ERROR Event: 04011200 Data: 0, 0, 0, 0
BUG=b:111901461
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961
Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com>
---
M src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16LY-075-E.spd.hex
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27657/2
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