coreboot-gerrit July 2018

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Change in coreboot[master]: google/grunt: Fix Micron MT40A512M16LY-075:E POST CRC error
by Martin Roth (Code Review) 27 Jul '18

27 Jul '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27657 ) Change subject: google/grunt: Fix Micron MT40A512M16LY-075:E POST CRC error ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27657/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27657/1//COMMIT_MSG@7 PS1, Line 7: google/grunt mainboard/google/kahlee would probably be better here -- To view, visit https://review.coreboot.org/27657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961 Gerrit-Change-Number: 27657 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Jul 2018 02:54:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: google/grunt: Fix Micron MT40A512M16LY-075:E POST CRC error
by Martin Roth (Code Review) 27 Jul '18

27 Jul '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27657 ) Change subject: google/grunt: Fix Micron MT40A512M16LY-075:E POST CRC error ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961 Gerrit-Change-Number: 27657 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Jul 2018 02:49:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: enable FPMCU power
by Furquan Shaikh (Code Review) 27 Jul '18

27 Jul '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27658 ) Change subject: mb/google/poppy/variants/nocturne: enable FPMCU power ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289 Gerrit-Change-Number: 27658 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nicolas Norvez <norvez(a)chromium.org> Gerrit-Comment-Date: Fri, 27 Jul 2018 02:36:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: enable FPMCU power
by Nick Vaccaro (Code Review) 27 Jul '18

27 Jul '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/27658 Change subject: mb/google/poppy/variants/nocturne: enable FPMCU power ...................................................................... mb/google/poppy/variants/nocturne: enable FPMCU power Enable power to FPMCU by default on power-on and deassert the PCH_FPMCU_RST_ODL reset line. BUG=b:111880258 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel prompt, wait a few seconds, press power button to wake, then execute "cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes up empty. Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/gpio.c 2 files changed, 3 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27658/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 235391e..9d9c5ae 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -423,15 +423,8 @@ register "compat_string" = ""google,cros-ec-spi"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)" register "wake" = "GPE0_DW0_09" # GPP_C9 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "reset_delay_ms" = "0" - register "reset_off_delay_ms" = "0" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" - register "enable_delay_ms" = "0" - register "enable_off_delay_ms" = "0" - register "has_power_resource" = "1" device spi 0 on end - end + end # FPMCU end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 3c186c7..782ce00 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -38,7 +38,7 @@ /* A10 : CLKOUT_LPC1 ==> NC */ PAD_CFG_NC(GPP_A10), /* A11 : PCH_FP_PWR_EN */ - PAD_CFG_GPO(GPP_A11, 0, DEEP), + PAD_CFG_GPO(GPP_A11, 1, DEEP), /* A12 : ISH_GP6 */ PAD_CFG_NC(GPP_A12), /* A13 : SUSWARN# ==> SUSWARN_L */ @@ -133,7 +133,7 @@ /* C9 : UART0_TXD ==> FPMCU_INT */ PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT), /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 0, DEEP), + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ -- To view, visit https://review.coreboot.org/27658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289 Gerrit-Change-Number: 27658 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: google/grunt: Fix Micron MT40A512M16LY-075:E POST CRC error
by Kevin Chiu (Code Review) 27 Jul '18

27 Jul '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/27657 Change subject: google/grunt: Fix Micron MT40A512M16LY-075:E POST CRC error ...................................................................... google/grunt: Fix Micron MT40A512M16LY-075:E POST CRC error Fix Micron MT40A512M16LY-075:E DRAM SPD CRC error in AGESA MemSPDChecking: ERROR Event: 04011200 Data: 0, 0, 0, 0 BUG=b:111901461 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16LY-075-E.spd.hex 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27657/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16LY-075-E.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16LY-075-E.spd.hex index bd65771..1b39e3e 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16LY-075-E.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16LY-075-E.spd.hex @@ -6,7 +6,7 @@ 16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 D6 60 5B +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 60 5B 0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/27657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961 Gerrit-Change-Number: 27657 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: Documentation: Add Util.md summary
by Tom Hiller (Code Review) 27 Jul '18

27 Jul '18

Tom Hiller has uploaded this change for review. ( https://review.coreboot.org/27656 Change subject: Documentation: Add Util.md summary ...................................................................... Documentation: Add Util.md summary Add short explanation of Utility list Change-Id: I5fc45ebe29cd42c1aa18c59dabc3ac3db3107bd7 Signed-off-by: Tom Hiller <thrilleratplay(a)gmail.com> --- M Documentation/util.md M util/util_readme/util_readme.sh 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/27656/1 diff --git a/Documentation/util.md b/Documentation/util.md index 9adb908..be7cc99 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -1,4 +1,5 @@ # Utilities +_Scripts and programs found in the `./util` directory_ * __abuild__ - coreboot autobuild script builds coreboot images for all available targets. `bash` * __acpi__ - Walk through all ACPI tables with their addresses. `bash` diff --git a/util/util_readme/util_readme.sh b/util/util_readme/util_readme.sh index 2516614..420ffae 100755 --- a/util/util_readme/util_readme.sh +++ b/util/util_readme/util_readme.sh @@ -10,11 +10,13 @@ UTIL_DIR=$(dirname "$UTIL_README_DIR") COREBOOT_ROOT_DIR=$(dirname "$UTIL_DIR") DOCMENTATION_DIR="$COREBOOT_ROOT_DIR/Documentation" +SUMMARY="_Scripts and programs found in the \`./util\` directory_" DESCRIPTION_FILES=$(find "$UTIL_DIR" -name "description.md" | sort) echo -n "" > "$UTIL_DIR/README.md" echo "# Utilities" > "$DOCMENTATION_DIR/util.md" +echo "$SUMMARY" >> "$DOCMENTATION_DIR/util.md" for DESC_FILE in $DESCRIPTION_FILES; do UTIL_NAME=$(echo "$DESC_FILE" | rev | cut -d '/' -f2 | rev) -- To view, visit https://review.coreboot.org/27656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5fc45ebe29cd42c1aa18c59dabc3ac3db3107bd7 Gerrit-Change-Number: 27656 Gerrit-PatchSet: 1 Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com>

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Change in coreboot[master]: mediatek/mt8183: Remove unused MMU stuff from bootblock
by Tristan Hsieh (Code Review) 27 Jul '18

27 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27655 Change subject: mediatek/mt8183: Remove unused MMU stuff from bootblock ...................................................................... mediatek/mt8183: Remove unused MMU stuff from bootblock Since we move mtk_mmu_init() from bootblock to decompressor, we don't need to build mmu_opertations.c in bootblock and we don't need to include <soc/mmu_operations.h> in bootblock.c. BUG=b:80501386 TEST=manually flashed into kukui and boots into romstage. Change-Id: I58f97ac1705e4dfde5e2d497d9bec33a1d8d17c2 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/bootblock.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/27655/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 752395d..1b3f9d5 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -2,7 +2,6 @@ bootblock-y += bootblock.c bootblock-y += ../common/gpio.c gpio.c -bootblock-y += ../common/mmu_operations.c mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8183/bootblock.c b/src/soc/mediatek/mt8183/bootblock.c index 4e05e18..d7d5c2d 100644 --- a/src/soc/mediatek/mt8183/bootblock.c +++ b/src/soc/mediatek/mt8183/bootblock.c @@ -14,7 +14,6 @@ */ #include <bootblock_common.h> -#include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/wdt.h> -- To view, visit https://review.coreboot.org/27655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I58f97ac1705e4dfde5e2d497d9bec33a1d8d17c2 Gerrit-Change-Number: 27655 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: 3rdparty/blobs: Update submodule pointer to include latest BL31
by Philipp Deppenwiese (Code Review) 27 Jul '18

27 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27647 ) Change subject: 3rdparty/blobs: Update submodule pointer to include latest BL31 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie8f3b2e8db0692e95caee245733054e4e20f61ea Gerrit-Change-Number: 27647 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 27 Jul 2018 01:22:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: device/pnp_device: rewrite pnp_get_ioresource
by Felix Held (Code Review) 27 Jul '18

27 Jul '18

Felix Held has uploaded a new patch set (#2). ( https://review.coreboot.org/27654 ) Change subject: device/pnp_device: rewrite pnp_get_ioresource ...................................................................... device/pnp_device: rewrite pnp_get_ioresource The rewrite simplifies the code and fixes the limit on the case of IO resources with the length of 1 byte. This patch is inspired by the comment of Nico Huber on Ia99b785dcd9cf56fb236ad7ade54656851f88a5e If the ones in the mask aren't a continuous block, now a warning message gets printed. Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/pnp_device.c 1 file changed, 23 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/27654/2 -- To view, visit https://review.coreboot.org/27654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7 Gerrit-Change-Number: 27654 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: device/pnp_device: rewrite pnp_get_ioresource
by Felix Held (Code Review) 27 Jul '18

27 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27654 Change subject: device/pnp_device: rewrite pnp_get_ioresource ...................................................................... device/pnp_device: rewrite pnp_get_ioresource The rewrite simplifies the code and fixes the limit on the case of IO resources with the length of 1 byte. This patch is inspired by the comment of Nico Huber on Ia99b785dcd9cf56fb236ad7ade54656851f88a5e If the ones in the mask aren't a continuous block, now a warning message gets printed. Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/pnp_device.c 1 file changed, 24 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/27654/1 diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 5600231..edf3343 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -7,6 +7,7 @@ * Copyright (C) 2005 Tyan * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * Copyright (C) 2018 Felix Held <felix-coreboot(a)felixheld.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +26,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <assert.h> /* PNP config mode wrappers */ @@ -194,8 +196,10 @@ static void pnp_get_ioresource(struct device *dev, u8 index, u16 mask) { struct resource *resource; - unsigned moving, gran, step; + unsigned int bit; + /* If none of the mask bits is set, the resource would occupy the whole + IO space leading to IO resource conflicts with the other devices */ if (!mask) { printk(BIOS_ERR, "ERROR: device %s index %d has no mask.\n", dev_path(dev), index); @@ -203,43 +207,31 @@ } resource = new_resource(dev, index); - - /* Initilize the resource. */ - resource->limit = 0xffff; resource->flags |= IORESOURCE_IO; - /* Get the resource size... */ + /* Calculate IO region size which is determined by the first one from + the LSB of the mask. */ + for (bit = 0; bit <= 15 && (mask & (1 << bit)) == 0; ++bit) + ; - moving = mask; - gran = 15; - step = 1 << gran; + resource->gran = bit; + resource->align = bit; + resource->size = 1 << bit; - /* Find the first bit that moves. */ - while ((moving & step) == 0) { - gran--; - step >>= 1; - } + /* Calculate IO region address limit which is determined by the first + one from the MSB of the mask. */ + for (bit = 15; bit != 0 && (mask & (1 << bit)) == 0; --bit) + ; - /* Now find the first bit that does not move. */ - while ((moving & step) != 0) { - gran--; - step >>= 1; - } + resource->limit = (1 << (bit + 1)) - 1; - /* - * Of the moving bits the last bit in the first group, - * tells us the size of this resource. - */ - if ((moving & step) == 0) { - gran++; - step <<= 1; - } - - /* Set the resource size and alignment. */ - resource->gran = gran; - resource->align = gran; - resource->limit = mask | (step - 1); - resource->size = 1 << gran; + /* The block of ones in the mask is expected to be continuous. + If there is any zero inbetween the block of ones, it is ignored + in the calculation of the resource size and limit. */ + if (mask != (resource->limit ^ (resource->size - 1))) + printk(BIOS_WARNING, + "WARNING: mask of device %s index %d wrong.\n", + dev_path(dev), index); } static void get_resources(struct device *dev, struct pnp_info *info) -- To view, visit https://review.coreboot.org/27654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7 Gerrit-Change-Number: 27654 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit July 2018