Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/27630 )
Change subject: Documenation/conf.py: Make sure release is a string
......................................................................
Documenation/conf.py: Make sure release is a string
With python3 the split method can operate on strings while check_output
generates bytestrings.
Change-Id: I7b455c56e8195f0ecfbe5e360ac161c176f00115
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27630
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
M Documentation/conf.py
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Philipp Deppenwiese: Looks good to me, approved
diff --git a/Documentation/conf.py b/Documentation/conf.py
index b8415c6..ff1ad9d 100644
--- a/Documentation/conf.py
+++ b/Documentation/conf.py
@@ -20,7 +20,7 @@
# built documents.
#
# The full version, including alpha/beta/rc tags.
-release = subprocess.check_output(('git', 'describe'))
+release = subprocess.check_output(('git', 'describe')).decode("utf-8")
# The short X.Y version.
version = release.split("-")[0]
--
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Gerrit-Change-Id: I7b455c56e8195f0ecfbe5e360ac161c176f00115
Gerrit-Change-Number: 27630
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Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/27631 )
Change subject: Documentation/writing_docs: Document the need for recommonmark
......................................................................
Documentation/writing_docs: Document the need for recommonmark
python-recommonmark is need for sphinx to be able to hande the markdown
documentation.
Change-Id: I9513ab4bdc753e0350754d9869239ea833893af9
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27631
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
M Documentation/getting_started/writing_documentation.md
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Philipp Deppenwiese: Looks good to me, approved
diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md
index 9a9bbf0..027def9 100644
--- a/Documentation/getting_started/writing_documentation.md
+++ b/Documentation/getting_started/writing_documentation.md
@@ -16,7 +16,9 @@
### Install Sphinx
-Please follow this official [guide].
+Please follow this official [guide] to install sphinx.
+You will also need python-recommonmark for sphinx to be able to handle
+markdown documenation.
### Optional
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Gerrit-Change-Number: 27631
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27564 )
Change subject: util: Add util_readme script
......................................................................
Patch Set 6: Code-Review+2
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Gerrit-Change-Id: I015ae6816ea74cacb7f0332fda2c3ebef205c1e2
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Gerrit-Owner: Tom Hiller <thrilleratplay(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Gerrit-Comment-Date: Thu, 26 Jul 2018 10:39:25 +0000
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Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27645
Change subject: riscv: add support move bootblock to CAR/SRAM before exection
......................................................................
riscv: add support move bootblock to CAR/SRAM before exection
It cannot access the data segment, if program located in masked rom.
So we can move it to CAR/SRAM before execution.
Change-Id: If1f53a7dbd7db9643bd9aeea6567cd4fae0f310e
Signed-off-by: Xiang Wang <wxjstz(a)126.com>
---
M src/arch/riscv/Kconfig
M src/arch/riscv/bootblock.S
2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27645/1
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 916e269..e36bbd6 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -28,3 +28,7 @@
config ARCH_RAMSTAGE_RISCV
bool
default n
+
+config MOVE_BOOTBLOCK_TO_CAR
+ bool
+ default n
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index f92ed4b..378214c 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -37,6 +37,31 @@
# initialize cache as ram
call cache_as_ram
+ # It cannot access the data segment, if program located in masked rom.
+ # so we can move it to CAR/SRAM before execution.
+#if IS_ENABLED(CONFIG_MOVE_BOOTBLOCK_TO_CAR)
+_m2car:
+ la a0, _program
+ la a1, _eprogram
+ ld a2, _program_execution_address
+ beq a0, a2, _em2car
+1:
+ lb t0, 0(a0)
+ sb t0, 0(a2)
+ addi a0, a0, 1
+ addi a2, a2, 1
+ blt a0, a1, 1b
+
+ ld a0, _em2car_execution_address
+ jr a0
+_program_execution_address:
+ .dword _program
+_em2car_execution_address:
+ .dword _em2car
+_em2car:
+
+#endif
+
# Save the FDT pointer to memory.
# Make mscratch vacate for exception context switching.
csrrw a1, mscratch, zero
--
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Kane Chen has posted comments on this change. ( https://review.coreboot.org/27644 )
Change subject: mb/google/poppy/variant/nami: Overwrite AC/DC loadlines
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/27644/3/src/mainboard/google/poppy/variants…
File src/mainboard/google/poppy/variants/nami/mainboard.c:
https://review.coreboot.org/#/c/27644/3/src/mainboard/google/poppy/variants…
PS3, Line 168: ant_devtree_update(void)
Do we need to move this entire function here?
thanks.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/poppy/variant/nami: Overwrite AC/DC loadlines
......................................................................
mb/google/poppy/variant/nami: Overwrite AC/DC loadlines
This patch adds a function to overwrite AC/DC loadlines for differnt
projects.
BUG=b:111761175
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump
AC/DC loadline settings.
Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864
Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com>
---
A src/mainboard/google/poppy/variants/nami/include/variant/variant.h
M src/mainboard/google/poppy/variants/nami/mainboard.c
2 files changed, 175 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/27644/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/27644
to look at the new patch set (#2).
Change subject: mb/google/poppy/variant/nami: Overwrite AC/DC loadlines
......................................................................
mb/google/poppy/variant/nami: Overwrite AC/DC loadlines
This patch adds a fucntion to overwrite AC/DC loadlines for differnt
projects.
BUG=b:111761175
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump
AC/DC loadline settings.
Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864
Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com>
---
A src/mainboard/google/poppy/variants/nami/include/variant/variant.h
M src/mainboard/google/poppy/variants/nami/mainboard.c
2 files changed, 175 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/27644/2
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