coreboot-gerrit July 2018

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Change in coreboot[master]: mb/google/octopusi/variants/bip: Fix unused pins and those with exter...
by build bot (Jenkins) (Code Review) 26 Jul '18

26 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27634 ) Change subject: mb/google/octopusi/variants/bip: Fix unused pins and those with external terminations ...................................................................... Patch Set 2: (23 comments) https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/bip/gpio.c: https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 96: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 131: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 133: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 134: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 137: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 141: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 147: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 148: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 166: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 167: PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 176: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 179: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 198: PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 202: PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 203: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 206: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 228: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 230: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 238: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 241: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 269: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 279: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters https://review.coreboot.org/#/c/27634/2/src/mainboard/google/octopus/varian… PS2, Line 306: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters -- To view, visit https://review.coreboot.org/27634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b Gerrit-Change-Number: 27634 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Jul 2018 23:44:30 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus/variants/phaser: Provide override GPIO config
by Furquan Shaikh (Code Review) 26 Jul '18

26 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27642 Change subject: mb/google/octopus/variants/phaser: Provide override GPIO config ...................................................................... mb/google/octopus/variants/phaser: Provide override GPIO config This change provides override GPIO table for variant phaser depending upon the board id. BUG=b:111743717 TEST=Verified that GPIO configuration for the override GPIOs is different than before with this change. Change-Id: I4d2e829e1b886299442c17cecc069854b742b43c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/phaser/Makefile.inc A src/mainboard/google/octopus/variants/phaser/gpio.c 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27642/1 diff --git a/src/mainboard/google/octopus/variants/phaser/Makefile.inc b/src/mainboard/google/octopus/variants/phaser/Makefile.inc index 1644083..5cb5a05 100644 --- a/src/mainboard/google/octopus/variants/phaser/Makefile.inc +++ b/src/mainboard/google/octopus/variants/phaser/Makefile.inc @@ -1 +1,2 @@ ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c new file mode 100644 index 0000000..54eb95d --- /dev/null +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <console/console.h> +#include <soc/gpio.h> + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_161, DN_20K), + PAD_NC(GPIO_213, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +static const struct pad_config bid0_override_table[] = { + PAD_NC(GPIO_52, UP_20K), + PAD_NC(GPIO_53, UP_20K), + PAD_NC(GPIO_67, UP_20K), + PAD_NC(GPIO_117, UP_20K), + PAD_NC(GPIO_143, UP_20K), + PAD_NC(GPIO_161, DN_20K), + PAD_NC(GPIO_214, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + const struct pad_config *c; + + switch (board_id()) { + case 0: + case UNDEFINED_STRAPPING_ID: + c = bid0_override_table; + *num = ARRAY_SIZE(bid0_override_table); + break; + default: + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); + } + + return c; +} -- To view, visit https://review.coreboot.org/27642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4d2e829e1b886299442c17cecc069854b742b43c Gerrit-Change-Number: 27642 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: Stoneyridge: Remove IMC support
by Richard Spiegel (Code Review) 25 Jul '18

25 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27639 to look at the new patch set (#2). Change subject: Stoneyridge: Remove IMC support ...................................................................... Stoneyridge: Remove IMC support An agreement between AMD and Google decided to remove all support to IMC. All boards will use external EC. Remove all stoney IMC files and functions from coreboot. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I1bda0ac7f8f8f5bb1403396d6703a4fac6f60f88 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/gardenia/Makefile.inc D src/mainboard/amd/gardenia/fchec.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/Makefile.inc D src/soc/amd/stoneyridge/acpi/AmdImc.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl D src/soc/amd/stoneyridge/imc.c D src/soc/amd/stoneyridge/include/fchec.h D src/soc/amd/stoneyridge/include/soc/imc.h M src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/spi.c D src/vendorcode/amd/pi/00670F00/Lib/imc/HwmLateService.c D src/vendorcode/amd/pi/00670F00/Lib/imc/ImcLib.c M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h 16 files changed, 2 insertions(+), 832 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/27639/2 -- To view, visit https://review.coreboot.org/27639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1bda0ac7f8f8f5bb1403396d6703a4fac6f60f88 Gerrit-Change-Number: 27639 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/octopus: Use newly added gpio_configure_pads_with_override
by Furquan Shaikh (Code Review) 25 Jul '18

25 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27641 Change subject: mb/google/octopus: Use newly added gpio_configure_pads_with_override ...................................................................... mb/google/octopus: Use newly added gpio_configure_pads_with_override This change updates mainboard_init to call gpio_configure_pads_with_override instead of gpio_configure_pads to allow variants to provide overrides for the GPIO config table provided by the baseboard. BUG=b:111743717 TEST=Verified on phaser that GPIO config with and without this change is the same. Change-Id: I494a950100e5ec82504d652ff6e8a75746456d1f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/octopus/variants/bip/gpio.c 4 files changed, 18 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/27641/1 diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index eda44ba..4876d10 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -32,14 +32,18 @@ static void mainboard_init(void *chip_info) { int boardid; - const struct pad_config *pads; - size_t num; + const struct pad_config *base_pads; + const struct pad_config *override_pads; + size_t base_num, override_num; boardid = board_id(); printk(BIOS_INFO, "Board ID: %d\n", boardid); - pads = variant_gpio_table(&num); - gpio_configure_pads(pads, num); + base_pads = variant_base_gpio_table(&base_num); + override_pads = variant_override_gpio_table(&override_num); + + gpio_configure_pads_with_override(base_pads, base_num, + override_pads, override_num); mainboard_ec_init(); } diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 7b1075f..3dee892 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -281,12 +281,18 @@ PAD_NC(GPIO_210, DN_20K), }; -const struct pad_config *__weak variant_gpio_table(size_t *num) +const struct pad_config *__weak variant_base_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } +const struct pad_config *__weak variant_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h index 4c3fbbe..666e562 100644 --- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h @@ -26,7 +26,8 @@ /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ -const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_base_gpio_table(size_t *num); +const struct pad_config *variant_override_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_sleep_gpio_table(size_t *num, int slp_typ); diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c index 5f83ee4..18cb6d9 100644 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ b/src/mainboard/google/octopus/variants/bip/gpio.c @@ -259,7 +259,7 @@ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 0, DEEP, NONE, HIZCRx0, DISPUPD), }; -const struct pad_config *variant_gpio_table(size_t *num) +const struct pad_config *variant_base_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; -- To view, visit https://review.coreboot.org/27641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I494a950100e5ec82504d652ff6e8a75746456d1f Gerrit-Change-Number: 27641 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/common/block/gpio: Add API for gpio_configure_pads_with_ove...
by Furquan Shaikh (Code Review) 25 Jul '18

25 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27640 Change subject: soc/intel/common/block/gpio: Add API for gpio_configure_pads_with_override ...................................................................... soc/intel/common/block/gpio: Add API for gpio_configure_pads_with_override This function adds support for gpio_configure_pads_with_override which: 1. Takes as input two GPIO tables -- base config table and override config table 2. Configures each pad in base config by first checking if there is a config available for the pad in override config table. If yes, then uses the one from override config table. Else, uses the base config to configure the pad. This is done to allow sharing of GPIO tables across baseboard-variants for various boards i.e. Each board can have a base config table which is provided by the baseboard and an optional override config table that can be provided by a variant to configure certain GPIOs differently. It is helpful when the variant GPIO diff list is not very huge compared to the baseboard. BUG=b:111743717 TEST=Verified that the GPIO config for phaser is same with and without this change. Change-Id: I1c5dc72c8368957201ab53d2e8398ff861341a4c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/27640/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 50a3a02..931fb7f 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -288,6 +288,43 @@ gpio_configure_pad(cfg + i); } +/* + * This functions checks to see if there is an override config present for the + * provided pad_config. If no override config is present, then the input config + * is returned. Else, it returns the override config. + */ +static const struct pad_config *gpio_get_config(const struct pad_config *c, + const struct pad_config *override_cfg_table, + size_t num) +{ + size_t i; + + if (override_cfg_table == NULL) + return c; + + for (i = 0; i < num; i++) { + if (c->pad == override_cfg_table[i].pad) + return override_cfg_table + i; + } + + return c; +} + +void gpio_configure_pads_with_override(const struct pad_config *base_cfg, + size_t base_num_pads, + const struct pad_config *override_cfg, + size_t override_num_pads) +{ + size_t i; + const struct pad_config *c; + + for (i = 0; i < base_num_pads; i++) { + c = gpio_get_config(base_cfg + i, override_cfg, + override_num_pads); + gpio_configure_pad(c); + } +} + void *gpio_dwx_address(const gpio_t pad) { /* Calculate Address of DW0 register for given GPIO diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 625ebef..4e26db3 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -133,6 +133,21 @@ void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); /* + * gpio_configure_pads_with_override accepts as input two GPIO tables: + * 1. Base config + * 2. Override config + * + * This function configures raw pads in base config and applies override in + * override config if any. Thus, for every GPIO_x in base config, this function + * looks up the GPIO in override config and if it is present there, then applies + * the configuration from override config. + */ +void gpio_configure_pads_with_override(const struct pad_config *base_cfg, + size_t base_num_pads, + const struct pad_config *override_cfg, + size_t override_num_pads); + +/* * Calculate Address of DW0 register for given GPIO */ void *gpio_dwx_address(const gpio_t pad); -- To view, visit https://review.coreboot.org/27640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1c5dc72c8368957201ab53d2e8398ff861341a4c Gerrit-Change-Number: 27640 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: Stoneyridge: Remove IMC support
by Richard Spiegel (Code Review) 25 Jul '18

25 Jul '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27639 Change subject: Stoneyridge: Remove IMC support ...................................................................... Stoneyridge: Remove IMC support An agreement between AMD and Google decided to remove all support to IMC. All boards will use external EC. Remove all stoney IMC files and functions from coreboot. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I1bda0ac7f8f8f5bb1403396d6703a4fac6f60f88 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/gardenia/Makefile.inc D src/mainboard/amd/gardenia/fchec.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/Makefile.inc D src/soc/amd/stoneyridge/acpi/AmdImc.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl D src/soc/amd/stoneyridge/imc.c D src/soc/amd/stoneyridge/include/fchec.h D src/soc/amd/stoneyridge/include/soc/imc.h M src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/spi.c D src/vendorcode/amd/pi/00670F00/Lib/imc/HwmLateService.c D src/vendorcode/amd/pi/00670F00/Lib/imc/ImcLib.c M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h 16 files changed, 2 insertions(+), 831 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/27639/1 diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index 158642a..16ac549 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -15,31 +15,13 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> -#include <soc/imc.h> #include <soc/southbridge.h> #include <stdlib.h> #include <string.h> -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM will fail to read the input temperature via I2C if other - * software switches the I2C address. AMD recommends using IMC - * to control fans, instead of HWM. - */ void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ - imc_reg_init(); - FchParams->Imc.ImcEnable = TRUE; - - /* 1 IMC, 0 HWM */ - FchParams->Hwm.HwmControl = 1; - - /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - FchParams->Imc.ImcEnableOverWrite = 1; - - memset(&FchParams->Imc.EcStruct, 0, sizeof(FCH_EC)); } void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index 5ddfe45..dd71331 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -24,4 +24,3 @@ ramstage-y += BiosCallOuts.c ramstage-y += gpio.c ramstage-y += OemCustomize.c -ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += fchec.c diff --git a/src/mainboard/amd/gardenia/fchec.c b/src/mainboard/amd/gardenia/fchec.c deleted file mode 100644 index aca3a9e..0000000 --- a/src/mainboard/amd/gardenia/fchec.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "fchec.h" - -void agesawrapper_fchecfancontrolservice(void) -{ - FCH_DATA_BLOCK LateParams; - - /* Thermal Zone Parameter */ - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - /* SMBUS Address for SMBUS based temperature sensor */ - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - /* PWM steping rate in unit of PWM level percentage */ - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; - LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 in oC */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 in oC */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 undefined */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 undefined */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 undefined */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 undefined */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 undefined */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*crit threshold */ - LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percent */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percent */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percent */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percent */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percent */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percent */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percent */ - LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percent */ - - LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111; - - FchECfancontrolservice(&LateParams); -} diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index d2f7a32..e8e65d4 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -58,8 +58,6 @@ FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) - oem_fan_control(FchParams_env); /* XHCI configuration */ if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE)) diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 5df4889..bf5724f 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -57,7 +57,6 @@ romstage-y += romstage.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c romstage-y += gpio.c -romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c romstage-y += monotonic_timer.c romstage-y += pmutil.c romstage-y += reset.c @@ -100,7 +99,6 @@ ramstage-y += monotonic_timer.c ramstage-y += southbridge.c ramstage-y += sb_util.c -ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c ramstage-y += lpc.c ramstage-y += northbridge.c ramstage-y += pmutil.c @@ -200,7 +198,6 @@ add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) -OPT_STONEYRIDGE_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_IMC_FWM_FILE), --imc) OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILEddd), --gec) OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey2) @@ -222,7 +219,6 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_STONEYRIDGE_IMC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ @@ -243,7 +239,6 @@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(OPT_STONEYRIDGE_XHCI_FWM_FILE) \ - $(OPT_STONEYRIDGE_IMC_FWM_FILE) \ $(OPT_STONEYRIDGE_GEC_FWM_FILE) \ $(OPT_AMD_PUBKEY_FILE) \ $(OPT_PSPBTLDR_FILE) \ diff --git a/src/soc/amd/stoneyridge/acpi/AmdImc.asl b/src/soc/amd/stoneyridge/acpi/AmdImc.asl deleted file mode 100644 index 519b05c..0000000 --- a/src/soc/amd/stoneyridge/acpi/AmdImc.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -//BTDC Due to IMC Fan, ACPI control codes -OperationRegion(IMIO, SystemIO, 0x3E, 0x02) -Field(IMIO , ByteAcc, NoLock, Preserve) { - IMCX,8, - IMCA,8 -} - -IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { - Offset(0x80), - MSTI, 8, - MITS, 8, - MRG0, 8, - MRG1, 8, - MRG2, 8, - MRG3, 8, -} - -Method(WACK, 0) -{ - Store(0, Local0) - While (LNotEqual(Local0, 0xFA)) { - Store(MRG0, Local0) - Sleep(10) - } -} - -//Init -Method (ITZE, 0) -{ - Store(0, MRG0) - Store(0xB5, MRG1) - Store(0, MRG2) - Store(0x96, MSTI) - WACK() - - Store(0, MRG0) - Store(0, MRG1) - Store(0, MRG2) - Store(0x80, MSTI) - WACK() - - Or(MRG2, 0x01, Local0) - - Store(0, MRG0) - Store(0, MRG1) - Store(Local0, MRG2) - Store(0x81, MSTI) - WACK() -} diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index e767fdd..4aba2f9 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -130,10 +130,6 @@ Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ -#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) - #include "acpi/AmdImc.asl" -#endif - /* * * FIRST METHOD CALLED UPON BOOT @@ -159,11 +155,6 @@ /* Determine the OS we're running on */ OSFL() -#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) -#if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) - ITZE() /* enable IMC Fan Control*/ -#endif -#endif } /* End Method(_SB._INI) */ Method(OSFL, 0){ diff --git a/src/soc/amd/stoneyridge/imc.c b/src/soc/amd/stoneyridge/imc.c deleted file mode 100644 index 5d883d9..0000000 --- a/src/soc/amd/stoneyridge/imc.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <amdblocks/agesawrapper.h> -#include <soc/imc.h> -#include <arch/io.h> -#include <device/device.h> -#include <delay.h> - -#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) - -void imc_reg_init(void) -{ - u8 reg8; - /* Init Power Management Block 2 (PM2) Registers. - * Check BKDG for AMD Family 16h for details. */ - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x00), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x01), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x02), 0xf7); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x03), 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x04), 0xff); - - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x10), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x11), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x12), 0xf7); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff); - - reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1e4); - reg8 &= 0x8f; - reg8 |= 0x10; - pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1e4, reg8); -} - -void enable_imc_thermal_zone(void) -{ - AMD_CONFIG_PARAMS StdHeader; - UINT8 FunNum; - UINT8 regs[10]; - int i; - - regs[0] = 0; - regs[1] = 0; - FunNum = Fun_80; - for (i = 0 ; i <= 1 ; i++) - WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); - WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); - WaitForEcLDN9MailboxCmdAck(&StdHeader); - - for (i = 2 ; i < ARRAY_SIZE(regs) ; i++) - ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); - - /* enable thermal zone 0 */ - regs[2] |= 1; - regs[0] = 0; - regs[1] = 0; - FunNum = Fun_81; - for (i = 0 ; i < ARRAY_SIZE(regs) ; i++) - WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader); - WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); - WaitForEcLDN9MailboxCmdAck(&StdHeader); -} - -void imc_sleep(void) -{ - ImcSleep(NULL); -} - -void imc_wakeup(void) -{ - ImcWakeup(NULL); -} diff --git a/src/soc/amd/stoneyridge/include/fchec.h b/src/soc/amd/stoneyridge/include/fchec.h deleted file mode 100644 index 80125ec..0000000 --- a/src/soc/amd/stoneyridge/include/fchec.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __AMD_STONEY_FCHEC__ -#define __AMD_STONEY_FCHEC__ - -#include <amdblocks/agesawrapper.h> -#include <soc/imc.h> - -void agesawrapper_fchecfancontrolservice(void); - -#endif diff --git a/src/soc/amd/stoneyridge/include/soc/imc.h b/src/soc/amd/stoneyridge/include/soc/imc.h deleted file mode 100644 index 079df79..0000000 --- a/src/soc/amd/stoneyridge/include/soc/imc.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __STONEYRIDGE_IMC_H__ -#define __STONEYRIDGE_IMC_H__ - -void imc_reg_init(void); -void enable_imc_thermal_zone(void); -void imc_sleep(void); -void imc_wakeup(void); - -#endif diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 18e6c6c..e893cb7 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -25,10 +25,10 @@ #include <cbmem.h> #include <elog.h> #include <amdblocks/amd_pci_util.h> +#include <amdblocks/agesawrapper.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> -#include <fchec.h> #include <delay.h> #include <soc/pci_devs.h> #include <agesa_headers.h> @@ -766,11 +766,6 @@ { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; - if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) { - agesawrapper_fchecfancontrolservice(); - if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) - enable_imc_thermal_zone(); - } if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE)) restored_power = PM_RESTORE_S0_IF_PREV_S0; pm_write8(PM_RTC_SHADOW, restored_power); diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index 718ad94..9baf433 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -29,7 +29,6 @@ #include <device/pci_ops.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <soc/imc.h> #define SPI_DEBUG_DRIVER IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) @@ -169,15 +168,11 @@ int chipset_volatile_group_begin(const struct spi_flash *flash) { - if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) - imc_sleep(); return 0; } int chipset_volatile_group_end(const struct spi_flash *flash) { - if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) - imc_wakeup(); return 0; } diff --git a/src/vendorcode/amd/pi/00670F00/Lib/imc/HwmLateService.c b/src/vendorcode/amd/pi/00670F00/Lib/imc/HwmLateService.c deleted file mode 100644 index 8800e38..0000000 --- a/src/vendorcode/amd/pi/00670F00/Lib/imc/HwmLateService.c +++ /dev/null @@ -1,188 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Config FCH Hwm controller - * - * Init Hwm Controller features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" -#include "Filecode.h" -#define FILECODE PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMLATESERVICE_FILECODE - -/** - * Table for Function Number - * - * - * - * - */ -STATIC UINT8 FunctionNumber[] = -{ - Fun_81, - Fun_83, - Fun_85, - Fun_89, -}; - -/** - * Table for Max Thermal Zone - * - * - * - * - */ -UINT8 MaxZone[] = -{ - 4, - 4, - 4, - 4, -}; - - -/** - * Table for Max Register - * - * - * - * - */ -UINT8 MaxRegister[] = -{ - MSG_REG9, - MSG_REGB, - MSG_REG9, - MSG_REGA, -}; - -/*------------------------------------------------------------------------------- -;Procedure: IsZoneFuncEnable -; -;Description: This routine will check every zone support function with BitMap from user define -; -; -;Exit: None -; -;Modified: None -; -;----------------------------------------------------------------------------- -*/ -STATIC BOOLEAN -IsZoneFuncEnable ( - IN UINT16 Flag, - IN UINT8 func, - IN UINT8 Zone - ) -{ - return (BOOLEAN) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone)); -} - -/*------------------------------------------------------------------------------- -;Procedure: FchECfancontrolservice -; -;Description: This routine service EC fan policy -; -; -;Exit: None -; -;Modified: None -; -;----------------------------------------------------------------------------- -*/ -VOID -FchECfancontrolservice ( - IN VOID *FchDataPtr - ) -{ - UINT8 ZoneNum; - UINT8 FunNum; - UINT8 RegNum; - UINT8 *CurPoint; - UINT8 FunIndex; - BOOLEAN IsSendEcMsg; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - if (!IsImcEnabled (StdHeader)) { - return; //IMC is not enabled - } - - CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1); - - for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) { - FunNum = FunctionNumber[FunIndex]; - for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { - IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); - if (IsSendEcMsg) { - for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { - WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader); - CurPoint += 1; - } - WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number - WaitForEcLDN9MailboxCmdAck (StdHeader); - } else { - CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1); - } - } - } - - CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0; - for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) { - FunNum = FunctionNumber[FunIndex]; - for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { - IsSendEcMsg = IsZoneFuncEnable (LocalCfgPtr->Imc.EcStruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); - if (IsSendEcMsg) { - for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { - if (RegNum == MSG_REG2) { - *CurPoint &= 0xFE; - } - WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader); - CurPoint += 1; - } - WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number - WaitForEcLDN9MailboxCmdAck (StdHeader); - } else { - CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1); - } - } - } -} diff --git a/src/vendorcode/amd/pi/00670F00/Lib/imc/ImcLib.c b/src/vendorcode/amd/pi/00670F00/Lib/imc/ImcLib.c deleted file mode 100644 index 3a5f8cd..0000000 --- a/src/vendorcode/amd/pi/00670F00/Lib/imc/ImcLib.c +++ /dev/null @@ -1,312 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * FCH IMC lib - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: FCH - * @e \$Revision: 87213 $ @e \$Date: 2013-01-30 15:37:54 -0600 (Wed, 30 Jan 2013) $ - * - */ -/* -***************************************************************************** -* - * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -**************************************************************************** -*/ -#include "FchPlatform.h" - -/** - * WriteECmsg - * - * - * - * @param[in] Address - Address - * @param[in] OpFlag - Access width - * @param[in] *Value - Out Value pointer - * @param[in] StdHeader - * - */ -VOID -WriteECmsg ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - - ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */ - OpFlag = (OpFlag & 0x7f) - 1; - if (OpFlag == 0x02) { - OpFlag = 0x03; - } - - for (Index = 0; Index <= OpFlag; Index++) { - /// EC_LDN9_MAILBOX_BASE_ADDRESS - LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader); - Address++; - /// EC_LDN9_MAILBOX_BASE_ADDRESS - LibAmdIoWrite (AccessWidth8, MailBoxPort + 1, (UINT8 *)Value + Index, StdHeader); - } -} - -/** - * ReadECmsg - * - * - * - * @param[in] Address - Address - * @param[in] OpFlag - Access width - * @param[out] *Value - Out Value pointer - * @param[in] StdHeader - * - */ -VOID -ReadECmsg ( - IN UINT8 Address, - IN UINT8 OpFlag, - OUT VOID *Value, - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Index; - - ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */ - OpFlag = (OpFlag & 0x7f) - 1; - if (OpFlag == 0x02) { - OpFlag = 0x03; - } - - for (Index = 0; Index <= OpFlag; Index++) { - /// EC_LDN9_MAILBOX_BASE_ADDRESS - LibAmdIoWrite (AccessWidth8, MailBoxPort, &Address, StdHeader); - Address++; - /// EC_LDN9_MAILBOX_BASE_ADDRESS - LibAmdIoRead (AccessWidth8, MailBoxPort + 1, (UINT8 *)Value + Index, StdHeader); - } -} - -/** - * WaitForEcLDN9MailboxCmdAck - * - * - * @param[in] StdHeader - * - */ -VOID -WaitForEcLDN9MailboxCmdAck ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - UINT8 Msgdata; - UINT16 Delaytime; - - Msgdata = 0; - - for (Delaytime = 0; Delaytime < 0xFFFF; Delaytime++) { - ReadECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); - if ( Msgdata == 0xfa) { - break; - } - - FchStall (5, StdHeader); /// Wait for 1ms - } -} - -/** - * ImcSleep - IMC Sleep. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcSleep ( - IN VOID *FchDataPtr - ) -{ - UINT8 Msgdata; - FCH_DATA_BLOCK *LocalCfgPtr; - AMD_CONFIG_PARAMS *StdHeader; - - LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; - StdHeader = LocalCfgPtr->StdHeader; - - if (!(IsImcEnabled (StdHeader)) ) { - return; ///IMC is not enabled - } - - Msgdata = 0x00; - WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0xB4; - WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x00; - WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x96; - WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); - WaitForEcLDN9MailboxCmdAck (StdHeader); -} - -/** - * SoftwareDisableImc - Software disable IMC strap - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -SoftwareDisableImc ( - IN VOID *FchDataPtr - ) -{ - UINT8 ValueByte; - UINT8 PortStatusByte; - UINT32 AbValue; - UINT32 ABStrapOverrideReg; - AMD_CONFIG_PARAMS *StdHeader; - - StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; - GetChipSysMode (&PortStatusByte, StdHeader); - - RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader); - ReadPmio (0xBF, AccessWidth8, &ValueByte, StdHeader); - - ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue); - ABStrapOverrideReg = AbValue; - ABStrapOverrideReg &= ~BIT2; // bit2=0 EcEnableStrap - WriteMem ((ACPI_MMIO_BASE + MISC_BASE + 0x84), AccessWidth32, &ABStrapOverrideReg); - - ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader); - ValueByte |= BIT1; - WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader); - - ValueByte = 06; - LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader); - FchStall (0xffffffff, StdHeader); -} - -/** - * ImcDisableSurebootTimer - IMC Disable Sureboot Timer. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcDisableSurebootTimer ( - IN VOID *FchDataPtr - ) -{ - UINT8 Msgdata; - AMD_CONFIG_PARAMS *StdHeader; - - StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; - - if (!(IsImcEnabled (StdHeader)) ) { - return; ///IMC is not enabled - } - - ImcWakeup (FchDataPtr); - Msgdata = 0x00; - WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x01; - WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x00; - WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x94; - WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); - WaitForEcLDN9MailboxCmdAck (StdHeader); - ImcSleep (FchDataPtr); -} - -/** - * ImcWakeup - IMC Wakeup. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcWakeup ( - IN VOID *FchDataPtr - ) -{ - UINT8 Msgdata; - AMD_CONFIG_PARAMS *StdHeader; - - StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; - if (!(IsImcEnabled (StdHeader)) ) { - return; ///IMC is not enabled - } - - Msgdata = 0x00; - WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0xB5; - WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x00; - WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x96; - WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); - WaitForEcLDN9MailboxCmdAck (StdHeader); -} - -/** - * ImcIdle - IMC Idle. - * - * - * @param[in] FchDataPtr Fch configuration structure pointer. - * - */ -VOID -ImcIdle ( - IN VOID *FchDataPtr - ) -{ - UINT8 Msgdata; - AMD_CONFIG_PARAMS *StdHeader; - - StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader; - - if (!(IsImcEnabled (StdHeader)) ) { - return; ///IMC is not enabled - } - - Msgdata = 0x00; - WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x01; - WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x00; - WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader); - Msgdata = 0x98; - WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader); - WaitForEcLDN9MailboxCmdAck (StdHeader); -} diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 26a6007..bd807a9 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -94,11 +94,6 @@ agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS]) endif agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS]) -ifeq ($(CONFIG_STONEYRIDGE_IMC_FWM),y) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Lib/imc/*.c) -agesa_raw_files += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c -agesa_raw_files += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c -endif classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h index c80dc52..42017bb 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h @@ -62,7 +62,6 @@ VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl); VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader); VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); @@ -183,18 +182,14 @@ /// -/// Fch Imc Routines +/// Fch EC Routines /// /// Pei Phase /// -VOID FchInitResetImc (IN VOID *FchDataPtr); VOID FchInitResetEc (IN VOID *FchDataPtr); /// /// Dxe Phase /// -VOID FchInitEnvImc (IN VOID *FchDataPtr); -VOID FchInitMidImc (IN VOID *FchDataPtr); -VOID FchInitLateImc (IN VOID *FchDataPtr); VOID FchInitEnvEc (IN VOID *FchDataPtr); VOID FchInitMidEc (IN VOID *FchDataPtr); VOID FchInitLateEc (IN VOID *FchDataPtr); @@ -210,17 +205,6 @@ VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader); -VOID ImcSleep (IN VOID *FchDataPtr); -VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr); -VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr); -VOID ImcWakeup (IN VOID *FchDataPtr); -VOID ImcIdle (IN VOID *FchDataPtr); -BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr); -VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr); -VOID ImcCrashReset (IN VOID *FchDataPtr); -VOID SoftwareDisableImc (IN VOID *FchDataPtr); - - /// /// Fch Ir Routines /// -- To view, visit https://review.coreboot.org/27639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1bda0ac7f8f8f5bb1403396d6703a4fac6f60f88 Gerrit-Change-Number: 27639 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/google/octopusi/variants/bip: Fix unused pins and those with exter...
by build bot (Jenkins) (Code Review) 25 Jul '18

25 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27634 ) Change subject: mb/google/octopusi/variants/bip: Fix unused pins and those with external terminations ...................................................................... Patch Set 1: (23 comments) https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/bip/gpio.c: https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 96: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 138: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 140: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 141: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 144: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 148: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 154: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 155: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 173: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 174: PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 183: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 186: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 206: PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 210: PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 211: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 214: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 236: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 238: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 246: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 249: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 277: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 287: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters https://review.coreboot.org/#/c/27634/1/src/mainboard/google/octopus/varian… PS1, Line 314: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters -- To view, visit https://review.coreboot.org/27634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b Gerrit-Change-Number: 27634 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Jul 2018 16:02:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/octopus: Fix unused pins and those with external terminations
by build bot (Jenkins) (Code Review) 25 Jul '18

25 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27183 ) Change subject: mb/google/octopus: Fix unused pins and those with external terminations ...................................................................... Patch Set 5: (22 comments) https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 98: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 133: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 135: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 136: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 139: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 143: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 149: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 150: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 168: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 169: PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 181: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 200: PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 204: PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 207: PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 226: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RXDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 229: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 231: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 239: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 242: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 270: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 280: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ line over 80 characters https://review.coreboot.org/#/c/27183/5/src/mainboard/google/octopus/varian… PS5, Line 307: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ line over 80 characters -- To view, visit https://review.coreboot.org/27183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I67ec62913b0ef47105289838218f5d74c004223c Gerrit-Change-Number: 27183 Gerrit-PatchSet: 5 Gerrit-Owner: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Peter Lin <peterlin(a)ami.corp-partner.google.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Jul 2018 16:02:43 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopusi/variants/bip: Fix unused pins and those with exter...
by Furquan Shaikh (Code Review) 25 Jul '18

25 Jul '18

Hello Shamile Khan, I'd like you to do a code review. Please visit https://review.coreboot.org/27634 to review the following change. Change subject: mb/google/octopusi/variants/bip: Fix unused pins and those with external terminations ...................................................................... mb/google/octopusi/variants/bip: Fix unused pins and those with external terminations For unused pins, configure them as GPIO input and use the default termination. For the pins where board has an external termination, remove SOC's internal termintation. BUG=b:110654510 TEST=On Bip, flashed image and verified that it boots to OS. Also executed a few suspend resume cycles. Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b Signed-off-by: Shamile Khan <shamile.khan(a)intel.com> --- M src/mainboard/google/octopus/variants/bip/gpio.c 1 file changed, 99 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/27634/1 diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c index 5f83ee4..9d15c72 100644 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ b/src/mainboard/google/octopus/variants/bip/gpio.c @@ -24,14 +24,14 @@ */ static const struct pad_config gpio_table[] = { /* NORTHWEST COMMUNITY GPIOS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TCK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, IGNORE, ENPD), /* TRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TMS */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, UP_20K, DEEP, NF1, IGNORE, ENPU), /* TDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), /* JTAGX */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PREQ_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), /* CX_PRDY_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_0, NONE, DEEP, NF1), /* TCK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_1, DN_20K, DEEP, NF1), /* TRST_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_2, NONE, DEEP, NF1), /* TMS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_3, NONE, DEEP, NF1), /* TDI */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_4, NONE, DEEP, NF1), /* TDO */ + PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_6, UP_20K, DEEP, NF1), /* CX_PREQ_B */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_7, UP_20K, DEEP, NF1), /* CX_PRDY_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ @@ -63,44 +63,46 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA3_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA4_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA5_VNN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_42, 0, DEEP, DN_20K, HIZCRx1, DISPUPD), /* GP_INTD_DSI_TE1 */ + PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */ + PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */ + PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */ + PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_46, 0, DEEP, DN_20K, HIZCRx0, DISPUPD), /* DSI_I2C_SDA */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_47, 0, DEEP, DN_20K, HIZCRx0, DISPUPD), /* DSI_I2C_SCL */ + PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */ + PAD_NC(GPIO_47, DN_20K), /* DSI_I2C_SCL -- unused */ + + /* PMC stays active in suspend so disable standby for these pins */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C0_SCL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_54, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* LPSS_I2C2_SDA -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_55, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* LPSS_I2C2_SCL -- unused */ + PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */ + PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ - PAD_CFG_GPIO_HI_Z(GPIO_58, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SDA - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_59, NONE, DEEP, HIZCRx0, DISPUPD), /* LPSS_I2C4_SCL - unused */ + PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA - unused */ + PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL - unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ - PAD_CFG_GPI_APIC_IOS(GPIO_62, UP_20K, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* UART0-RTS_B */ + PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, HIZCRx0, DISPUPD), /* UART2-RTS_B -- LTE_OFF_ODL*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, Tx0RxDCRx0, DISPUPD), /* UART2-CTS_B */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */ PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */ PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */ PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_72, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_TXD */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_CLK */ + PAD_NC(GPIO_72, DN_20K), /* PMC_SPI_TXD -- unused */ + PAD_NC(GPIO_73, DN_20K), /* PMC_SPI_CLK -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_211, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* EMMC_RST_B */ + PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */ PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* P_SENSOR_INT_L */ @@ -108,9 +110,9 @@ /* NORTH COMMUNITY GPIOS */ /* svid - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_76, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Alert - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_77, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Data - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_78, NONE, DEEP, HIZCRx0, DISPUPD),/* SVID Clk - unused */ + PAD_NC(GPIO_76, UP_20K),/* SVID Alert - unused */ + PAD_NC(GPIO_77, UP_20K),/* SVID Data - unused */ + PAD_NC(GPIO_78, UP_20K),/* SVID Clk - unused */ /* LPSS */ PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ @@ -118,6 +120,13 @@ PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */ PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ + PAD_NC(GPIO_84, DN_20K), /* LPSS_SPI_2_CLK - unused */ + PAD_NC(GPIO_85, DN_20K), /* LPSS_SPI_2_FS0 - unused */ + PAD_NC(GPIO_86, DN_20K), /* LPSS_SPI_2_FS1 - unused */ + PAD_NC(GPIO_87, DN_20K), /* LPSS_SPI_2_FS2 - unused */ + PAD_NC(GPIO_88, DN_20K), /* LPSS_SPI_2_RXD - unused */ + PAD_NC(GPIO_89, DN_20K), /* LPSS_SPI_2_TXD - unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_84, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* LPSS_SPI_2_CLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_85, DN_20K, DEEP, NF1, HIZCRx1, ENPU), /* LPSS_SPI_2_FS0 */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_86, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* stest_CNTRL -- stest */ @@ -126,26 +135,26 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_89, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* LPSS_SPI_2_TXD */ /* Fast SPI */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, DN_20K, DEEP, NF1, HIZCRx1, ENPU),/* FST_SPI_CS0_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* FST_SPI_MOSI_IO0 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* FST_SPI_MISO_IO1 */ - PAD_CFG_GPIO_HI_Z(GPIO_94, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO2 - unused */ - PAD_CFG_GPIO_HI_Z(GPIO_95, NONE, DEEP, HIZCRx0, DISPUPD),/* FST_SPI_IO3 - unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, DN_20K, DEEP, NF1, HIZCRx0, ENPD),/* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */ + PAD_NC(GPIO_94, NATIVE),/* FST_SPI_IO2 - unused */ + PAD_NC(GPIO_95, NATIVE),/* FST_SPI_IO3 - unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */ /* PMU Signals */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_PLTRST_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, UP_20K, DEEP, NF1, TxDRxE, ENPU),/* PMU_PWRBTN_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, NONE, DEEP, NF1, HIZCRx0, DISPUPD),/* EMMC_DNX_PWR_EN_B - unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PMU_BATLOW_B */ + PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/* PMU_SUSCLK */ + PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */ /* I2C5 - Audio */ @@ -161,22 +170,26 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */ /* PCIE_WAKE[0:3]_B */ - PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */ - PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */ + PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ + PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */ PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */ - /* PCIE_CLKREQ[0:3]_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/ + /* + * PCIE_CLKREQ[0:3]_B. For unused pins, follow the termination + * guideline for unused PCIE ports as described in PDG i.e. keep + * the pins in native mode and deploy the internal pull up. + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */ /* DDI[0:1] SDA and SCL -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_124, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SDA -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_125, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SCL -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_126, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SDA -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_127, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI1_DDC_SCL -- unused */ + PAD_NC(GPIO_124, UP_20K),/* HV_DDI0_DDC_SDA -- unused */ + PAD_NC(GPIO_125, UP_20K),/* HV_DDI0_DDC_SCL -- unused */ + PAD_NC(GPIO_126, UP_20K),/* HV_DDI1_DDC_SDA -- unused */ + PAD_NC(GPIO_127, UP_20K),/* HV_DDI1_DDC_SCL -- unused */ /* Panel 0 control */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/ @@ -190,17 +203,15 @@ // TODO Need to set HIZCRx1 PAD_CFG_GPI(GPIO_134, NONE, DEEP),/* GPIO_134 -- SD_CD_OD */ - PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_135, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, EDGE_BOTH, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ - PAD_CFG_GPI(GPIO_138, NONE, DEEP),/* GPIO_138 -- PEN_PDCT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_INT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ + PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ - // TODO check if it is ok to set to GPIROUTSCI (as in Coral/Reef and others). - // Settings here do not match table // Also we may be able to use eSPI WAKE# Virtual Wire instead - PAD_CFG_GPI_SCI_IOS(GPIO_141, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, SAME),/* GPIO_141 -- EC_PCH_WAKE_ODL */ + PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_144, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_VDDN */ @@ -214,38 +225,56 @@ */ /* AUDIO COMMUNITY GPIOS*/ - PAD_CFG_GPIO_HI_Z(GPIO_156, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_MCLK -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_157, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_BCLK -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_158, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_WS_SYNC -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_159, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_SDI -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_160, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_SDO -- unused */ - PAD_CFG_GPIO_HI_Z(GPIO_161, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S1_MCLK -- unused */ + PAD_NC(GPIO_156, DN_20K), /* AVS_I2S0_MCLK -- unused */ + PAD_NC(GPIO_157, DN_20K),/* AVS_I2S0_BCLK -- unused */ + PAD_NC(GPIO_158, DN_20K),/* AVS_I2S0_WS_SYNC -- unused */ + PAD_NC(GPIO_159, DN_20K),/* AVS_I2S0_SDI -- unused */ + PAD_NC(GPIO_160, DN_20K),/* AVS_I2S0_SDO -- unused */ + PAD_NC(GPIO_161, DN_20K),/* AVS_I2S1_MCLK -- unused */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, SAME), /* AVS_I2S2_BCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */ + + /* Disable standby for GPIO_171 and GPIO_173 to support Wake on Voice */ PAD_CFG_NF_IOSSTATE(GPIO_171, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_A1 */ - PAD_CFG_NF_IOSSTATE(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_CLK_B1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */ PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_1 */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_174, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* AVS_M_CLK_AB2*/ - PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx0), /* AVS_M_DATA_2 */ + PAD_NC(GPIO_174, DN_20K), /* AVS_M_CLK_AB2 -- unused */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */ /* SCC COMMUNITY GPIOS */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_176, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_ALERTB */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_177, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_CLK */ + PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */ + PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ + PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */ + PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */ + PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */ + PAD_NC(GPIO_182, UP_20K), /* SDCARD_D1 -- unused */ + PAD_NC(GPIO_183, UP_20K), /* SDCARD_D2 -- unused */ + PAD_NC(GPIO_184, UP_20K), /* SDCARD_D3 -- unused */ + PAD_NC(GPIO_185, UP_20K), /* SDCARD_CMD -- unused */ + PAD_NC(GPIO_186, UP_20K), /* SDCARD_CD_N -- unused */ + PAD_NC(GPIO_187, NONE), /* SDCARD_LVL_WP -- unused */ + PAD_NC(GPIO_188, UP_20K), /* SDCARD_PWR_DWN_N -- unused */ PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ + PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ + + /* + * Disable standby state for these CNVI pins to allow wake on + * WiFI & Bluetooth. + */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC0_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */ @@ -255,8 +284,8 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0, ENPU), /* EMMC0_STROBE */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 0, DEEP, NONE, HIZCRx0, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */ + PAD_NC(GPIO_210, DN_20K), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -282,7 +311,7 @@ /* Enable power to wifi early in bootblock and de-assert PERST#. */ PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* WLAN_PE_RST */ /* * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak -- To view, visit https://review.coreboot.org/27634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b Gerrit-Change-Number: 27634 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com>

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Change in coreboot[master]: drivers/tpm: Add TPM ramstage driver for devices without vboot.
by Philipp Deppenwiese (Code Review) 25 Jul '18

25 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/24905 ) Change subject: drivers/tpm: Add TPM ramstage driver for devices without vboot. ...................................................................... drivers/tpm: Add TPM ramstage driver for devices without vboot. Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/haswell/romstage.c M src/drivers/intel/fsp1_1/romstage.c A src/drivers/tpm/Kconfig A src/drivers/tpm/Makefile.inc A src/drivers/tpm/tpm.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/rotor/Kconfig M src/mainboard/google/stout/romstage.c M src/mainboard/google/urara/Kconfig M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c 20 files changed, 43 insertions(+), 48 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 0e91dae..b30d4af 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -42,7 +42,6 @@ #include "northbridge/intel/haswell/raminit.h" #include "southbridge/intel/lynxpoint/pch.h" #include "southbridge/intel/lynxpoint/me.h" -#include <security/tpm/tspi.h> #include <cpu/intel/romstage.h> static inline void reset_system(void) @@ -157,6 +156,4 @@ romstage_handoff_init(wake_from_s3); post_code(0x3f); - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(wake_from_s3); } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 0320bf5..51f9a75 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -37,7 +37,6 @@ #include <stage_cache.h> #include <string.h> #include <timestamp.h> -#include <security/tpm/tspi.h> #include <vendorcode/google/chromeos/chromeos.h> asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) @@ -167,15 +166,6 @@ if (romstage_handoff_init( params->power_state->prev_sleep_state == ACPI_S3) < 0) hard_reset(); - - /* - * Initialize the TPM, unless the TPM was already initialized - * in verstage and used to verify romstage. - */ - if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) && - !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) - tpm_setup(params->power_state->prev_sleep_state == - ACPI_S3); } void after_cache_as_ram_stage(void) diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig new file mode 100644 index 0000000..8508210 --- /dev/null +++ b/src/drivers/tpm/Kconfig @@ -0,0 +1,7 @@ +config TPM_INIT + bool + default y if TPM1 || TPM2 + depends on !VBOOT + help + This driver automatically initializes the TPM if vboot is not used. + The TPM driver init is done during the ramstage chip init phase. diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc new file mode 100644 index 0000000..4e80600 --- /dev/null +++ b/src/drivers/tpm/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_TPM_INIT) += tpm.c diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c new file mode 100644 index 0000000..e4a81c3 --- /dev/null +++ b/src/drivers/tpm/tpm.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <stddef.h> +#include <bootstate.h> +#include <security/tpm/tspi.h> + +#if IS_ENABLED(CONFIG_ARCH_X86) +#include <arch/acpi.h> +#endif + +static void init_tpm_dev(void *unused) +{ +#if IS_ENABLED(CONFIG_ARCH_X86) + int s3resume = acpi_is_wakeup_s3(); + tpm_setup(s3resume); +#else + tpm_setup(false); +#endif +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, init_tpm_dev, NULL); diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 6188fcc..95fe630 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -46,7 +46,6 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> -#include <security/tpm/tspi.h> #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" @@ -624,9 +623,6 @@ pci_write_config16(PCI_DEV(0, 0x14, 0), 0x54, 0x0707); pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0); pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0); - - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(s3resume); } /** diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index d9f00f4..d7bf7c1 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -35,7 +35,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include <security/tpm/tspi.h> #include <cbfs.h> #include <southbridge/intel/bd82x6x/chip.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 6163c35..782d6e5 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -35,7 +35,6 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <cbfs.h> -#include <security/tpm/tspi.h> #include "ec/compal/ene932/ec.h" void pch_enable_lpc(void) diff --git a/src/mainboard/google/rotor/Kconfig b/src/mainboard/google/rotor/Kconfig index 7a86493..437fa02 100644 --- a/src/mainboard/google/rotor/Kconfig +++ b/src/mainboard/google/rotor/Kconfig @@ -20,8 +20,6 @@ select SOC_MARVELL_MVMAP2315 select MAINBOARD_HAS_CHROMEOS select BOARD_ROMSIZE_KB_4096 - select MAINBOARD_HAS_I2C_TPM_GENERIC - select MAINBOARD_HAS_TPM1 config VBOOT select VBOOT_MOCK_SECDATA diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 36ebcf7..f64e012 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -35,7 +35,6 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <bootmode.h> -#include <security/tpm/tspi.h> #include <cbfs.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index 2c4431c..3d415c4 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -24,8 +24,6 @@ select CPU_IMGTEC_PISTACHIO select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH - select MAINBOARD_HAS_I2C_TPM_GENERIC - select MAINBOARD_HAS_TPM1 config MAINBOARD_DIR string diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 9f46fe2..bdda191 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -35,7 +35,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include <security/tpm/tspi.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index d93cb8c..d4c60dd 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -35,7 +35,6 @@ #include <timestamp.h> #include <arch/acpi.h> #include <cbmem.h> -#include <security/tpm/tspi.h> #include "dock.h" #include "arch/early_variables.h" @@ -282,7 +281,4 @@ if (!s3resume) quick_ram_check(); - - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(s3resume); } diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 7ea89b8..e35afc0 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -33,7 +33,6 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <Fch/Fch.h> -#include <security/tpm/tspi.h> #include "gpio_ftns.h" @@ -103,9 +102,6 @@ post_code(0x41); AGESAWRAPPER(amdinitenv); - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(false); - outb(0xEA, 0xCD6); outb(0x1, 0xcd7); } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index cea206a..3f655da 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -28,7 +28,6 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> -#include <security/tpm/tspi.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index f502cc3..ffaff42 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -37,7 +37,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> -#include <security/tpm/tspi.h> #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 3bfefb9..3e128cd 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_def.h> #include <device/device.h> #include <halt.h> -#include <security/tpm/tspi.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> @@ -117,8 +116,5 @@ northbridge_romstage_finalize(s3resume); - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(s3resume); - post_code(0x3f); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index c971b35..027e0d8 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -30,7 +30,6 @@ #include <stage_cache.h> #include <string.h> #include <timestamp.h> -#include <security/tpm/tspi.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -228,9 +227,6 @@ timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); - - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(prev_sleep_state == ACPI_S3); } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 2fbe406..f485dfd 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -43,7 +43,6 @@ #include <soc/romstage.h> #include <soc/smm.h> #include <soc/spi.h> -#include <security/tpm/tspi.h> void program_base_addresses(void) { diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 1e2aa22..142f3b3 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -26,7 +26,6 @@ #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> -#include <security/tpm/tspi.h> #include <program_loading.h> #include <romstage_handoff.h> #include <stage_cache.h> @@ -110,9 +109,6 @@ timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); - - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(params->power_state->prev_sleep_state == ACPI_S3); } asmlinkage void romstage_after_car(void) -- To view, visit https://review.coreboot.org/24905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Gerrit-Change-Number: 24905 Gerrit-PatchSet: 19 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com>

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coreboot-gerrit July 2018