coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: [WIP]mb/opencellular/satima: Add new port
by build bot (Jenkins) (Code Review) 25 Jul '18

25 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27425 ) Change subject: [WIP]mb/opencellular/satima: Add new port ...................................................................... Patch Set 12: (174 comments) https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… File src/mainboard/opencellular/satima/cn81xx-linux.dtsi: https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 46: compatible = "cavium,thunder-81xx"; DT compatible string "cavium,thunder-81xx" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 46: compatible = "cavium,thunder-81xx"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 52: compatible = "arm,psci-0.2"; DT compatible string "arm,psci-0.2" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 52: compatible = "arm,psci-0.2"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 79: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "cavium,thunder" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 79: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 79: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "arm,armv8" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 79: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 88: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "cavium,thunder" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 88: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 88: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "arm,armv8" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 88: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 96: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "cavium,thunder" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 96: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 96: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "arm,armv8" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 96: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 104: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "cavium,thunder" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 104: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 104: compatible = "cavium,thunder", "arm,armv8"; DT compatible string "arm,armv8" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 104: compatible = "cavium,thunder", "arm,armv8"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 113: compatible = "cache"; DT compatible string "cache" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 118: compatible = "arm,armv8-timer"; DT compatible string "arm,armv8-timer" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 118: compatible = "arm,armv8-timer"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 126: compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; DT compatible string "cavium,thunder-pmu" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 126: compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 126: compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; DT compatible string "arm,armv8-pmuv3" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 126: compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 131: compatible = "regulator-fixed"; DT compatible string "regulator-fixed" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 141: compatible = "arm,gic-v3"; DT compatible string "arm,gic-v3" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 141: compatible = "arm,gic-v3"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 153: compatible = "arm,gic-v3-its"; DT compatible string "arm,gic-v3-its" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 153: compatible = "arm,gic-v3-its"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 161: compatible = "simple-bus"; DT compatible string "simple-bus" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 168: compatible = "fixed-clock"; DT compatible string "fixed-clock" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 175: compatible = "fixed-clock"; DT compatible string "fixed-clock" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 182: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,pl011" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 182: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 182: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,primecell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 182: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 191: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,pl011" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 191: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 191: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,primecell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 191: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 200: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,pl011" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 200: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 200: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,primecell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 200: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 209: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,pl011" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 209: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 209: compatible = "arm,pl011", "arm,primecell"; DT compatible string "arm,primecell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 209: compatible = "arm,pl011", "arm,primecell"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 218: compatible = "arm,sbsa-gwdt"; DT compatible string "arm,sbsa-gwdt" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 218: compatible = "arm,sbsa-gwdt"; DT compatible string vendor "arm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 219: reg = <0x8440 0xa0000 0x0 0x1000>, <0x8440 0xb0000 0x0 0x1000>; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 224: compatible = "cfi-flash"; DT compatible string "cfi-flash" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 232: compatible = "cavium,smmu-v2"; DT compatible string "cavium,smmu-v2" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 232: compatible = "cavium,smmu-v2"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 235: interrupts = <0 68 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 236: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 237: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 238: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 239: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 240: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 241: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 242: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 243: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 244: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 245: <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 255: compatible = "pci-host-ecam-generic"; DT compatible string "pci-host-ecam-generic" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 265: reg = <0x8480 0x00000000 0 0x02000000>; /* Configuration space */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 266: ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x080 0x00000000>, /* mem ranges */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 267: <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>, /* SATA */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 268: <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x160 0x28000000>, /* UARTs */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 269: <0x03000000 0x87e0 0x2c000000 0x87e0 0x2c000000 0x000 0x94000000>, /* PEMs */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 270: <0x03000000 0x8400 0x00000000 0x8400 0x00000000 0x010 0x00000000>, /* RNM */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 271: <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x02 0x00000000>, /* NIC0*/ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 272: <0x03000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x01f 0x3a000000>; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 275: compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; DT compatible string "pci-bridge" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 275: compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; DT compatible string "cavium,thunder-8890-mrml-bridge" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 275: compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 275: compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 278: ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 284: compatible = "cavium,thunder-8890-mdio-nexus"; DT compatible string "cavium,thunder-8890-mdio-nexus" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 284: compatible = "cavium,thunder-8890-mdio-nexus"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 284: compatible = "cavium,thunder-8890-mdio-nexus"; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 287: reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 288: assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 289: ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 291: compatible = "cavium,thunder-8890-mdio"; DT compatible string "cavium,thunder-8890-mdio" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 291: compatible = "cavium,thunder-8890-mdio"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 291: compatible = "cavium,thunder-8890-mdio"; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 294: reg = <0x87e0 0x05003800 0x0 0x30>; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 297: compatible = "cavium,thunder-8890-mdio"; DT compatible string "cavium,thunder-8890-mdio" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 297: compatible = "cavium,thunder-8890-mdio"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 297: compatible = "cavium,thunder-8890-mdio"; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 300: reg = <0x87e0 0x05003880 0x0 0x30>; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 305: compatible = "cavium,thunder-8890-mmc"; DT compatible string "cavium,thunder-8890-mmc" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 305: compatible = "cavium,thunder-8890-mmc"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 306: reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 315: compatible = "cavium,thunder-8890-twsi"; DT compatible string "cavium,thunder-8890-twsi" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 315: compatible = "cavium,thunder-8890-twsi"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 316: reg = <0x4800 0 0 0 0>; /* DEVFN = 0x48 (9:0) */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 325: compatible = "cavium,thunder-8890-twsi"; DT compatible string "cavium,thunder-8890-twsi" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 325: compatible = "cavium,thunder-8890-twsi"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 326: reg = <0x4900 0 0 0 0>; /* DEVFN = 0x49 (9:1) */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 335: compatible = "cavium,thunder-8890-bgx"; DT compatible string "cavium,thunder-8890-bgx" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 335: compatible = "cavium,thunder-8890-bgx"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 336: reg = <0x9000 0 0 0 0>; /* DEVFN = 0x90 (16:1) */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 341: compatible = "cavium,thunder-8890-bgx"; DT compatible string "cavium,thunder-8890-bgx" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 341: compatible = "cavium,thunder-8890-bgx"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 342: reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 347: compatible = "cavium,thunder-8890-bgx"; DT compatible string "cavium,thunder-8890-bgx" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 347: compatible = "cavium,thunder-8890-bgx"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 348: reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 353: compatible = "cavium,thunder-8190-spi"; DT compatible string "cavium,thunder-8190-spi" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 353: compatible = "cavium,thunder-8190-spi"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 354: reg = <0x3800 0x0 0x0 0x0 0x0>; /* DEVFN = 0x38 (7:0) */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 362: compatible = "cavium,thunder-8890-gpio"; DT compatible string "cavium,thunder-8890-gpio" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 362: compatible = "cavium,thunder-8890-gpio"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 364: reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 371: compatible = "cavium,cn8130-nand"; DT compatible string "cavium,cn8130-nand" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 371: compatible = "cavium,cn8130-nand"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 392: compatible = "cavium,pci-host-thunder-pem"; DT compatible string "cavium,pci-host-thunder-pem" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 392: compatible = "cavium,pci-host-thunder-pem"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 401: reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 402: <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 403: ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 404: <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 405: <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 406: <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 417: compatible = "cavium,pci-host-thunder-pem"; DT compatible string "cavium,pci-host-thunder-pem" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 417: compatible = "cavium,pci-host-thunder-pem"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 426: reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 427: <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 428: ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 429: <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 430: <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 431: <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 442: compatible = "cavium,pci-host-thunder-pem"; DT compatible string "cavium,pci-host-thunder-pem" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 442: compatible = "cavium,pci-host-thunder-pem"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 451: reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 452: <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 453: ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 454: <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 455: <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 456: <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 469: compatible = "cavium,thunder-8190-tdm"; DT compatible string "cavium,thunder-8190-tdm" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 469: compatible = "cavium,thunder-8190-tdm"; DT compatible string vendor "cavium" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… File src/mainboard/opencellular/satima/death.c: https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 31: } while(1); space required before the open parenthesis '(' https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… File src/mainboard/opencellular/satima/mainboard.h: https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 18: #define SATIMA_GPIO_SPI_MUX 24 please, no space before tabs https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… File src/mainboard/opencellular/satima/sff8104-linux.dts: https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 53: compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; DT compatible string "marvell,88e1510" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 53: compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; DT compatible string vendor "marvell" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 53: compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; DT compatible string "ethernet-phy-ieee802.3-c22" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 53: compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 59: compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; DT compatible string "vitesse,vsc8574" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 59: compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; DT compatible string vendor "vitesse" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 59: compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; DT compatible string "ethernet-phy-ieee802.3-c22" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 59: compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 66: compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; DT compatible string "aquantia,aqr105" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 66: compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; DT compatible string vendor "aquantia" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 66: compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; DT compatible string "ethernet-phy-ieee802.3-c45" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 66: compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 98: compatible = "mmc-slot"; DT compatible string "mmc-slot" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 108: /* There is no card detection available; polling must be used. */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 117: compatible = "mmc-slot"; DT compatible string "mmc-slot" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 128: /* There is no card detection available; polling must be used. */ line over 80 characters https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string "micron,n25q128a13" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string vendor "micron" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string "spi-flash" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string "jedec,spi-nor" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 142: compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; DT compatible string vendor "jedec" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 149: compatible = "spinand,mt29f", "mt29f"; DT compatible string "spinand,mt29f" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 149: compatible = "spinand,mt29f", "mt29f"; DT compatible string vendor "spinand" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/vendor-prefixes.txt https://review.coreboot.org/#/c/27425/12/src/mainboard/opencellular/satima/… PS12, Line 149: compatible = "spinand,mt29f", "mt29f"; DT compatible string "mt29f" appears un-documented -- check util/lint/checkpatch.pl/Documentation/devicetree/bindings/ -- To view, visit https://review.coreboot.org/27425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4f972d59ac2243823a77f614c4f92c1666185705 Gerrit-Change-Number: 27425 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Jul 2018 10:24:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: Documentation/writing_docs: Document the need for recommonmark
by Arthur Heymans (Code Review) 25 Jul '18

25 Jul '18

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/27631 ) Change subject: Documentation/writing_docs: Document the need for recommonmark ...................................................................... Documentation/writing_docs: Document the need for recommonmark python-recommonmark is need for sphinx to be able to hande the markdown documentation. Change-Id: I9513ab4bdc753e0350754d9869239ea833893af9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/getting_started/writing_documentation.md 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27631/2 -- To view, visit https://review.coreboot.org/27631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9513ab4bdc753e0350754d9869239ea833893af9 Gerrit-Change-Number: 27631 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: Documentation/writing_docs: Also document the need for recommonmark
by Arthur Heymans (Code Review) 25 Jul '18

25 Jul '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27631 Change subject: Documentation/writing_docs: Also document the need for recommonmark ...................................................................... Documentation/writing_docs: Also document the need for recommonmark python-recommonmark is need for sphinx to be able to hande the markdown documentation. Change-Id: I9513ab4bdc753e0350754d9869239ea833893af9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/getting_started/writing_documentation.md 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27631/1 diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index 9a9bbf0..027def9 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -16,7 +16,9 @@ ### Install Sphinx -Please follow this official [guide]. +Please follow this official [guide] to install sphinx. +You will also need python-recommonmark for sphinx to be able to handle +markdown documenation. ### Optional -- To view, visit https://review.coreboot.org/27631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9513ab4bdc753e0350754d9869239ea833893af9 Gerrit-Change-Number: 27631 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: asrock/g41c-gs: make serial console setup depend on selected super IO
by Felix Held (Code Review) 25 Jul '18

25 Jul '18

Hello Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27629 to look at the new patch set (#2). Change subject: asrock/g41c-gs: make serial console setup depend on selected super IO ...................................................................... asrock/g41c-gs: make serial console setup depend on selected super IO The used super IO is selected in Kconfig depending on the board variant, so use the selected super IO instead of the board variant directly. Change-Id: I8421e7c9b1f9ca875c9291f4105c3c20726adfd0 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/asrock/g41c-gs/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/27629/2 -- To view, visit https://review.coreboot.org/27629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8421e7c9b1f9ca875c9291f4105c3c20726adfd0 Gerrit-Change-Number: 27629 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: asrock/g41c-gs: make serial console setup depend on selected super IO
by Arthur Heymans (Code Review) 25 Jul '18

25 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27629 ) Change subject: asrock/g41c-gs: make serial console setup depend on selected super IO ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8421e7c9b1f9ca875c9291f4105c3c20726adfd0 Gerrit-Change-Number: 27629 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 25 Jul 2018 09:47:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documenation/conf.py: Make sure release is a string
by Arthur Heymans (Code Review) 25 Jul '18

25 Jul '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27630 Change subject: Documenation/conf.py: Make sure release is a string ...................................................................... Documenation/conf.py: Make sure release is a string With python3 the split method can operate on strings while check_output generates bytestrings. Change-Id: I7b455c56e8195f0ecfbe5e360ac161c176f00115 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/conf.py 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/27630/1 diff --git a/Documentation/conf.py b/Documentation/conf.py index b8415c6..ff1ad9d 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -20,7 +20,7 @@ # built documents. # # The full version, including alpha/beta/rc tags. -release = subprocess.check_output(('git', 'describe')) +release = subprocess.check_output(('git', 'describe')).decode("utf-8") # The short X.Y version. version = release.split("-")[0] -- To view, visit https://review.coreboot.org/27630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7b455c56e8195f0ecfbe5e360ac161c176f00115 Gerrit-Change-Number: 27630 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: asrock/g41c-gs: make serial console setup depend on selected super IO
by Felix Held (Code Review) 25 Jul '18

25 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27629 Change subject: asrock/g41c-gs: make serial console setup depend on selected super IO ...................................................................... asrock/g41c-gs: make serial console setup depend on selected super IO The used super IO is selected in Kconfig depending on the board variant, so use the selected super IO instead of the board variant directly. Change-Id: I8421e7c9b1f9ca875c9291f4105c3c20726adfd0 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/asrock/g41c-gs/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/27629/1 diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index e1f4152..7a30e35 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -47,7 +47,7 @@ setup_pch_gpios(&mainboard_gpio_map); /* Set GPIOs on superio, enable UART */ - if (IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)) { + if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) { nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); pnp_set_logical_device(SERIAL_DEV_R2); -- To view, visit https://review.coreboot.org/27629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8421e7c9b1f9ca875c9291f4105c3c20726adfd0 Gerrit-Change-Number: 27629 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Add new board
by Lijian Zhao (Code Review) 25 Jul '18

25 Jul '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/27628 Change subject: mainboard/intel/coffeelake_rvp: Add new board ...................................................................... mainboard/intel/coffeelake_rvp: Add new board Add new mainboard variant of whiskey lake rvp. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskeylake rvp platform. Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c A src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h 6 files changed, 191 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27628/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 5bd7531..0af1723 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU +if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP config BOARD_SPECIFIC_OPTIONS def_bool y @@ -23,11 +23,13 @@ string default "cfl_u" if BOARD_INTEL_COFFEELAKE_RVPU default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11 + default "whl_w" if BOARD_INTEL_WHISKEYLAKE_RVP config MAINBOARD_PART_NUMBER string default "Coffeelake U RVP" if BOARD_INTEL_COFFEELAKE_RVPU default "Coffeelake H RVP11" if BOARD_INTEL_COFFEELAKE_RVP11 + default "Whiskeylake RVP" if BOARD_INTEL_WHISKEYLAKE_RVP config MAINBOARD_VENDOR string diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 0dc7079..9bf3ac8 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -2,3 +2,5 @@ bool "Coffeelake U LPDDR4 RVP" config BOARD_INTEL_COFFEELAKE_RVP11 bool "Coffeelake H LPDDR4 RVP11" +config BOARD_INTEL_WHISKEYLAKE_RVP + bool "Whiskeylake DDR4 RVP" diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index e0699da..9fddc8b 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -27,7 +27,6 @@ { FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - u8 spd_index; mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); @@ -36,10 +35,17 @@ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - spd_index = 2; +#if !IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU) + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */ + + /* TODO: Hard coding SpdAddress */ + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; +#else + u8 spd_index = 2; struct region_device spd_rdev; @@ -49,6 +55,7 @@ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); /* Memory leak is ok since we have memory mapped boot media */ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); - mem_cfg->RefClk = 0; /* Auto Select CLK freq */ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; +#endif + mem_cfg->SafeMode = 0; } diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c index c6f9511..48575ab 100644 --- a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c @@ -31,11 +31,18 @@ void mainboard_fill_dq_map_ch1(void *dq_map_ptr) { - const u8 dq_map[12] = { + const u8 dq_map_u[12] = { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + const u8 dq_map_h[12] = { + 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)) + memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u)); + else + memcpy(dq_map_ptr, dq_map_h, sizeof(dq_map_h)); } void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) @@ -43,12 +50,12 @@ /* DQS CPU<>DRAM map Ch0 */ const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 }; - const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; + const u8 dqs_map_h[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)) memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h)); } void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) @@ -56,12 +63,12 @@ /* DQS CPU<>DRAM map Ch1 */ const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 }; - const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; + const u8 dqs_map_h[8] = { 1, 0, 4, 5, 3, 2, 6, 7 }; if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)) memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h)); } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb new file mode 100644 index 0000000..62a6635 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb @@ -0,0 +1,139 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "3" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "1" + register "HeciEnabled" = "1" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on end # CNVi wifi + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h new file mode 100644 index 0000000..4b6f579 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/27628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Gerrit-Change-Number: 27628 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: nb/amd/pi/00730F01: Add initial native IVRS support
by build bot (Jenkins) (Code Review) 25 Jul '18

25 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/15164 ) Change subject: nb/amd/pi/00730F01: Add initial native IVRS support ...................................................................... Patch Set 21: (4 comments) https://review.coreboot.org/#/c/15164/21/src/northbridge/amd/pi/00730F01/no… File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/#/c/15164/21/src/northbridge/amd/pi/00730F01/no… PS21, Line 507: is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); line over 80 characters https://review.coreboot.org/#/c/15164/21/src/northbridge/amd/pi/00730F01/no… PS21, Line 528: } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && line over 80 characters https://review.coreboot.org/#/c/15164/21/src/northbridge/amd/pi/00730F01/no… PS21, Line 608: printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); line over 80 characters https://review.coreboot.org/#/c/15164/21/src/northbridge/amd/pi/00730F01/no… PS21, Line 609: printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); line over 80 characters -- To view, visit https://review.coreboot.org/15164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Gerrit-Change-Number: 15164 Gerrit-PatchSet: 21 Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 24 Jul 2018 23:55:07 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/amd/pi/00730F01: Add initial native IVRS support
by build bot (Jenkins) (Code Review) 25 Jul '18

25 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/15164 ) Change subject: nb/amd/pi/00730F01: Add initial native IVRS support ...................................................................... Patch Set 20: (7 comments) https://review.coreboot.org/#/c/15164/20/src/northbridge/amd/pi/00730F01/no… File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/#/c/15164/20/src/northbridge/amd/pi/00730F01/no… PS20, Line 507: is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); line over 80 characters https://review.coreboot.org/#/c/15164/20/src/northbridge/amd/pi/00730F01/no… PS20, Line 528: } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && line over 80 characters https://review.coreboot.org/#/c/15164/20/src/northbridge/amd/pi/00730F01/no… PS20, Line 608: printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); line over 80 characters https://review.coreboot.org/#/c/15164/20/src/northbridge/amd/pi/00730F01/no… PS20, Line 609: printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); line over 80 characters https://review.coreboot.org/#/c/15164/20/src/northbridge/amd/pi/00730F01/no… PS20, Line 624: ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ line over 80 characters https://review.coreboot.org/#/c/15164/20/src/northbridge/amd/pi/00730F01/no… PS20, Line 626: ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ line over 80 characters https://review.coreboot.org/#/c/15164/20/src/northbridge/amd/pi/00730F01/no… PS20, Line 627: ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ line over 80 characters -- To view, visit https://review.coreboot.org/15164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Gerrit-Change-Number: 15164 Gerrit-PatchSet: 20 Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 24 Jul 2018 23:49:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit July 2018