coreboot-gerrit July 2018

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Change in coreboot[master]: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA
by build bot (Jenkins) (Code Review) 25 Jul '18

25 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27602 ) Change subject: nb/amd/pi/00730F01: use MMIO and performance counters from AGESA ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/27602/5/src/northbridge/amd/pi/00730F01/nor… File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/#/c/27602/5/src/northbridge/amd/pi/00730F01/nor… PS5, Line 640: ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info & 0x7fe000; line over 80 characters -- To view, visit https://review.coreboot.org/27602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d Gerrit-Change-Number: 27602 Gerrit-PatchSet: 5 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 24 Jul 2018 23:17:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/amd/pi/00730F01: Add initial native IVRS support
by build bot (Jenkins) (Code Review) 25 Jul '18

25 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/15164 ) Change subject: nb/amd/pi/00730F01: Add initial native IVRS support ...................................................................... Patch Set 19: (12 comments) https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 459: if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) line over 80 characters https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 506: is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); line over 80 characters https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 527: } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && line over 80 characters https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 527: } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && that open brace { should be on the previous line https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 556: for (sibling = link->children; sibling; sibling = sibling->sibling) line over 80 characters https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 557: add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); line over 80 characters https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 562: unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 599: static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 605: printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate G-series northbridge device! IVRS table not generated...\n"); Prefer using '"%s...", __func__' to using 'acpi_fill_ivrs', this function's name, in a string https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 619: ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ line over 80 characters https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 621: ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ line over 80 characters https://review.coreboot.org/#/c/15164/19/src/northbridge/amd/pi/00730F01/no… PS19, Line 622: ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ line over 80 characters -- To view, visit https://review.coreboot.org/15164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Gerrit-Change-Number: 15164 Gerrit-PatchSet: 19 Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 24 Jul 2018 23:16:46 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Add header file: psp.h, and modify code in psp.c to use internal func...
by Martin Roth (Code Review) 24 Jul '18

24 Jul '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/27619 ) Change subject: Add header file: psp.h, and modify code in psp.c to use internal functions rather than functions from PspBaseLib. ...................................................................... Patch Set 1: (18 comments) Lots of style comments. Welcome to coreboot. :) https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.h File src/soc/amd/common/block/psp/psp.h: https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.h@4 PS1, Line 4: 2017 Is this a new file, or copied from somewhere else? https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.h@… PS1, Line 34: G change to spaces to match the rest of the file? https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.h@… PS1, Line 35: Extra newline at the end. This is what's causing the jenkins failure. https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c File src/soc/amd/common/block/psp/psp.c: https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 12: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the You probably didn't mean to make this change https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 27: extra line https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 37: static BOOLEAN psp_bar_init_early(VOID); We don't generally have function definitions for static functions. https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 38: extra line https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 46: BOOLEAN We don't really use BOOLEAN in coreboot. It's only used in vendorcode https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 49: PspMmioSize; No camelcase unless it's needed for interfacing with vendorcode please. https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 61: // For multi-line comments, please use a style like this: /* * Comment */ https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 96: 0x34); Does this need to be split to a separate line? https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 110: /** : Return the PspMMIO MMIO location : : @param[in] PspMmio Pointer to Psp MMIO address : : @retval BOOLEAN 0: Error, 1 Success : **/ Same issue with the comment style, with the additional * for doxygen: /** * * */ https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 117: static BOOLEAN : get_psp_bar3_addr( : IN OUT u32 *PspMmio : ) Single line? We don't typically use BOOLEAN, or IN & OUT in coreboot code: static int get_psp_bar3_addr(u32 psp_mmio_addr) { https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 134: BIT12 You mention updating the magic numbers in a todo, but just changing this to a BAR3_HIDE #define would eliminate the need for the above comment. https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 140: __func__ We probably don't need to print out __func__ all over the place. I'd just print the message and leave that off. Generally you can find the correct function if you just search for the error message, and it makes the log a lot cleaner if you leave them out. https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 148: BIOS_DEBUG You might want to look at what you're printing vs what's really useful. Just printing the address of the PSP isn't really going to be useful most of the time, so you might want to change this to BIOS_SPEW. On the other hand, when we fail above, that might be better as a BIOS_WARNING. https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 187: , base=0x%x...\ Here and above, do we care what base is if the function failed? https://review.coreboot.org/#/c/27619/1/src/soc/amd/common/block/psp/psp.c@… PS1, Line 287: You might want to make sure your editor isn't configured to change this for some reason. -- To view, visit https://review.coreboot.org/27619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a Gerrit-Change-Number: 27619 Gerrit-PatchSet: 1 Gerrit-Owner: Charles Marslett <charles.marslett(a)amd.corp-partner.google.com> Gerrit-Reviewer: Charles Marslett <charles.marslett(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 24 Jul 2018 21:09:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: google/caroline: Add missing audio codec info
by Matt DeVillier (Code Review) 24 Jul '18

24 Jul '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27626 Change subject: google/caroline: Add missing audio codec info ...................................................................... google/caroline: Add missing audio codec info Add audio codec definitions in devicetree, which were accidentally dropped when upstreaming Test: build/boot Caroline with GalliumOS 3.0a2, verify working audio. Change-Id: I707b93c83f773cde2108b75ec550a15e5566d974 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/glados/variants/caroline/devicetree.cb 1 file changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/27626/1 diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 9ada5c5..a040714 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -226,7 +226,41 @@ device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on end # I2C #4 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" # R389 + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1c" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "uid" = "0" + device i2c 34 on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "uid" = "1" + device i2c 35 on end + end + end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" -- To view, visit https://review.coreboot.org/27626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I707b93c83f773cde2108b75ec550a15e5566d974 Gerrit-Change-Number: 27626 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge/northbridge.c: Enable eDP HIGH_VDIFF
by Richard Spiegel (Code Review) 24 Jul '18

24 Jul '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27625 Change subject: soc/amd/stoneyridge/northbridge.c: Enable eDP HIGH_VDIFF ...................................................................... soc/amd/stoneyridge/northbridge.c: Enable eDP HIGH_VDIFF The careena board needs different video setting to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display setted eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27625/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 6af1351..71fcf58 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -484,6 +484,7 @@ void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) { params->IommuSupport = FALSE; + params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE; } void SetNbMidParams(GNB_MID_CONFIGURATION *params) -- To view, visit https://review.coreboot.org/27625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95 Gerrit-Change-Number: 27625 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: google/caroline: ACPI fixes
by Matt DeVillier (Code Review) 24 Jul '18

24 Jul '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27624 Change subject: google/caroline: ACPI fixes ...................................................................... google/caroline: ACPI fixes - remove duplicate FMCN package for I2C2, since already generated by devicetree-linked driver - add audio codec definitions in devicetree, which were accidentally dropped when upstreaming Test: build/boot Caroline with GalliumOS 3.0a2, verify touchpad, touchscreen, and audio all functioning properly, no ACPI errors in dmesg. Change-Id: I68315daf087aef0fc51411605b054e6322d5d7f8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl 2 files changed, 35 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/27624/1 diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 9ada5c5..a040714 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -226,7 +226,41 @@ device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 - device pci 19.2 on end # I2C #4 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "0" # R389 + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x0c" + register "sar_threshold[1]" = "0x1c" + register "sar_threshold[2]" = "0x38" + register "sar_threshold[3]" = "0x60" + register "sar_hysteresis" = "1" + register "sar_voltage" = "0" # VDDA + register "sar_compare_time" = "0" # 500ns + register "sar_sampling_time" = "0" # 2us + register "short_key_debounce" = "2" # 100ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "7" # 512ms + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "uid" = "0" + device i2c 34 on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "uid" = "1" + device i2c 35 on end + end + end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl index 19c8834..d0324cf 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/glados/variants/caroline/include/variant/acpi/mainboard.asl @@ -66,8 +66,6 @@ Scope (\_SB.PCI0.I2C2) { - Name (FMCN, Package () { 87, 197, 26 }) - Device (DIGI) { Name (_HID, "ACPI0C50") -- To view, visit https://review.coreboot.org/27624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I68315daf087aef0fc51411605b054e6322d5d7f8 Gerrit-Change-Number: 27624 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x
by build bot (Jenkins) (Code Review) 24 Jul '18

24 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27585 ) Change subject: cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/27585/3/src/cpu/intel/smm/gen1/smmrelocate.c File src/cpu/intel/smm/gen1/smmrelocate.c: https://review.coreboot.org/#/c/27585/3/src/cpu/intel/smm/gen1/smmrelocate.… PS3, Line 78: && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { code indent should use tabs where possible https://review.coreboot.org/#/c/27585/3/src/cpu/intel/smm/gen1/smmrelocate.… PS3, Line 78: && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { please, no space before tabs -- To view, visit https://review.coreboot.org/27585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9 Gerrit-Change-Number: 27585 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 24 Jul 2018 17:12:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x
by build bot (Jenkins) (Code Review) 24 Jul '18

24 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27585 ) Change subject: cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/27585/2/src/cpu/intel/smm/gen1/smmrelocate.c File src/cpu/intel/smm/gen1/smmrelocate.c: https://review.coreboot.org/#/c/27585/2/src/cpu/intel/smm/gen1/smmrelocate.… PS2, Line 78: && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { code indent should use tabs where possible https://review.coreboot.org/#/c/27585/2/src/cpu/intel/smm/gen1/smmrelocate.… PS2, Line 78: && (msr.lo & FEATURE_CONTROL_LOCK_BIT))) { please, no space before tabs https://review.coreboot.org/#/c/27585/2/src/cpu/intel/smm/gen1/smmrelocate.… PS2, Line 164: /* for model_6fx and model_1067x byte [0:11] on smrr_base are reserved */ line over 80 characters https://review.coreboot.org/#/c/27585/2/src/cpu/intel/smm/gen1/smmrelocate.… PS2, Line 169: params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; line over 80 characters -- To view, visit https://review.coreboot.org/27585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9 Gerrit-Change-Number: 27585 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 24 Jul 2018 17:07:36 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.5
by John Zhao (Code Review) 24 Jul '18

24 Jul '18

John Zhao has uploaded this change for review. ( https://review.coreboot.org/27623 Change subject: vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.5 ...................................................................... vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.5 Update FSP header files to match FSP Reference Code Release v2.0.5 for Geminilake BUG=b:111683980 CQ-DEPEND=CL:*653835 Change-Id: Ib5ac532843fdb30ac3269fb6ed96dd05ef5736cc Signed-off-by: zhaojohn <john.zhao(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/27623/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index 1cbcb69..cc194b2 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -173,13 +173,13 @@ Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). $EN_DIS **/ - UINT8 IpuEn; + UINT8 IpuEnReserved; /** Offset 0x003A - IMGU ACPI mode selection 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. 0:Disable, 1:IGFX Child device, 2:ACPI device **/ - UINT8 IpuAcpiMode; + UINT8 IpuAcpiModeReserved; /** Offset 0x003B - Enable ForceWake Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. @@ -279,7 +279,7 @@ Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. $EN_DIS **/ - UINT8 SaIpuEnable; + UINT8 SaIpuEnableReserved; /** Offset 0x0052 - GT PM Support Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). -- To view, visit https://review.coreboot.org/27623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib5ac532843fdb30ac3269fb6ed96dd05ef5736cc Gerrit-Change-Number: 27623 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com>

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Change in coreboot[master]: chromeec: Sync ec_commands.h with CrOS upstream.
by Jonathan Brandmeyer (Code Review) 24 Jul '18

24 Jul '18

Jonathan Brandmeyer has posted comments on this change. ( https://review.coreboot.org/27620 ) Change subject: chromeec: Sync ec_commands.h with CrOS upstream. ...................................................................... Patch Set 1: PTAL. Note that this is currently marked WIP pending one last upstream change. -- To view, visit https://review.coreboot.org/27620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic3daa09ffd83c089b6874e0ea9aab8aa60016775 Gerrit-Change-Number: 27620 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Brandmeyer <jbrandmeyer(a)chromium.org> Gerrit-Reviewer: Jonathan Brandmeyer <jbrandmeyer(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 24 Jul 2018 16:30:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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