coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

1 participants
877 discussions

Change in coreboot[master]: mb/pcengines/apu2: change GPIO setting
by build bot (Jenkins) (Code Review) 30 Jul '18

30 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27665 ) Change subject: mb/pcengines/apu2: change GPIO setting ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/27665/6/src/mainboard/pcengines/apu2/romsta… File src/mainboard/pcengines/apu2/romstage.c: https://review.coreboot.org/#/c/27665/6/src/mainboard/pcengines/apu2/romsta… PS6, Line 116: if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Gerrit-Change-Number: 27665 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kamran javed <kamrangulhaji315a(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Jul 2018 10:52:41 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/pcengines/apu2: correct LED setting
by Michał Żygowski (Code Review) 30 Jul '18

30 Jul '18

Michał Żygowski has uploaded a new patch set (#2). ( https://review.coreboot.org/27729 ) Change subject: mb/pcengines/apu2: correct LED setting ...................................................................... mb/pcengines/apu2: correct LED setting Due to vendor's requirements LED 2 and LED 3 should be turned off in late boot process. Add appropriate functions to read and write GPIO status. Change-Id: Ia286ef7d02cfcefacf0e8d358847406efe1496fb Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/gpio_ftns.h M src/mainboard/pcengines/apu2/mainboard.c 3 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/27729/2 -- To view, visit https://review.coreboot.org/27729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia286ef7d02cfcefacf0e8d358847406efe1496fb Gerrit-Change-Number: 27729 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

1 0

Change in coreboot[master]: mb/pcengines/apu2: correct LED setting
by Michał Żygowski (Code Review) 30 Jul '18

30 Jul '18

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/27729 Change subject: mb/pcengines/apu2: correct LED setting ...................................................................... mb/pcengines/apu2: correct LED setting Due to vendor's requirements LED 2 and LED 3 should be turned off in late boot process. Add appropriate functions to read and write GPIO status. Change-Id: Ia286ef7d02cfcefacf0e8d358847406efe1496fb Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/gpio_ftns.h M src/mainboard/pcengines/apu2/mainboard.c 3 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/27729/1 diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index b14d8a4..9a4a9ff 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -41,6 +41,18 @@ *iomuxptr = iomux_ftn & 0x3; } +u8 read_gpio(u32 gpio) +{ + u32 *memptr = (u32 *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio); + return (*memptr & GPIO_PIN_STS) ? 1 : 0; +} + +void write_gpio(u32 gpio, u8 value) +{ + u32 *memptr = (u32 *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio); + *memptr |= (value > 0) ? GPIO_OUTPUT_VALUE : 0; +} + int get_spd_offset(void) { u8 index = 0; diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 05f5414..24d6a7f 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -17,6 +17,8 @@ #define GPIO_FTNS_H void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting); +u8 read_gpio(u32 gpio); +void write_gpio(u32 gpio, u8 value); int get_spd_offset(void); #define IOMUX_OFFSET 0xD00 diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 8f2d622..9434b93 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -178,6 +178,15 @@ pirq_setup(); } +static void mainboard_final(void *chip_info) +{ + // + // Turn off LED 2 and LED 3 + // + write_gpio(GPIO_58, 1); + write_gpio(GPIO_59, 1); +} + /* * We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address * into the smbios serial number location. @@ -228,4 +237,5 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .final = mainboard_final, }; -- To view, visit https://review.coreboot.org/27729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia286ef7d02cfcefacf0e8d358847406efe1496fb Gerrit-Change-Number: 27729 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

1 0

Change in coreboot[master]: mainboard/opencellular/rotundu: Add FMAP support
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/25084 ) Change subject: mainboard/opencellular/rotundu: Add FMAP support ...................................................................... mainboard/opencellular/rotundu: Add FMAP support * Add 8M and 16M fmap configurations. * Fix kconfig selects. * Add vboot options and fixes Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Signed-off-by: zaolin <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/25084 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/opencellular/rotundu/Kconfig A src/mainboard/opencellular/rotundu/vboot-16M.fmd A src/mainboard/opencellular/rotundu/vboot-8M.fmd 3 files changed, 84 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig index a062a7a..edacf0d 100644 --- a/src/mainboard/opencellular/rotundu/Kconfig +++ b/src/mainboard/opencellular/rotundu/Kconfig @@ -18,7 +18,7 @@ config BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU def_bool n select SOC_INTEL_FSP_BAYTRAIL - select BOARD_ROMSIZE_KB_16384 + select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select ENABLE_BUILTIN_COM1 @@ -32,6 +32,21 @@ if BOARD_OPENCELLULAR_BASEBOARD_ROTUNDU +config VBOOT + select MRC_CACHE_FMAP + select VBOOT_VBNV_CMOS + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config GBB_HWID + string + depends on VBOOT + default "ROTUNDU" if BOARD_OPENCELLULAR_ROTUNDU + default "SUPABRCKV1" if BOARD_OPENCELLULAR_SUPABRCKV1 + config VARIANT_DIR string default "rotundu" if BOARD_OPENCELLULAR_ROTUNDU @@ -67,11 +82,16 @@ hex default 0xfffb0000 -# FIXME: Slow boot performance when increasing CBFS_SIZE beyond 8MB? +config FMDFILE + string + depends on VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-8M.fmd" if BOARD_ROMSIZE_KB_8192 + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-16M.fmd" if BOARD_ROMSIZE_KB_16384 + config CBFS_SIZE hex - default 0x00200000 if BOARD_ROMSIZE_KB_8192 - default 0x00800000 + default 0x00140000 if BOARD_ROMSIZE_KB_8192 + default 0x003effc0 if BOARD_ROMSIZE_KB_16384 config VIRTUAL_ROM_SIZE hex diff --git a/src/mainboard/opencellular/rotundu/vboot-16M.fmd b/src/mainboard/opencellular/rotundu/vboot-16M.fmd new file mode 100644 index 0000000..ec078e5 --- /dev/null +++ b/src/mainboard/opencellular/rotundu/vboot-16M.fmd @@ -0,0 +1,30 @@ +FLASH 16M { + SI_ALL@0x0 0x300000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2ff000 + } + SI_BIOS@0x300000 0xd00000 { + RW_SECTION_B@0x0 0x400000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3effc0 + RW_FWID_B@0x3fffc0 0x40 + } + RW_SECTION_A@0x400000 0x400000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3effc0 + RW_FWID_A@0x3fffc0 0x40 + } + RW_MRC_CACHE@0x800000 0x10000 + RW_VPD@0x810000 0x2000 + WP_RO@0x812000 0x4ee000 { + RO_VPD@0x0 0x4000 + RO_SECTION@0x4000 0x4ea000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x3fa000 + } + } + } +} diff --git a/src/mainboard/opencellular/rotundu/vboot-8M.fmd b/src/mainboard/opencellular/rotundu/vboot-8M.fmd new file mode 100644 index 0000000..623f86a --- /dev/null +++ b/src/mainboard/opencellular/rotundu/vboot-8M.fmd @@ -0,0 +1,30 @@ +FLASH 8M { + SI_ALL@0x0 0x300000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2ff000 + } + SI_BIOS@0x300000 0x500000 { + RW_SECTION_B@0x0 0x150040 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x140000 + RW_FWID_B@0x150000 0x40 + } + RW_SECTION_A@0x150040 0x150040 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x140000 + RW_FWID_A@0x150000 0x40 + } + RW_MRC_CACHE@0x2a0080 0x10000 + RW_VPD@0x2b0080 0x2000 + WP_RO@0x2b2080 0x24df80 { + RO_VPD@0x0 0x4000 + RO_SECTION@0x4000 0x249f80 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x159f80 + } + } + } +} -- To view, visit https://review.coreboot.org/25084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I49d97a9d324207e45520d43b814b03a20005122a Gerrit-Change-Number: 25084 Gerrit-PatchSet: 15 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mb/pcengines/apu2: change GPIO setting
by build bot (Jenkins) (Code Review) 30 Jul '18

30 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27665 ) Change subject: mb/pcengines/apu2: change GPIO setting ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/27665/5/src/mainboard/pcengines/apu2/romsta… File src/mainboard/pcengines/apu2/romstage.c: https://review.coreboot.org/#/c/27665/5/src/mainboard/pcengines/apu2/romsta… PS5, Line 116: if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Gerrit-Change-Number: 27665 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kamran javed <kamrangulhaji315a(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Jul 2018 10:20:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/pcengines/apu2: change GPIO setting
by build bot (Jenkins) (Code Review) 30 Jul '18

30 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27665 ) Change subject: mb/pcengines/apu2: change GPIO setting ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/27665/4/src/mainboard/pcengines/apu2/romsta… File src/mainboard/pcengines/apu2/romstage.c: https://review.coreboot.org/#/c/27665/4/src/mainboard/pcengines/apu2/romsta… PS4, Line 116: if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Gerrit-Change-Number: 27665 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kamran javed <kamrangulhaji315a(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Jul 2018 09:54:36 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/pcengines/apu2: change GPIO setting
by build bot (Jenkins) (Code Review) 30 Jul '18

30 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27665 ) Change subject: mb/pcengines/apu2: change GPIO setting ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/27665/3/src/mainboard/pcengines/apu2/romsta… File src/mainboard/pcengines/apu2/romstage.c: https://review.coreboot.org/#/c/27665/3/src/mainboard/pcengines/apu2/romsta… PS3, Line 116: if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/27665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 Gerrit-Change-Number: 27665 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: kamran javed <kamrangulhaji315a(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 30 Jul 2018 09:33:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/intel/fsp_baytrail: Add VBOOT support
by Patrick Rudolph (Code Review) 30 Jul '18

30 Jul '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/27728 ) Change subject: soc/intel/fsp_baytrail: Add VBOOT support ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/#/c/27728/3/src/soc/intel/fsp_baytrail/pmutil.c File src/soc/intel/fsp_baytrail/pmutil.c: https://review.coreboot.org/#/c/27728/3/src/soc/intel/fsp_baytrail/pmutil.c… PS3, Line 29: static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); pci_devfn_t https://review.coreboot.org/#/c/27728/3/src/soc/intel/fsp_baytrail/pmutil.c… PS3, Line 31: static inline device_t get_pcu_dev(void) pci_devfn_t https://review.coreboot.org/#/c/27728/3/src/soc/intel/fsp_baytrail/pmutil.c… PS3, Line 36: #else /* !__SMM__ */ /* !__SIMPLE_DEVICE__ */ -- To view, visit https://review.coreboot.org/27728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Gerrit-Change-Number: 27728 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 30 Jul 2018 07:10:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: security/vboot: Enable TCPA log extension
by Patrick Rudolph (Code Review) 30 Jul '18

30 Jul '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/27727 ) Change subject: security/vboot: Enable TCPA log extension ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/27727/2/src/security/tpm/tspi/tspi.c File src/security/tpm/tspi/tspi.c: https://review.coreboot.org/#/c/27727/2/src/security/tpm/tspi/tspi.c@181 PS2, Line 181: uint32_t tpm_extend_pcr(const char *name, int pcr, uint8_t *digest, i'd prefer "const char *name" to be the last argument, as it's only required for logging. https://review.coreboot.org/#/c/27727/2/src/security/tpm/tspi/tspi.c@195 PS2, Line 195: printk(BIOS_ERR, "ERROR: Couldn't creat TCPA log entry\n"); create https://review.coreboot.org/#/c/27727/2/src/security/vboot/secdata_tpm.c File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/#/c/27727/2/src/security/vboot/secdata_tpm.c@83 PS2, Line 83: return tpm_extend_pcr("GBB flags", pcr, buffer, size); do you want to use defines for the TCPA log entries in a public header ? -- To view, visit https://review.coreboot.org/27727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f Gerrit-Change-Number: 27727 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 30 Jul 2018 07:04:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: security/tpm: Fix TCPA log commit
by Patrick Rudolph (Code Review) 30 Jul '18

30 Jul '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/27726 ) Change subject: security/tpm: Fix TCPA log commit ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/27726/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27726/3//COMMIT_MSG@9 PS3, Line 9: * TCPA log overwrites newly generated log add commit hash and subject https://review.coreboot.org/#/c/27726/3/src/commonlib/include/commonlib/cbm… File src/commonlib/include/commonlib/cbmem_id.h: https://review.coreboot.org/#/c/27726/3/src/commonlib/include/commonlib/cbm… PS3, Line 67: #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 missing tab -- To view, visit https://review.coreboot.org/27726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Gerrit-Change-Number: 27726 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 30 Jul 2018 06:59:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

← Newer
1
...
4
5
6
7
8
9
10
...
88
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2018