coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: payload/LinuxBoot: Fix compilation
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/27745 Change subject: payload/LinuxBoot: Fix compilation ...................................................................... payload/LinuxBoot: Fix compilation * Update kernel version * Add kernel directory removal during clean target * Add x86 and x86_64 default configs Change-Id: I6793bffd2c537a0e9fe7c07abbea99b28defb52e Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Makefile A payloads/external/LinuxBoot/x86/defconfig A payloads/external/LinuxBoot/x86_64/defconfig 4 files changed, 329 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27745/1 diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 24d44cf..14ee895 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -53,10 +53,17 @@ bool "4.15.3" help Stable kernel version + +config LINUXBOOT_KERNEL_LATEST + bool "4.17.11" + help + Latest kernel version + endchoice config LINUXBOOT_KERNEL_VERSION string + default "4.17.11" if LINUXBOOT_KERNEL_LATEST default "4.15.3" if LINUXBOOT_KERNEL_STABLE config LINUXBOOT_KERNEL_CONFIGFILE diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 651e982..f259373 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -21,23 +21,23 @@ XGCCPATH?=$(PWD)/util/crossgcc/xgcc/bin ifeq ($(CONFIG_LINUXBOOT_ARCH),386) -CROSS_COMPILE?=$(XGCCPATH)/i386-linux- +LINUXBOOT_COMPILE?=$(XGCCPATH)/i386-linux- ARCH?=x86 else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64) -CROSS_COMPILE?=$(XGCCPATH)/x86_64-linux- +LINUXBOOT_COMPILE?=$(XGCCPATH)/x86_64-linux- ARCH?=x86_64 else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64) -CROSS_COMPILE?=$(XGCCPATH)/aarch64-linux- +LINUXBOOT_COMPILE?=$(XGCCPATH)/aarch64-linux- ARCH?=arm64 endif -OBJCOPY:=$(CROSS_COMPILE)objcopy +OBJCOPY:=$(LINUXBOOT_COMPILE)objcopy all: payload toolchain: - if [[ ! -x "$(CROSS_COMPILE)gcc" ]]; then \ - echo "Toolchain '$(CROSS_COMPILE)*' is missing."; \ + if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \ + echo "Toolchain '$(LINUXBOOT_COMPILE)*' is missing."; \ exit 1; \ fi @@ -67,8 +67,8 @@ $(kernel_dir)/vmlinux: config toolchain endif echo " MAKE Kernel $(CONFIG_LINUXBOOT_KERNEL_VERSION)" - $(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH) - $(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH) + $(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH) + $(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH) ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64)) $(project_dir)/kernel-image: $(kernel_dir)/arch/x86/boot/bzImage @@ -99,7 +99,7 @@ payload: $(project_dir)/kernel-image $(project_dir)/initramfs.cpio.xz clean: - if [ -d "$(kernel_dir)" ]; then make -C $(kernel_dir) clean; fi + if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi rm -f $(project_dir)/initramfs.cpio.xz distclean: diff --git a/payloads/external/LinuxBoot/x86/defconfig b/payloads/external/LinuxBoot/x86/defconfig new file mode 100644 index 0000000..6c20c14 --- /dev/null +++ b/payloads/external/LinuxBoot/x86/defconfig @@ -0,0 +1,147 @@ +# CONFIG_64BIT is not set +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_XZ=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_USELIB is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_MULTIUSER is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_BUG is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_BASE_FULL is not set +# CONFIG_AIO is not set +# CONFIG_KALLSYMS is not set +CONFIG_BPF_SYSCALL=y +CONFIG_USERFAULTFD=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_GCC_PLUGINS=y +CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y +CONFIG_GCC_PLUGIN_STRUCTLEAK=y +CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y +CONFIG_GCC_PLUGIN_RANDSTRUCT=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_MMAP_RND_BITS=16 +CONFIG_REFCOUNT_FULL=y +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_ZONE_DMA is not set +# CONFIG_X86_FAST_FEATURE_TESTS is not set +# CONFIG_X86_MPPARSE is not set +# CONFIG_X86_EXTENDED_PLATFORM is not set +# CONFIG_SCHED_OMIT_FRAME_POINTER is not set +# CONFIG_DMI is not set +CONFIG_PREEMPT=y +# CONFIG_X86_MCE is not set +# CONFIG_MICROCODE is not set +CONFIG_SPARSEMEM_MANUAL=y +# CONFIG_COMPACTION is not set +# CONFIG_MTRR is not set +# CONFIG_X86_INTEL_UMIP is not set +CONFIG_KEXEC=y +# CONFIG_RELOCATABLE is not set +# CONFIG_MODIFY_LDT_SYSCALL is not set +# CONFIG_SUSPEND is not set +CONFIG_PM=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_ACPI_REV_OVERRIDE_POSSIBLE is not set +# CONFIG_ACPI_AC is not set +# CONFIG_ACPI_BATTERY is not set +# CONFIG_ACPI_BUTTON is not set +# CONFIG_ACPI_FAN is not set +# CONFIG_ACPI_PROCESSOR is not set +# CONFIG_ACPI_TABLE_UPGRADE is not set +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y +# CONFIG_CPU_IDLE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEASPM_POWER_SUPERSAVE=y +CONFIG_PCI_MSI=y +# CONFIG_BINFMT_SCRIPT is not set +# CONFIG_COREDUMP is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_PNP_DEBUG_MESSAGES is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_HW_RANDOM_TIMERIOMEM=y +# CONFIG_HW_RANDOM_AMD is not set +# CONFIG_HW_RANDOM_VIA is not set +# CONFIG_DEVPORT is not set +CONFIG_I2C=y +CONFIG_POWER_SUPPLY=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +# CONFIG_USB_SUPPORT is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_GOOGLE_FIRMWARE=y +CONFIG_GOOGLE_COREBOOT_TABLE_ACPI=y +CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y +CONFIG_GOOGLE_VPD=y +CONFIG_EXT4_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_TMPFS=y +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_ZLIB is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_NETWORK_FILESYSTEMS is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y +# CONFIG_X86_VERBOSE_BOOTUP is not set +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DOUBLEFAULT is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_X86_DEBUG_FPU is not set +CONFIG_UNWINDER_GUESS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_HW is not set +# CONFIG_VIRTUALIZATION is not set diff --git a/payloads/external/LinuxBoot/x86_64/defconfig b/payloads/external/LinuxBoot/x86_64/defconfig new file mode 100644 index 0000000..71c5d77 --- /dev/null +++ b/payloads/external/LinuxBoot/x86_64/defconfig @@ -0,0 +1,166 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_XZ=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_MULTIUSER is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_BUG is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_BASE_FULL is not set +# CONFIG_AIO is not set +# CONFIG_KALLSYMS is not set +CONFIG_BPF_SYSCALL=y +CONFIG_USERFAULTFD=y +CONFIG_EMBEDDED=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLOB=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_GCC_PLUGINS=y +CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y +CONFIG_GCC_PLUGIN_STRUCTLEAK=y +CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y +CONFIG_GCC_PLUGIN_RANDSTRUCT=y +# CONFIG_VMAP_STACK is not set +CONFIG_REFCOUNT_FULL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_ZONE_DMA is not set +# CONFIG_X86_MPPARSE is not set +# CONFIG_X86_EXTENDED_PLATFORM is not set +CONFIG_IOSF_MBI=y +# CONFIG_SCHED_OMIT_FRAME_POINTER is not set +# CONFIG_DMI is not set +CONFIG_PREEMPT=y +# CONFIG_X86_MCE is not set +# CONFIG_MICROCODE is not set +CONFIG_X86_MSR=y +CONFIG_X86_CPUID=y +# CONFIG_SPARSEMEM_VMEMMAP is not set +# CONFIG_COMPACTION is not set +# CONFIG_MTRR is not set +# CONFIG_X86_INTEL_UMIP is not set +# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set +CONFIG_KEXEC=y +# CONFIG_RELOCATABLE is not set +# CONFIG_MODIFY_LDT_SYSCALL is not set +# CONFIG_SUSPEND is not set +# CONFIG_ACPI_REV_OVERRIDE_POSSIBLE is not set +# CONFIG_ACPI_AC is not set +# CONFIG_ACPI_BATTERY is not set +CONFIG_ACPI_VIDEO=y +# CONFIG_ACPI_FAN is not set +# CONFIG_ACPI_PROCESSOR is not set +# CONFIG_ACPI_TABLE_UPGRADE is not set +# CONFIG_X86_PM_TIMER is not set +# CONFIG_CPU_IDLE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEASPM_POWER_SUPERSAVE=y +CONFIG_PCI_MSI=y +# CONFIG_ISA_DMA_API is not set +# CONFIG_BINFMT_SCRIPT is not set +# CONFIG_COREDUMP is not set +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FW_LOADER is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_PNP_DEBUG_MESSAGES is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_HW_RANDOM_TIMERIOMEM=y +# CONFIG_HW_RANDOM_AMD is not set +# CONFIG_HW_RANDOM_VIA is not set +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS=y +# CONFIG_DEVPORT is not set +CONFIG_I2C=y +CONFIG_POWER_SUPPLY=y +# CONFIG_HWMON is not set +# CONFIG_VGA_ARB is not set +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_FOREIGN_ENDIAN=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_USB_SUPPORT is not set +CONFIG_SYNC_FILE=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_GOOGLE_FIRMWARE=y +CONFIG_GOOGLE_COREBOOT_TABLE_ACPI=y +CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y +CONFIG_GOOGLE_VPD=y +CONFIG_EXT4_FS=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY_USER is not set +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +# CONFIG_X86_VERBOSE_BOOTUP is not set +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DOUBLEFAULT is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_X86_DEBUG_FPU is not set +CONFIG_UNWINDER_GUESS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_CRYPTO_ECHAINIV is not set +CONFIG_CRYPTO_SHA256_SSSE3=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_HW is not set +# CONFIG_VIRTUALIZATION is not set -- To view, visit https://review.coreboot.org/27745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6793bffd2c537a0e9fe7c07abbea99b28defb52e Gerrit-Change-Number: 27745 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: soc/amd/stoneyridge/lpc.c: Fix LPC host control
by Richard Spiegel (Code Review) 30 Jul '18

30 Jul '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27744 Change subject: soc/amd/stoneyridge/lpc.c: Fix LPC host control ...................................................................... soc/amd/stoneyridge/lpc.c: Fix LPC host control 2 bits of LPC host control were originally not public, and wrongly identified as IMC related. Now that the bits are available in public BKDG, fix the naming of the bits. BUG=b:111912080 TEST=build and boot grunt. Change-Id: I1921f46c6be54eda6329c98267cec27004caadd5 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/lpc.c 2 files changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/27744/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index ece78b6..15c9581 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -213,8 +213,8 @@ #define SPI_FROM_USB_PREFETCH_EN BIT(23) #define LPC_HOST_CONTROL 0xbb -#define IMC_PAGE_FROM_HOST_EN BIT(0) -#define IMC_PORT_FROM_HOST_EN BIT(3) +#define PREFETCH_EN_SPI_FROM_HOST BIT(0) +#define T_START_ENH BIT(3) /* SPI Controller */ #define SPI_CNTRL0 0x00 diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 4bf5a4f..6833db6 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -76,12 +76,11 @@ pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); /* - * IMC is not used, but some of its registers and ports need to be - * programmed/accessed. So enable CPU access to them. This fixes - * SPI_CS# timing issue when running at 66MHz. + * Enable hand-instance of the pulse generator and SPI + * controller prefetch of flash. */ byte = pci_read_config8(dev, LPC_HOST_CONTROL); - byte |= IMC_PAGE_FROM_HOST_EN | IMC_PORT_FROM_HOST_EN; + byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; pci_write_config8(dev, LPC_HOST_CONTROL, byte); cmos_check_update_date(); -- To view, visit https://review.coreboot.org/27744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1921f46c6be54eda6329c98267cec27004caadd5 Gerrit-Change-Number: 27744 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: mb/google/parrot/smihandler: Use new PMBASE API
by Patrick Georgi (Code Review) 30 Jul '18

30 Jul '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27679 ) Change subject: mb/google/parrot/smihandler: Use new PMBASE API ...................................................................... mb/google/parrot/smihandler: Use new PMBASE API Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/27679 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/parrot/smihandler.c 1 file changed, 3 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 7681065..e30f78f 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -20,6 +20,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/pmutil.h> +#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> #include <elog.h> @@ -29,7 +30,6 @@ static u8 mainboard_smi_ec(void) { u8 src; - u32 pm1_cnt; #if IS_ENABLED(CONFIG_ELOG_GSMI) static int battery_critical_logged; #endif @@ -54,9 +54,7 @@ elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ - pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); break; } @@ -65,8 +63,6 @@ void mainboard_smi_gpi(u32 gpi_sts) { - u32 pm1_cnt; - printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts); if (gpi_sts & (1 << EC_SMI_GPI)) { /* Process all pending events from EC */ @@ -79,9 +75,7 @@ elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED); #endif /* Go to S5 */ - pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10)); } } -- To view, visit https://review.coreboot.org/27679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e Gerrit-Change-Number: 27679 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: drivers/i2c/da7219: Allow disabling micbias-pulse feature
by Patrick Georgi (Code Review) 30 Jul '18

30 Jul '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27613 ) Change subject: drivers/i2c/da7219: Allow disabling micbias-pulse feature ...................................................................... drivers/i2c/da7219: Allow disabling micbias-pulse feature These two da7219_aad properties are optional: - dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV). [<2800>, <2900>] - dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms) When the Mic Bias Higher Voltage feature is not required, firmware should just not provide the dlg,micbias-pulse-lvl and dlg,micbias-pulse-time properties. Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> BUG=b:111700809 TEST=On grunt: No "Invalid micbias pulse level" in dmesg Change-Id: Ie99a8962e78c68b3f6927d0de34168f265d4efa9 Reviewed-on: https://review.coreboot.org/27613 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Akshu Agrawal <akshu.agrawal(a)amd.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/i2c/da7219/da7219.c 1 file changed, 6 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Akshu Agrawal: Looks good to me, but someone else must approve diff --git a/src/drivers/i2c/da7219/da7219.c b/src/drivers/i2c/da7219/da7219.c index b8af689..43e6076 100644 --- a/src/drivers/i2c/da7219/da7219.c +++ b/src/drivers/i2c/da7219/da7219.c @@ -77,10 +77,12 @@ acpi_dp_add_integer(aad, "dlg,c-mic-btn-thr", config->c_mic_btn_thr); acpi_dp_add_integer(aad, "dlg,btn-avg", config->btn_avg); acpi_dp_add_integer(aad, "dlg,adc-1bit-rpt", config->adc_1bit_rpt); - acpi_dp_add_integer(aad, "dlg,micbias-pulse-lvl", - config->micbias_pulse_lvl); - acpi_dp_add_integer(aad, "dlg,micbias-pulse-time", - config->micbias_pulse_time); + if (config->micbias_pulse_lvl > 0) { + acpi_dp_add_integer(aad, "dlg,micbias-pulse-lvl", + config->micbias_pulse_lvl); + acpi_dp_add_integer(aad, "dlg,micbias-pulse-time", + config->micbias_pulse_time); + } /* DA7219 Properties */ dsd = acpi_dp_new_table("_DSD"); -- To view, visit https://review.coreboot.org/27613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ie99a8962e78c68b3f6927d0de34168f265d4efa9 Gerrit-Change-Number: 27613 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sandybridge/raminit_common: use FOR_ALL_CHANNELS macro
by Felix Held (Code Review) 30 Jul '18

30 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27733 Change subject: sandybridge/raminit_common: use FOR_ALL_CHANNELS macro ...................................................................... sandybridge/raminit_common: use FOR_ALL_CHANNELS macro Change-Id: I01bd69605760e8a03787dcfa3da9f47576e3144a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/27733/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6639fd9..4de83fb 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3083,8 +3083,8 @@ MCHBAR32(0x4cd4) = 0x00000046; - MCHBAR32_AND_OR(0x400c, 0xFFFFCFFF, 0x1000); - MCHBAR32_AND_OR(0x440c, 0xFFFFCFFF, 0x1000); + FOR_ALL_CHANNELS + MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xFFFFCFFF, 0x1000); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3093,8 +3093,9 @@ /* APD - PPD, 64 DCLKs until idle, decision per rank */ MCHBAR32(PM_PDWN_Config) = 0x00000340; - MCHBAR32(0x4380) = 0x00000aaa; // OK - MCHBAR32(0x4780) = 0x00000aaa; // OK + FOR_ALL_CHANNELS + MCHBAR32(0x4380 + 0x400 * channel) = 0x00000aaa; + MCHBAR32(0x4f88) = 0x5f7003ff; // OK MCHBAR32(0x5064) = 0x00073000 | ctrl->reg_5064b0; // OK @@ -3120,8 +3121,9 @@ MCHBAR32(0x5880) = 0xca9171e5; MCHBAR32_AND_OR(0x5888, ~0xffffff, 0xe4d5d0); MCHBAR32_AND(0x58a8, ~0x1f); - MCHBAR32_AND_OR(0x4294, ~0x30000, 1 << 16); - MCHBAR32_AND_OR(0x4694, ~0x30000, 1 << 16); + + FOR_ALL_CHANNELS + MCHBAR32_AND_OR(0x4294 + 0x400 * channel, ~0x30000, 1 << 16); MCHBAR32(0x5030) |= 1; MCHBAR32(0x5030) |= 0x80; -- To view, visit https://review.coreboot.org/27733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I01bd69605760e8a03787dcfa3da9f47576e3144a Gerrit-Change-Number: 27733 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: security/tpm: Use unique CBMEM names for TCPA logs
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27726 ) Change subject: security/tpm: Use unique CBMEM names for TCPA logs ...................................................................... security/tpm: Use unique CBMEM names for TCPA logs Fix regression introduced in commit f18dc5c7 "Add TCPA logging functionality": Introduced TCPA log got overwritten in acpi.c of x86/arch, due to CBMEM name collision. Use a different cbmem name to have two independent TCPA logs. Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/27726 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/acpi.c M src/commonlib/include/commonlib/cbmem_id.h 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 60d2879..8d7579d 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -260,14 +260,14 @@ const struct cbmem_entry *ce; const u32 tcpa_default_log_len = 0x10000; void *lasa; - ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG); + ce = cbmem_entry_find(CBMEM_ID_TCPA_TCG_LOG); if (ce) { lasa = cbmem_entry_start(ce); *size = cbmem_entry_size(ce); printk(BIOS_DEBUG, "TCPA log found at %p\n", lasa); return lasa; } - lasa = cbmem_add(CBMEM_ID_TCPA_LOG, tcpa_default_log_len); + lasa = cbmem_add(CBMEM_ID_TCPA_TCG_LOG, tcpa_default_log_len); if (!lasa) { printk(BIOS_ERR, "TCPA log creation failed\n"); return NULL; diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index cc2fed1..287de1d 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -64,7 +64,7 @@ #define CBMEM_ID_STAGEx_RAW 0x57a9e200 #define CBMEM_ID_STORAGE_DATA 0x53746f72 #define CBMEM_ID_TCPA_LOG 0x54435041 -#define CBMEM_ID_TCPA_COMPLIANT_LOG 0x54445041 +#define CBMEM_ID_TCPA_TCG_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 @@ -121,7 +121,7 @@ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ { CBMEM_ID_STORAGE_DATA, "SD/MMC/eMMC" }, \ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ - { CBMEM_ID_TCPA_COMPLIANT_LOG, "TCPA COMPLIANT LOG " }, \ + { CBMEM_ID_TCPA_TCG_LOG, "TCPA TCGLOG" }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ -- To view, visit https://review.coreboot.org/27726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iac63ac26989080a401aac2273265a263a3fdec56 Gerrit-Change-Number: 27726 Gerrit-PatchSet: 8 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/vboot: Enable TCPA log extension
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27727 ) Change subject: security/vboot: Enable TCPA log extension ...................................................................... security/vboot: Enable TCPA log extension * Implement TCPA log for tspi extend function. * Hook tcpa_log_init into vboot tpm_setup function. * Add TCPA log output for vboot GBB flags and HWID Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/27727 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/security/tpm/tspi.h M src/security/tpm/tspi/tspi.c M src/security/vboot/secdata_tpm.c 3 files changed, 31 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 01b2984..43254c1 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -35,10 +35,12 @@ * Ask vboot for a digest and extend a TPM PCR with it. * @param pcr sets the pcr index * @param digest sets the hash to extend into the tpm - * @param out_digest get extended hash + * @param digest_len the length of the digest + * @param name sets additional info where the digest comes from * @return TPM_SUCCESS on success. If not a tpm error is returned */ -uint32_t tpm_extend_pcr(int pcr, uint8_t *digest, uint8_t *out_digest); +uint32_t tpm_extend_pcr(int pcr, uint8_t *digest, size_t digest_len, + const char *name); /** * Issue a TPM_Clear and reenable/reactivate the TPM. diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 407e1fa..48b6219 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -178,13 +178,21 @@ return TPM_SUCCESS; } -uint32_t tpm_extend_pcr(int pcr, uint8_t *digest, uint8_t *out_digest) +uint32_t tpm_extend_pcr(int pcr, uint8_t *digest, + size_t digest_len, const char *name) { + uint32_t result; + if (!digest) return TPM_E_IOERROR; - if (out_digest) - return tlcl_extend(pcr, digest, out_digest); + result = tlcl_extend(pcr, digest, NULL); + if (result != TPM_SUCCESS) + return result; - return tlcl_extend(pcr, digest, NULL); + result = tcpa_log_add_table_entry(name, pcr, digest, digest_len); + if (result != 0) + printk(BIOS_ERR, "ERROR: Couldn't create TCPA log entry\n"); + + return 0; } diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 57c107b..d3f4a11 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -61,11 +61,13 @@ } \ } while (0) +#define TPM_PCR_GBB_FLAGS_NAME "GBB flags" +#define TPM_PCR_GBB_HWID_NAME "GBB HWID" static uint32_t safe_write(uint32_t index, const void *data, uint32_t length); uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, - enum vb2_pcr_digest which_digest) + enum vb2_pcr_digest which_digest) { uint8_t buffer[VB2_PCR_DIGEST_RECOMMENDED_SIZE]; uint32_t size = sizeof(buffer); @@ -77,7 +79,15 @@ if (size < TPM_PCR_MINIMUM_DIGEST_SIZE) return VB2_ERROR_UNKNOWN; - return tpm_extend_pcr(pcr, buffer, NULL); + switch (which_digest) { + case BOOT_MODE_PCR: + return tpm_extend_pcr(pcr, buffer, size, + TPM_PCR_GBB_FLAGS_NAME); + case HWID_DIGEST_PCR: + return tpm_extend_pcr(pcr, buffer, size, TPM_PCR_GBB_HWID_NAME); + default: + return VB2_ERROR_UNKNOWN; + } } static uint32_t read_space_firmware(struct vb2_context *ctx) @@ -441,6 +451,9 @@ if (result == TPM_E_MUST_REBOOT) ctx->flags |= VB2_CONTEXT_SECDATA_WANTS_REBOOT; + // TCPA cbmem log + tcpa_log_init(); + return result; } -- To view, visit https://review.coreboot.org/27727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f Gerrit-Change-Number: 27727 Gerrit-PatchSet: 10 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/fsp_baytrail: Add VBOOT support
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27728 ) Change subject: soc/intel/fsp_baytrail: Add VBOOT support ...................................................................... soc/intel/fsp_baytrail: Add VBOOT support * Add vbnv_cmos_failed function to SoC. * Add VBOOT starts in romstage select. Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/27728 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_baytrail/pmutil.c 3 files changed, 27 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 1d7e64a..68084bc 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -47,6 +47,9 @@ # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + config SOC_INTEL_FSP_BAYTRAIL_MD bool default n diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index e01a944..0cf99de 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += ramstage.c ramstage-y += gpio.c romstage-y += gpio.c +romstage-y += pmutil.c ramstage-y += pmutil.c ramstage-y += southcluster.c romstage-y += reset.c diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index 33ecc09..402842e 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -15,14 +15,16 @@ #include <stdint.h> #include <arch/io.h> +#include <cbmem.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pmc.h> +#include <security/vboot/vbnv.h> -#if defined(__SMM__) +#if defined(__SIMPLE_DEVICE__) static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); @@ -31,7 +33,7 @@ return pcu_dev; } -#else /* !__SMM__ */ +#else /* !__SIMPLE_DEVICE__ */ #include <device/device.h> #include <device/pci.h> @@ -358,3 +360,22 @@ write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); } + +int vbnv_cmos_failed(void) +{ + uint32_t gen_pmcon1; + int rtc_fail; + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps != NULL) + gen_pmcon1 = ps->gen_pmcon1; + else + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + + rtc_fail = !!(gen_pmcon1 & RPS); + + if (rtc_fail) + printk(BIOS_DEBUG, "RTC failure.\n"); + + return rtc_fail; +} -- To view, visit https://review.coreboot.org/27728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Gerrit-Change-Number: 27728 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: northbridge/nehalem: add MCHBAR8/16 AND_OR macros
by Felix Held (Code Review) 30 Jul '18

30 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27732 Change subject: northbridge/nehalem: add MCHBAR8/16 AND_OR macros ...................................................................... northbridge/nehalem: add MCHBAR8/16 AND_OR macros Change-Id: I62e4a8610689e72944e1a9c020f13a47d402c136 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/nehalem/nehalem.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/27732/1 diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index bc49e96..5756c90 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -177,8 +177,12 @@ #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR8_AND_OR(x, and, or) \ + (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) +#define MCHBAR16_AND_OR(x, and, or) \ + (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) #define MCHBAR32_AND_OR(x, and, or) \ -- To view, visit https://review.coreboot.org/27732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I62e4a8610689e72944e1a9c020f13a47d402c136 Gerrit-Change-Number: 27732 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: security/vboot: Enable TCPA log extension
by Philipp Deppenwiese (Code Review) 30 Jul '18

30 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27727 ) Change subject: security/vboot: Enable TCPA log extension ...................................................................... Patch Set 4: done -- To view, visit https://review.coreboot.org/27727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I22b1aa8da1a95380c39715727615ce5ce4c9443f Gerrit-Change-Number: 27727 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 30 Jul 2018 12:53:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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