coreboot-gerrit July 2018

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Change in coreboot[master]: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void
by Furquan Shaikh (Code Review) 31 Jul '18

31 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27757 Change subject: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void ...................................................................... security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void Change f849972 (security/vboot: Enable TCPA log extension) enabled support for adding TCPA log to CBMEM. However, if CBMEM is not online, this function doesn't do anything and … [View More]returns early. This condition is not really a valid error condition as it depends on when the call to tcpa_log_add_table_entry is made. Since tcpa_log_add_table_entry returns -1 when cbmem is not online, tpm_extend_pcr prints an error message with prefix "ERROR:". This can confuse any scripts trying to catch errors in boot flow. This CL makes the following changes: 1. Removes the print in tpm_extend_pcr since tcpa_log_add_table_entry already prints out appropriate ERROR messages in case of failure to add log entry. 2. Since the return value of tcpa_log_add_table_entry is not used anymore, return type for tcpa_log_add_table_entry is changed to void. BUG=b:112030232 Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c 3 files changed, 10 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27757/1 diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 43254c1..94b53b0 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -28,8 +28,9 @@ /** * Add table entry for cbmem TCPA log. */ -int tcpa_log_add_table_entry(const char *name, const uint32_t pcr, - const uint8_t *digest, const size_t digest_length); +void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, + const uint8_t *digest, + const size_t digest_length); /** * Ask vboot for a digest and extend a TPM PCR with it. diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 6091dfe..8ec4c6d 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -44,24 +44,24 @@ printk(BIOS_DEBUG, "TCPA log created at %p\n", tclt); } -int tcpa_log_add_table_entry(const char *name, const uint32_t pcr, - const uint8_t *digest, const size_t digest_length) +void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, + const uint8_t *digest, const size_t digest_length) { MAYBE_STATIC struct tcpa_table *tclt = NULL; struct tcpa_entry *tce; if (!cbmem_possibly_online()) - return -1; + return; tclt = cbmem_find(CBMEM_ID_TCPA_LOG); if (!tclt) { printk(BIOS_ERR, "ERROR: No TCPA log table found\n"); - return -1; + return; } if (tclt->num_entries == tclt->max_entries) { printk(BIOS_WARNING, "ERROR: TCPA log table is full\n"); - return -1; + return; } tce = &tclt->entries[tclt->num_entries++]; @@ -70,6 +70,4 @@ tce->pcr = pcr; memcpy(tce->digest, digest, digest_length); tce->digest_length = digest_length; - - return 0; } diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 48b6219..950e930 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -190,9 +190,7 @@ if (result != TPM_SUCCESS) return result; - result = tcpa_log_add_table_entry(name, pcr, digest, digest_len); - if (result != 0) - printk(BIOS_ERR, "ERROR: Couldn't create TCPA log entry\n"); + tcpa_log_add_table_entry(name, pcr, digest, digest_len); - return 0; + return TPM_SUCCESS; } -- To view, visit https://review.coreboot.org/27757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Gerrit-Change-Number: 27757 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> [View Less]

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Change in coreboot[master]: soc/intel/cannonlake: Report Whiskey Lake info
by Lijian Zhao (Code Review) 31 Jul '18

31 Jul '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/27756 Change subject: soc/intel/cannonlake: Report Whiskey Lake info ...................................................................... soc/intel/cannonlake: Report Whiskey Lake info According to #574725, report Whiskey Lake CPUID, MCH device ID and graphics device ID in bootblock stage. BUG=N/A TEST=Build and boot up whiskey lake rvp platform and check serial log to see proper CPU/MCH/GFX/PCH got recognized.… [View More]

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Add new board
by Lijian Zhao (Code Review) 31 Jul '18

31 Jul '18

Hello Maulik V Vaghela, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27628 to look at the new patch set (#5). Change subject: mainboard/intel/coffeelake_rvp: Add new board ...................................................................... mainboard/intel/coffeelake_rvp: Add new board Add new mainboard variant of whiskey lake rvp. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskeylake rvp … [View More]

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Change in coreboot[master]: mb/google/octopus: Enable EC SW sync for all
by Justin TerAvest (Code Review) 31 Jul '18

31 Jul '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/27755 Change subject: mb/google/octopus: Enable EC SW sync for all ...................................................................... mb/google/octopus: Enable EC SW sync for all Since this works on Yorp and Bip, we should enable EC SW sync for all known boards so that it doesn't get forgotten. BUG=None TEST=None Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d Signed-off-by: Justin TerAvest <… [View More]

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Change in coreboot[master]: sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining places
by Felix Held (Code Review) 31 Jul '18

31 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27754 Change subject: sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining places ...................................................................... sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining places Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 … [View More]file changed, 21 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/27754/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2e5fe70..d806066 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -195,7 +195,7 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { struct cpuid_result cpures; - u32 reg, addr, cpu, stretch; + u32 cpu, stretch; stretch = ctrl->ref_card_offset[channel]; /* ODT stretch: Delay ODT signal by stretch value. @@ -205,19 +205,13 @@ if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { if (stretch == 2) stretch = 3; - addr = 0x400 * channel + 0x401c; - reg = MCHBAR32(addr) & 0xffffc3ff; - reg |= (stretch << 12); - reg |= (stretch << 10); - MCHBAR32(addr) = reg; + MCHBAR32_AND_OR(0x401c + 0x400 * channel, 0xffffc3ff, + (stretch << 12) | (stretch << 10)); printram("OTHP Workaround [%x] = %x\n", addr, reg); } else { // OTHP - addr = 0x400 * channel + 0x400c; - reg = MCHBAR32(addr) & 0xfff0ffff; - reg |= (stretch << 16); - reg |= (stretch << 18); - MCHBAR32(addr) = reg; + MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xfff0ffff, + (stretch << 16) | (stretch << 18)); printram("OTHP [%x] = %x\n", addr, reg); } } @@ -262,7 +256,7 @@ MCHBAR32(0x400 * channel + 0x4014) = 0; - MCHBAR32(addr) |= 0x00020000; + MCHBAR32_OR(addr, 0x00020000); dram_odt_stretch(ctrl, channel); @@ -280,7 +274,7 @@ printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); MCHBAR32(0x400 * channel + 0x4298) = reg; - MCHBAR32(0x400 * channel + 0x4294) |= 0xff; + MCHBAR32_OR(0x400 * channel + 0x4294, 0xff); // SRFTP reg = 0; @@ -656,7 +650,7 @@ void dram_jedecreset(ramctr_timing * ctrl) { - u32 reg, addr; + u32 reg; int channel; while (!(MCHBAR32(0x5084) & 0x10000)); @@ -672,37 +666,33 @@ MCHBAR32(0x5030) = reg; // Assert dimm reset signal - reg = MCHBAR32(0x5030); - reg &= ~0x2; - MCHBAR32(0x5030) = reg; + MCHBAR32_AND(0x5030, ~0x2); // Wait 200us udelay(200); // Deassert dimm reset signal - MCHBAR32(0x5030) |= 2; + MCHBAR32_OR(0x5030, 2); // Wait 500us udelay(500); // Enable DCLK - MCHBAR32(0x5030) |= 4; + MCHBAR32_OR(0x5030, 4); // XXX Wait 20ns udelay(1); FOR_ALL_CHANNELS { // Set valid rank CKE - reg = 0; - reg = (reg & ~0xf) | ctrl->rankmap[channel]; - addr = 0x400 * channel + 0x42a0; - MCHBAR32(addr) = reg; + reg = ctrl->rankmap[channel]; + MCHBAR32(0x42a0 + 0x400 * channel) = reg; // Wait 10ns for ranks to settle //udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); - MCHBAR32(addr) = reg; + MCHBAR32(0x42a0 + 0x400 * channel) = reg; // Write reset using a NOP write_reset(ctrl); @@ -862,7 +852,6 @@ void dram_mrscommands(ramctr_timing * ctrl) { u8 slotrank; - u32 reg, addr; int channel; FOR_ALL_POPULATED_CHANNELS { @@ -903,13 +892,10 @@ } // Refresh enable - MCHBAR32(0x5030) |= 8; + MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - addr = 0x400 * channel + 0x4020; - reg = MCHBAR32(addr); - reg &= ~0x200000; - MCHBAR32(addr) = reg; + MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x200000); wait_428c(channel); @@ -1478,9 +1464,7 @@ MCHBAR32(0x4230 + 0x400 * channel) = (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16); - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; /* DRAM command NOP */ @@ -1518,9 +1502,7 @@ MCHBAR32(0x4234 + 0x400 * channel) = (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4214 + 0x400 * channel) = 0x244; /* DRAM command RD */ @@ -1553,7 +1535,7 @@ /* DRAM command PREA */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; MCHBAR32(0x4210 + 0x400 * channel) = 0x240; // execute command queue @@ -1725,7 +1707,6 @@ MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000; MCHBAR32(0x421c + 0x400 * channel) = 0; @@ -2095,11 +2076,10 @@ MCHBAR32(0x4230 + 0x400 * channel) = ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | ctr | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; + /* DRAM command WR */ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; MCHBAR32(0x4234 + 0x400 * channel) = @@ -3059,7 +3039,7 @@ FOR_ALL_POPULATED_CHANNELS { // Always drive command bus - MCHBAR32(0x4004 + 0x400 * channel) |= 0x20000000; + MCHBAR32_OR(0x4004 + 0x400 * channel, 0x20000000); } udelay(1); @@ -3170,8 +3150,8 @@ FOR_ALL_CHANNELS MCHBAR32_AND_OR(0x4294 + 0x400 * channel, ~0x30000, 1 << 16); - MCHBAR32(0x5030) |= 1; - MCHBAR32(0x5030) |= 0x80; + MCHBAR32_OR(0x5030, 1); + MCHBAR32_OR(0x5030, 0x80); MCHBAR32(0x5f18) = 0xfa; /* Find a populated channel. */ -- To view, visit https://review.coreboot.org/27754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55 Gerrit-Change-Number: 27754 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> [View Less]

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Change in coreboot[master]: mb/google/octopus: Enable EC SW sync for fleex
by Justin TerAvest (Code Review) 31 Jul '18

31 Jul '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/27753 Change subject: mb/google/octopus: Enable EC SW sync for fleex ...................................................................... mb/google/octopus: Enable EC SW sync for fleex This never got enabled for fleex; we should enable this to make it easier to have updated EC firmware. With this commit, here's the relevant console messages: sync_one_ec: devidx=0 select_rw=4 update_ec: Updating RW(active)..… [View More]

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Change in coreboot[master]: [Do Not Merge] add i945G based mainboard
by build bot (Jenkins) (Code Review) 31 Jul '18

31 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25509 ) Change subject: [Do Not Merge] add i945G based mainboard ...................................................................... Patch Set 22: (17 comments) https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… File src/mainboard/nec/945g-m4/romstage.c: https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 140: [ 16.101663] snd_intel8x0 … [View More]

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Change in coreboot[master]: nb/i945: Fix sdram_rcomp_buffer_strength_and_slew for i945gc
by build bot (Jenkins) (Code Review) 31 Jul '18

31 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27590 ) Change subject: nb/i945: Fix sdram_rcomp_buffer_strength_and_slew for i945gc ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/27590/4/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/27590/4/src/northbridge/intel/i945/raminit.… PS4, Line 1048: int offset … [View More]

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Change in coreboot[master]: cpu/intel/speedstep/acpi.c: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 31 Jul '18

31 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep/acpi.c: Add Netburst CPUs ...................................................................... Patch Set 19: (6 comments) https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/acpi.c File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/acpi.c@92 PS19, Line 92: else else is not generally useful … [View More]

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Change in coreboot[master]: drivers/spi: Read Winbond's flash protection bits
by build bot (Jenkins) (Code Review) 31 Jul '18

31 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25082 ) Change subject: drivers/spi: Read Winbond's flash protection bits ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/#/c/25082/11/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25082/11/src/drivers/spi/winbond.c@80 PS11, Line 80: u8 : 5; space prohibited before that ':' (… [View More]

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coreboot-gerrit July 2018