coreboot-gerrit July 2018

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Change in coreboot[master]: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void
by Furquan Shaikh (Code Review) 31 Jul '18

31 Jul '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/27757 Change subject: security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void ...................................................................... security/tpm/tspi: Set return type of tcpa_log_add_table_entry as void Change f849972 (security/vboot: Enable TCPA log extension) enabled support for adding TCPA log to CBMEM. However, if CBMEM is not online, this function doesn't do anything and returns early. This condition is not really a valid error condition as it depends on when the call to tcpa_log_add_table_entry is made. Since tcpa_log_add_table_entry returns -1 when cbmem is not online, tpm_extend_pcr prints an error message with prefix "ERROR:". This can confuse any scripts trying to catch errors in boot flow. This CL makes the following changes: 1. Removes the print in tpm_extend_pcr since tcpa_log_add_table_entry already prints out appropriate ERROR messages in case of failure to add log entry. 2. Since the return value of tcpa_log_add_table_entry is not used anymore, return type for tcpa_log_add_table_entry is changed to void. BUG=b:112030232 Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/security/tpm/tspi.h M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c 3 files changed, 10 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27757/1 diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 43254c1..94b53b0 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -28,8 +28,9 @@ /** * Add table entry for cbmem TCPA log. */ -int tcpa_log_add_table_entry(const char *name, const uint32_t pcr, - const uint8_t *digest, const size_t digest_length); +void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, + const uint8_t *digest, + const size_t digest_length); /** * Ask vboot for a digest and extend a TPM PCR with it. diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 6091dfe..8ec4c6d 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -44,24 +44,24 @@ printk(BIOS_DEBUG, "TCPA log created at %p\n", tclt); } -int tcpa_log_add_table_entry(const char *name, const uint32_t pcr, - const uint8_t *digest, const size_t digest_length) +void tcpa_log_add_table_entry(const char *name, const uint32_t pcr, + const uint8_t *digest, const size_t digest_length) { MAYBE_STATIC struct tcpa_table *tclt = NULL; struct tcpa_entry *tce; if (!cbmem_possibly_online()) - return -1; + return; tclt = cbmem_find(CBMEM_ID_TCPA_LOG); if (!tclt) { printk(BIOS_ERR, "ERROR: No TCPA log table found\n"); - return -1; + return; } if (tclt->num_entries == tclt->max_entries) { printk(BIOS_WARNING, "ERROR: TCPA log table is full\n"); - return -1; + return; } tce = &tclt->entries[tclt->num_entries++]; @@ -70,6 +70,4 @@ tce->pcr = pcr; memcpy(tce->digest, digest, digest_length); tce->digest_length = digest_length; - - return 0; } diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 48b6219..950e930 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -190,9 +190,7 @@ if (result != TPM_SUCCESS) return result; - result = tcpa_log_add_table_entry(name, pcr, digest, digest_len); - if (result != 0) - printk(BIOS_ERR, "ERROR: Couldn't create TCPA log entry\n"); + tcpa_log_add_table_entry(name, pcr, digest, digest_len); - return 0; + return TPM_SUCCESS; } -- To view, visit https://review.coreboot.org/27757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I32d313609a3e57845e67059b3747b81b5c8adb2a Gerrit-Change-Number: 27757 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/cannonlake: Report Whiskey Lake info
by Lijian Zhao (Code Review) 31 Jul '18

31 Jul '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/27756 Change subject: soc/intel/cannonlake: Report Whiskey Lake info ...................................................................... soc/intel/cannonlake: Report Whiskey Lake info According to #574725, report Whiskey Lake CPUID, MCH device ID and graphics device ID in bootblock stage. BUG=N/A TEST=Build and boot up whiskey lake rvp platform and check serial log to see proper CPU/MCH/GFX/PCH got recognized. Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/report_platform.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/27756/1 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 9d967ce..5ba8e71 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -36,6 +36,7 @@ { CPUID_CANNONLAKE_B0, "Cannonlake B0" }, { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, { CPUID_CANNONLAKE_D0, "Cannonlake D0" }, + { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, }; static struct { @@ -44,6 +45,7 @@ } mch_table[] = { { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, + { PCI_DEVICE_ID_INTEL_WHL_ID_W, "Whiskeylake" }, }; static struct { @@ -67,6 +69,7 @@ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2, "Cannonlake ULT GT1.5" }, { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, + { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Cannonlake ULT GT1" }, }; static uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/27756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Gerrit-Change-Number: 27756 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mainboard/intel/coffeelake_rvp: Add new board
by Lijian Zhao (Code Review) 31 Jul '18

31 Jul '18

Hello Maulik V Vaghela, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27628 to look at the new patch set (#5). Change subject: mainboard/intel/coffeelake_rvp: Add new board ...................................................................... mainboard/intel/coffeelake_rvp: Add new board Add new mainboard variant of whiskey lake rvp. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskeylake rvp platform. Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c A src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h 6 files changed, 191 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27628/5 -- To view, visit https://review.coreboot.org/27628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Gerrit-Change-Number: 27628 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/octopus: Enable EC SW sync for all
by Justin TerAvest (Code Review) 31 Jul '18

31 Jul '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/27755 Change subject: mb/google/octopus: Enable EC SW sync for all ...................................................................... mb/google/octopus: Enable EC SW sync for all Since this works on Yorp and Bip, we should enable EC SW sync for all known boards so that it doesn't get forgotten. BUG=None TEST=None Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/Kconfig.name 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/27755/1 diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index cd39816..633a456 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -33,12 +33,10 @@ bool "-> Bobba" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_MEEP bool "-> Meep" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS -- To view, visit https://review.coreboot.org/27755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d Gerrit-Change-Number: 27755 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining places
by Felix Held (Code Review) 31 Jul '18

31 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27754 Change subject: sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining places ...................................................................... sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining places Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 21 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/27754/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2e5fe70..d806066 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -195,7 +195,7 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { struct cpuid_result cpures; - u32 reg, addr, cpu, stretch; + u32 cpu, stretch; stretch = ctrl->ref_card_offset[channel]; /* ODT stretch: Delay ODT signal by stretch value. @@ -205,19 +205,13 @@ if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { if (stretch == 2) stretch = 3; - addr = 0x400 * channel + 0x401c; - reg = MCHBAR32(addr) & 0xffffc3ff; - reg |= (stretch << 12); - reg |= (stretch << 10); - MCHBAR32(addr) = reg; + MCHBAR32_AND_OR(0x401c + 0x400 * channel, 0xffffc3ff, + (stretch << 12) | (stretch << 10)); printram("OTHP Workaround [%x] = %x\n", addr, reg); } else { // OTHP - addr = 0x400 * channel + 0x400c; - reg = MCHBAR32(addr) & 0xfff0ffff; - reg |= (stretch << 16); - reg |= (stretch << 18); - MCHBAR32(addr) = reg; + MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xfff0ffff, + (stretch << 16) | (stretch << 18)); printram("OTHP [%x] = %x\n", addr, reg); } } @@ -262,7 +256,7 @@ MCHBAR32(0x400 * channel + 0x4014) = 0; - MCHBAR32(addr) |= 0x00020000; + MCHBAR32_OR(addr, 0x00020000); dram_odt_stretch(ctrl, channel); @@ -280,7 +274,7 @@ printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); MCHBAR32(0x400 * channel + 0x4298) = reg; - MCHBAR32(0x400 * channel + 0x4294) |= 0xff; + MCHBAR32_OR(0x400 * channel + 0x4294, 0xff); // SRFTP reg = 0; @@ -656,7 +650,7 @@ void dram_jedecreset(ramctr_timing * ctrl) { - u32 reg, addr; + u32 reg; int channel; while (!(MCHBAR32(0x5084) & 0x10000)); @@ -672,37 +666,33 @@ MCHBAR32(0x5030) = reg; // Assert dimm reset signal - reg = MCHBAR32(0x5030); - reg &= ~0x2; - MCHBAR32(0x5030) = reg; + MCHBAR32_AND(0x5030, ~0x2); // Wait 200us udelay(200); // Deassert dimm reset signal - MCHBAR32(0x5030) |= 2; + MCHBAR32_OR(0x5030, 2); // Wait 500us udelay(500); // Enable DCLK - MCHBAR32(0x5030) |= 4; + MCHBAR32_OR(0x5030, 4); // XXX Wait 20ns udelay(1); FOR_ALL_CHANNELS { // Set valid rank CKE - reg = 0; - reg = (reg & ~0xf) | ctrl->rankmap[channel]; - addr = 0x400 * channel + 0x42a0; - MCHBAR32(addr) = reg; + reg = ctrl->rankmap[channel]; + MCHBAR32(0x42a0 + 0x400 * channel) = reg; // Wait 10ns for ranks to settle //udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); - MCHBAR32(addr) = reg; + MCHBAR32(0x42a0 + 0x400 * channel) = reg; // Write reset using a NOP write_reset(ctrl); @@ -862,7 +852,6 @@ void dram_mrscommands(ramctr_timing * ctrl) { u8 slotrank; - u32 reg, addr; int channel; FOR_ALL_POPULATED_CHANNELS { @@ -903,13 +892,10 @@ } // Refresh enable - MCHBAR32(0x5030) |= 8; + MCHBAR32_OR(0x5030, 8); FOR_ALL_POPULATED_CHANNELS { - addr = 0x400 * channel + 0x4020; - reg = MCHBAR32(addr); - reg &= ~0x200000; - MCHBAR32(addr) = reg; + MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x200000); wait_428c(channel); @@ -1478,9 +1464,7 @@ MCHBAR32(0x4230 + 0x400 * channel) = (max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | 4 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16); - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; /* DRAM command NOP */ @@ -1518,9 +1502,7 @@ MCHBAR32(0x4234 + 0x400 * channel) = (max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10) | 8 | (ctrl->CAS << 16); - MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000; - MCHBAR32(0x4214 + 0x400 * channel) = 0x244; /* DRAM command RD */ @@ -1553,7 +1535,7 @@ /* DRAM command PREA */ MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002; MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; + MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400; MCHBAR32(0x4210 + 0x400 * channel) = 0x240; // execute command queue @@ -1725,7 +1707,6 @@ MCHBAR32(0x422c + 0x400 * channel) = 0x1f000; MCHBAR32(0x423c + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(0x420c + 0x400 * channel) = (slotrank << 24) | 0x360000; MCHBAR32(0x421c + 0x400 * channel) = 0; @@ -2095,11 +2076,10 @@ MCHBAR32(0x4230 + 0x400 * channel) = ((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10) | 8 | (ctrl->tRCD << 16); - MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | ctr | 0x60000; - MCHBAR32(0x4210 + 0x400 * channel) = 0x244; + /* DRAM command WR */ MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201; MCHBAR32(0x4234 + 0x400 * channel) = @@ -3059,7 +3039,7 @@ FOR_ALL_POPULATED_CHANNELS { // Always drive command bus - MCHBAR32(0x4004 + 0x400 * channel) |= 0x20000000; + MCHBAR32_OR(0x4004 + 0x400 * channel, 0x20000000); } udelay(1); @@ -3170,8 +3150,8 @@ FOR_ALL_CHANNELS MCHBAR32_AND_OR(0x4294 + 0x400 * channel, ~0x30000, 1 << 16); - MCHBAR32(0x5030) |= 1; - MCHBAR32(0x5030) |= 0x80; + MCHBAR32_OR(0x5030, 1); + MCHBAR32_OR(0x5030, 0x80); MCHBAR32(0x5f18) = 0xfa; /* Find a populated channel. */ -- To view, visit https://review.coreboot.org/27754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55 Gerrit-Change-Number: 27754 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: mb/google/octopus: Enable EC SW sync for fleex
by Justin TerAvest (Code Review) 31 Jul '18

31 Jul '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/27753 Change subject: mb/google/octopus: Enable EC SW sync for fleex ...................................................................... mb/google/octopus: Enable EC SW sync for fleex This never got enabled for fleex; we should enable this to make it easier to have updated EC firmware. With this commit, here's the relevant console messages: sync_one_ec: devidx=0 select_rw=4 update_ec: Updating RW(active)... Trying to locate 'ecrw' in CBFS update_ec: image len = 137580 EFS: EC is verifying updated image... send_packet: CrosEC result code 1 EFS: EC doesn't support EFS_VERIFY command vboot_hash_image: No valid hash (status=0 size=0). Compute one... print_hash: RW(active) hash: 35ba735cf97dd990f6f7f0895264382aa20beb4e7ba57270b0a7b24686e26afd Trying to locate 'ecrw.hash' in CBFS sync_one_ec: jumping to EC-RW send_packet: CrosEC result code 12 EC returned from reboot after 27753us BUG=b:112038021 TEST=Successful boot after EC update via sync Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/octopus/Kconfig.name 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/27753/1 diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index cfe051c..862efbd 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -28,7 +28,6 @@ bool "-> Fleex" select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if CHROMEOS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS config BOARD_GOOGLE_BOBBA -- To view, visit https://review.coreboot.org/27753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135 Gerrit-Change-Number: 27753 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: [Do Not Merge] add i945G based mainboard
by build bot (Jenkins) (Code Review) 31 Jul '18

31 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25509 ) Change subject: [Do Not Merge] add i945G based mainboard ...................................................................... Patch Set 22: (17 comments) https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… File src/mainboard/nec/945g-m4/romstage.c: https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 140: [ 16.101663] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x2 line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 141: [ 16.101785] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x2 line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 142: [ 16.101859] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x36 line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 143: [ 16.101974] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x36 line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 144: [ 16.102086] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x36 line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 145: [ 16.102156] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x38 line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 146: [ 16.102250] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x38 line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 147: [ 16.103089] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x10 line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/romstage… PS22, Line 151: [ 11.645291] snd_intel8x0m: probe of 0000:00:1e.3 failed with error -13 line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/superio_… File src/mainboard/nec/945g-m4/superio_hwm.c: https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/superio_… PS22, Line 83: //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/superio_… PS22, Line 90: //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/superio_… PS22, Line 135: hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/superio_… PS22, Line 140: temperatures[cpufan_temperature].deg_fahrenheit); line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/superio_… PS22, Line 141: hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/superio_… PS22, Line 149: hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/superio_… PS22, Line 154: temperatures[sysfan_temperature].deg_fahrenheit); line over 80 characters https://review.coreboot.org/#/c/25509/22/src/mainboard/nec/945g-m4/superio_… PS22, Line 155: hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature line over 80 characters -- To view, visit https://review.coreboot.org/25509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3 Gerrit-Change-Number: 25509 Gerrit-PatchSet: 22 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 17:27:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/i945: Fix sdram_rcomp_buffer_strength_and_slew for i945gc
by build bot (Jenkins) (Code Review) 31 Jul '18

31 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27590 ) Change subject: nb/i945: Fix sdram_rcomp_buffer_strength_and_slew for i945gc ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/27590/4/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/27590/4/src/northbridge/intel/i945/raminit.… PS4, Line 1048: int offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; line over 80 characters -- To view, visit https://review.coreboot.org/27590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iff1705788fdffeacd94fe5e50507733ff7c0f96b Gerrit-Change-Number: 27590 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 17:27:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/speedstep/acpi.c: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 31 Jul '18

31 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep/acpi.c: Add Netburst CPUs ...................................................................... Patch Set 19: (6 comments) https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/acpi.c File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/acpi.c@92 PS19, Line 92: else else is not generally useful after a break or return https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/speedstep.c File src/cpu/intel/speedstep/speedstep.c: https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/speedstep.… PS19, Line 45: if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and line over 80 characters https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/speedstep.… PS19, Line 46: enabled bits */ line over 80 characters https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/speedstep.… PS19, Line 48: params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); line over 80 characters https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/speedstep.… PS19, Line 77: !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { line over 80 characters https://review.coreboot.org/#/c/22604/19/src/cpu/intel/speedstep/speedstep.… PS19, Line 79: params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); line over 80 characters -- To view, visit https://review.coreboot.org/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 19 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 17:26:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi: Read Winbond's flash protection bits
by build bot (Jenkins) (Code Review) 31 Jul '18

31 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25082 ) Change subject: drivers/spi: Read Winbond's flash protection bits ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/#/c/25082/11/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25082/11/src/drivers/spi/winbond.c@80 PS11, Line 80: u8 : 5; space prohibited before that ':' (ctx:WxW) https://review.coreboot.org/#/c/25082/11/src/drivers/spi/winbond.c@82 PS11, Line 82: u8 : 1; space prohibited before that ':' (ctx:WxW) -- To view, visit https://review.coreboot.org/25082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5 Gerrit-Change-Number: 25082 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Jul 2018 14:28:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit July 2018