Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/27326
Change subject: payloads/seabios: Update stable from 1.11.1 to 1.11.2
......................................................................
payloads/seabios: Update stable from 1.11.1 to 1.11.2
SeaBIOS 1.11.2 was tagged with the following changes:
```
f9626cc cbvga_set_mode: refine clear display logic
f88297a qemu: add qemu ramfb support
a2e4001 vgasrc: add allocate_pmm()
17b01f4 pmm: use tmp zone on oom
44b17d0 bochs_display_setup: return error on failure
4ba61fa cbvga_set_mode: disable clearmem in windows x86 emulator.
dd69189 cbvga_list_modes: don't list current mode twice
5f0e7c9 cbvga_setup_modes: use real mode number instead of 0x140
961f67c qemu: add bochs-display support
767365e cbvga: factor out cbvga_setup_modes()
7906460 optionrom: enable non-vga display devices
```
Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0
Signed-off-by: Martin Kepplinger <martink(a)posteo.de>
Tested-by: Martin Kepplinger <martink(a)posteo.de>
---
M payloads/external/SeaBIOS/Kconfig
M payloads/external/SeaBIOS/Makefile
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/27326/1
diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
index 63f91d6..52dc738 100644
--- a/payloads/external/SeaBIOS/Kconfig
+++ b/payloads/external/SeaBIOS/Kconfig
@@ -5,7 +5,7 @@
default SEABIOS_STABLE
config SEABIOS_STABLE
- bool "1.11.1"
+ bool "1.11.2"
help
Stable SeaBIOS version
config SEABIOS_MASTER
diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
index 7058a8d..4e2ecbd 100644
--- a/payloads/external/SeaBIOS/Makefile
+++ b/payloads/external/SeaBIOS/Makefile
@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=0551a4be2ce599fb60e478b4c15e06ab6587822c
+TAG-$(CONFIG_SEABIOS_STABLE)=f9626ccb91e771f990fbb2da92e427a399d7d918
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
project_git_repo=https://review.coreboot.org/seabios.git
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0
Gerrit-Change-Number: 27326
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de>
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27325
Change subject: soc/amd/stoneyridge/southbridge.c: Add USB to aoac_devs table
......................................................................
soc/amd/stoneyridge/southbridge.c: Add USB to aoac_devs table
Table aoac_devs is used to define control and status registers for devices
that can do D3/D0 transition (AOAC), so that there's a single delay while
all devices are being enabled simultaneously. USB host are being enabled
later, so that's an added delay when they are enabled. Adding USB to the
table should reduce post time by some milliseconds.
BUG=b:111056662
TEST=Build and boot grunt.
Change-Id: I8dc22b3d1e1662b9ef278b18338d31fe9424f227
Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
---
M src/soc/amd/stoneyridge/southbridge.c
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27325/1
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 18e6c6c..ff64d9c 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -47,7 +47,9 @@
{ FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 },
{ FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 },
{ FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 },
- { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 }
+ { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 },
+ { FCH_AOAC_D3_CONTROL_USB2, FCH_AOAC_D3_STATE_USB2 },
+ { FCH_AOAC_D3_CONTROL_USB3, FCH_AOAC_D3_STATE_USB3 }
};
static int is_sata_config(void)
--
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Gerrit-Branch: master
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Gerrit-Change-Id: I8dc22b3d1e1662b9ef278b18338d31fe9424f227
Gerrit-Change-Number: 27325
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>