coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/atlas: MIPI camera ASL files for Atlas
by Ping-chung Chen (Code Review) 04 Jul '18

04 Jul '18

Hello Rajmohan Mani, JasonX Z Chen, Andy Yeh, Hyungwoo Yang, Rizwan Qureshi, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27350 to look at the new patch set (#4). Change subject: mb/google/atlas: MIPI camera ASL files for Atlas ...................................................................... mb/google/atlas: MIPI camera ASL files for Atlas Atlas has one sensor, create a single endpoint to CIO2. create power resource for enabling/disabling camera. BUG=b:111141128 Branch=None TEST=Testing (WIP) on Atlas board Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl M src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h 7 files changed, 233 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27350/4 -- To view, visit https://review.coreboot.org/27350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Gerrit-Change-Number: 27350 Gerrit-PatchSet: 4 Gerrit-Owner: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: JasonX Z Chen <jasonx.z.chen(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/atlas: MIPI camera ASL files for Atlas
by Ping-chung Chen (Code Review) 04 Jul '18

04 Jul '18

Hello Rajmohan Mani, JasonX Z Chen, Andy Yeh, Hyungwoo Yang, Rizwan Qureshi, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27350 to look at the new patch set (#3). Change subject: mb/google/atlas: MIPI camera ASL files for Atlas ...................................................................... mb/google/atlas: MIPI camera ASL files for Atlas Atlas has one sensor, create a single endpoint to CIO2. create power resource for enabling/disabling camera. BUG=None Branch=None TEST=NA Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl M src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h 7 files changed, 233 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27350/3 -- To view, visit https://review.coreboot.org/27350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Gerrit-Change-Number: 27350 Gerrit-PatchSet: 3 Gerrit-Owner: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: JasonX Z Chen <jasonx.z.chen(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/atlas: MIPI camera ASL files for Atlas
by Ping-chung Chen (Code Review) 04 Jul '18

04 Jul '18

Hello Rajmohan Mani, JasonX Z Chen, Andy Yeh, Hyungwoo Yang, Rizwan Qureshi, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27350 to look at the new patch set (#2). Change subject: mb/google/atlas: MIPI camera ASL files for Atlas ...................................................................... mb/google/atlas: MIPI camera ASL files for Atlas Atlas has one sensor, create a single endpoint to CIO2. create power resource for enabling/disabling camera. BUG=None Branch=None TEST=NA Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl M src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h 7 files changed, 233 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27350/2 -- To view, visit https://review.coreboot.org/27350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Gerrit-Change-Number: 27350 Gerrit-PatchSet: 2 Gerrit-Owner: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: JasonX Z Chen <jasonx.z.chen(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: temporarily block multiple-threads
by Anonymous Coward (Code Review) 04 Jul '18

04 Jul '18

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27348 to look at the new patch set (#2). Change subject: riscv: temporarily block multiple-threads ...................................................................... riscv: temporarily block multiple-threads Sometime needs to temporarily block multiple-threads. So add this code. Change-Id: Iedf58db6cddd44cfc17f5dfb3a5ccc0e12a49536 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A src/arch/riscv/include/smp.h 1 file changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27348/2 -- To view, visit https://review.coreboot.org/27348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iedf58db6cddd44cfc17f5dfb3a5ccc0e12a49536 Gerrit-Change-Number: 27348 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward (1001664) Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [Atlas] MIPI camera ASL files for Atlas
by build bot (Jenkins) (Code Review) 04 Jul '18

04 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27350 ) Change subject: [Atlas] MIPI camera ASL files for Atlas ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27350/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl: https://review.coreboot.org/#/c/27350/1/src/mainboard/google/poppy/variants… PS1, Line 122: trailing whitespace -- To view, visit https://review.coreboot.org/27350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Gerrit-Change-Number: 27350 Gerrit-PatchSet: 1 Gerrit-Owner: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: JasonX Z Chen <jasonx.z.chen(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Jul 2018 07:41:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [Atlas] MIPI camera ASL files for Atlas
by Andy Yeh (Code Review) 04 Jul '18

04 Jul '18

Andy Yeh has posted comments on this change. ( https://review.coreboot.org/27350 ) Change subject: [Atlas] MIPI camera ASL files for Atlas ...................................................................... Patch Set 1: Code-Review-1 (3 comments) please also change comment per the original patch. https://review.coreboot.org/#/c/coreboot/+/25536/ and please open a ticket to track this CL. https://partnerissuetracker.corp.google.com/ https://review.coreboot.org/#/c/27350/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl: https://review.coreboot.org/#/c/27350/1/src/mainboard/google/poppy/variants… PS1, Line 115: Package() { 384000000, 96000000 } should be slower for imx208 as the current settings are for nautilus/nocturne. https://review.coreboot.org/#/c/27350/1/src/mainboard/google/poppy/variants… PS1, Line 122: remove the blanks https://review.coreboot.org/#/c/27350/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h: https://review.coreboot.org/#/c/27350/1/src/mainboard/google/poppy/variants… PS1, Line 27: #define EN_CAM_CLOCK GPP_D18 suggest to add one more tab to align in gerrit review. -- To view, visit https://review.coreboot.org/27350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Gerrit-Change-Number: 27350 Gerrit-PatchSet: 1 Gerrit-Owner: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: JasonX Z Chen <jasonx.z.chen(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Wed, 04 Jul 2018 07:30:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: [Atlas] MIPI camera ASL files for Atlas
by Ping-chung Chen (Code Review) 04 Jul '18

04 Jul '18

Ping-chung Chen has removed Andy Yeh from this change. ( https://review.coreboot.org/27350 ) Change subject: [Atlas] MIPI camera ASL files for Atlas ...................................................................... Removed reviewer Andy Yeh. -- To view, visit https://review.coreboot.org/27350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteReviewer Gerrit-Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Gerrit-Change-Number: 27350 Gerrit-PatchSet: 1 Gerrit-Owner: Ping-chung Chen <ping-chung.chen(a)intel.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: JasonX Z Chen <jasonx.z.chen(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: [Atlas] MIPI camera ASL files for Atlas
by Ping-chung Chen (Code Review) 04 Jul '18

04 Jul '18

Ping-chung Chen has uploaded this change for review. ( https://review.coreboot.org/27350 Change subject: [Atlas] MIPI camera ASL files for Atlas ...................................................................... [Atlas] MIPI camera ASL files for Atlas Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl A src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl M src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h 7 files changed, 233 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27350/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig old mode 100644 new mode 100755 index 7ad846e..b2ff703 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -141,6 +141,7 @@ select DRIVERS_SPI_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select MAINBOARD_HAS_SPI_TPM_CR50 + select VARIANT_HAS_CAMERA_ACPI config VARIANT_SPECIFIC_OPTIONS_POPPY def_bool n diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb old mode 100644 new mode 100755 index 34bc4d4..7085d06 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -40,8 +40,8 @@ register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" - register "Cio2Enable" = "0" # FIXME: enable once MIPI is ready - register "SaImguEnable" = "0" # FIXME: enable once MIPI is ready + register "Cio2Enable" = "1" # FIXME: enable once MIPI is ready + register "SaImguEnable" = "1" # FIXME: enable once MIPI is ready register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl new file mode 100755 index 0000000..9405e2b --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/camera.asl @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "mipi_camera.asl" diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl new file mode 100755 index 0000000..5dc747b --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_endpoints.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.CIO2) +{ + Name (EP00, Package() { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "endpoint", 0 }, + Package () { "clock-lanes", 0 }, + Package () { "data-lanes", Package () { 1, 2 } }, + Package () { "remote-endpoint", + Package() { \_SB.PCI0.I2C3.CAM0, 0, 0 } + }, + } + }) +} diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl new file mode 100755 index 0000000..a7fdadf --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/ipu_mainboard.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.CIO2) +{ + /* Define two ports for CIO2 device where endpoint of port0 + is connected to CAM0 and endpoint of port1 is connected to CAM1 */ + + Name (_DSD, Package () { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "port0", "PRT0" }, + } + }) + + Name (PRT0, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port", 0 }, /* csi 0 */ + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "endpoint0", "EP00" }, + } + }) + +} diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl new file mode 100755 index 0000000..008adbe --- /dev/null +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/mipi_camera.asl @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C3) +{ + Device (CAM0) + { + Name (_HID, "INT3478") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "SONY IMX208 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (STA, 0) + Method (PMON, 0, Serialized) { + If (STA == 0) { + CTXS (EN_CAM_PMIC_RST_L) + STXS (EN_PP3300_DX_CAM) + Sleep(3) + STXS (EN_CAM_PMIC_RST_L) + STXS (EN_CAM_CLOCK) + Sleep(11); + } + STA++ + } + + Method (PMOF, 0, Serialized) { + If (STA == 0) { + Return + } + STA-- + If (STA == 0) { + CTXS (EN_CAM_CLOCK) + CTXS (EN_CAM_PMIC_RST_L) + CTXS (EN_PP3300_DX_CAM) + } + } + + Name (_PR0, Package (0x01) { FCPR }) + Name (_PR3, Package (0x01) { FCPR }) + + /* Power resource methods for Rear Camera */ + PowerResource (FCPR, 0, 0) { + Method (_ON, 0, Serialized) { + PMON () + } + Method (_OFF, 0, Serialized) { + PMOF () + } + Method (_STA, 0, Serialized) { + If (LGreater(STA,0)) { + Return (0x1) + } + Else { + Return (0x0) + } + } + } + + /* Port0 of CAM0 is connected to port0 of CIO2 device */ + Name (_DSD, Package () { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "port0", "PRT0" }, + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 19200000 }, + } + }) + + Name (PRT0, Package() { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port", 0 }, + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "endpoint0", "EP00" }, + } + }) + + Name (EP00, Package() { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "endpoint", 0 }, + Package () { "clock-lanes", 0 }, + Package () { "data-lanes", + Package () { 1, 2 } + }, + Package () { "link-frequencies", + Package() { 384000000, 96000000 } + }, + Package () { "remote-endpoint", + Package() { \_SB.PCI0.CIO2, 0, 0 } + }, + } + }) + + Method (SSDB, 0, Serialized) + { + Return (Buffer (0x5E) + { + /* 0000 */ 0x00, 0x30, 0x00, 0x00, 0x00, 0x00,0x00, 0x00, + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0028 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0030 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0038 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0040 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0048 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0050 */ 0x09, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x36, + /* 0058 */ 0x6E, 0x01, 0x00, 0x00, 0x00, 0x00 + }) + } + } +} diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h old mode 100644 new mode 100755 index f28fb31..9c7276f --- a/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/gpio.h @@ -24,4 +24,6 @@ #undef EN_CAM_PMIC_RST_L #define EN_CAM_PMIC_RST_L GPP_D17 +#define EN_CAM_CLOCK GPP_D18 + #endif /* __MAINBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/27350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Gerrit-Change-Number: 27350 Gerrit-PatchSet: 1 Gerrit-Owner: Ping-chung Chen <ping-chung.chen(a)intel.com>

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Change in coreboot[master]: mediatek: Share MMU operation code among similar SOCs
by Tristan Hsieh (Code Review) 04 Jul '18

04 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27349 Change subject: mediatek: Share MMU operation code among similar SOCs ...................................................................... mediatek: Share MMU operation code among similar SOCs Refactor MMU operation code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/oak/romstage.c R src/soc/mediatek/common/include/soc/mmu_operations.h A src/soc/mediatek/common/mmu_operations.c M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/bootblock.c M src/soc/mediatek/mt8173/flash_controller.c A src/soc/mediatek/mt8173/include/soc/dram_dma.h M src/soc/mediatek/mt8173/mmu_operations.c 8 files changed, 105 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27349/1 diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index 1f56547..9f5ce5f 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -63,7 +63,7 @@ else mt_pll_raise_ca53_freq(1700 * MHz); - mt8173_mmu_after_dram(); + mtk_mmu_after_dram(); /* should be called after memory init */ cbmem_initialize_empty(); diff --git a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h similarity index 69% rename from src/soc/mediatek/mt8173/include/soc/mmu_operations.h rename to src/soc/mediatek/common/include/soc/mmu_operations.h index 2428c42..687bb5c 100644 --- a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h +++ b/src/soc/mediatek/common/include/soc/mmu_operations.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2015 MediaTek Inc. + * Copyright 2018 MediaTek Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ -#define __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ +#ifndef __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__ +#define __SOC_MEDIATEK_COMMON_MMU_OPERATIONS_H__ #include <arch/mmu.h> @@ -29,11 +29,11 @@ extern unsigned char _esram_l2c[]; #define _sram_l2c_size (_esram_l2c - _sram_l2c) -extern unsigned char _dram_dma[]; -extern unsigned char _edram_dma[]; -#define _dram_dma_size (_edram_dma - _dram_dma) +void mtk_mmu_config_dram_dma(void); +void mtk_disable_l2c_sram(void); -void mt8173_mmu_init(void); -void mt8173_mmu_after_dram(void); +void mtk_mmu_init(void); +void mtk_mmu_after_dram(void); +void mtk_mmu_disable_l2c_sram(void); -#endif //__SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ +#endif diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c new file mode 100644 index 0000000..cb921f8 --- /dev/null +++ b/src/soc/mediatek/common/mmu_operations.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmu.h> +#include <compiler.h> +#include <symbols.h> +#include <soc/emi.h> +#include <soc/mmu_operations.h> + +__weak void mtk_mmu_config_dram_dma(void) { /* do nothing */ } + +void mtk_mmu_init(void) +{ + mmu_init(); + + /* Set 0x0 to the end of 2GB dram address as device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM); + + /* SRAM is cached */ + mmu_config_range(_sram, _sram_size, CACHED_MEM); + + /* L2C SRAM is cached */ + mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM); + + /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ + mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + + mmu_enable(); +} + +void mtk_mmu_after_dram(void) +{ + /* Map DRAM as cached now that it's up and running */ + mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM); + + mtk_mmu_config_dram_dma(); +} + +void mtk_mmu_disable_l2c_sram(void) +{ + /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ + /* TODO: Implement true unmapping, and also use it for the zero-page! */ + mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM); + + /* Careful: changing cache geometry while it's active is a bad idea! */ + mmu_disable(); + + mtk_disable_l2c_sram(); + + /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ + mmu_enable(); +} diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 56c966a..d661832 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -29,7 +29,7 @@ bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c bootblock-y += ../common/wdt.c -bootblock-y += mmu_operations.c +bootblock-y += ../common/mmu_operations.c mmu_operations.c ################################################################################ @@ -58,7 +58,7 @@ romstage-y += pmic_wrap.c mt6391.c romstage-y += memory.c romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c -romstage-y += mmu_operations.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += rtc.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index 7fe879c..efccc0b 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -29,7 +29,7 @@ /* post init pll */ mt_pll_post_init(); - mt8173_mmu_init(); + mtk_mmu_init(); /* init watch dog, will disable AP watch dog */ mtk_wdt_init(); diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index f776885..6856dcd 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -25,8 +25,8 @@ #include <string.h> #include <symbols.h> #include <timer.h> +#include <soc/dram_dma.h> #include <soc/flash_controller.h> -#include <soc/mmu_operations.h> #define get_nth_byte(d, n) ((d >> (8 * n)) & 0xff) diff --git a/src/soc/mediatek/mt8173/include/soc/dram_dma.h b/src/soc/mediatek/mt8173/include/soc/dram_dma.h new file mode 100644 index 0000000..8e2d0a4 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/dram_dma.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ +#define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ + +extern unsigned char _dram_dma[]; +extern unsigned char _edram_dma[]; +#define _dram_dma_size (_edram_dma - _dram_dma) + +#endif diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c index c744d65..c66fb3a 100644 --- a/src/soc/mediatek/mt8173/mmu_operations.c +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -15,55 +15,22 @@ #include <arch/io.h> #include <arch/mmu.h> -#include <console/console.h> #include <symbols.h> -#include <stdlib.h> -#include <stdint.h> -#include <soc/addressmap.h> -#include <soc/emi.h> +#include <soc/dram_dma.h> #include <soc/infracfg.h> #include <soc/mcucfg.h> #include <soc/mmu_operations.h> -void mt8173_mmu_init(void) +void mtk_mmu_config_dram_dma(void) { - mmu_init(); - - /* Set 0x0 to the end of 2GB dram address as device memory */ - mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM); - - /* SRAM is cached */ - mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM); - - /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ - mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); - - /* set ttb as secure */ - mmu_config_range(_ttb, _ttb_size, SECURE_MEM); - - mmu_enable(); + mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM); } -void mt8173_mmu_after_dram(void) +void mtk_disable_l2c_sram(void) { - /* Map DRAM as cached now that it's up and running */ - mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM); - - /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ - /* TODO: Implement true unmapping, and also use it for the zero-page! */ - mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM); - - mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM); - - /* Careful: changing cache geometry while it's active is a bad idea! */ - mmu_disable(); - /* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max * available L2 cache for A53 in MT8173. */ write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8); /* turn off the l2c sram clock */ write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN); - - /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ - mmu_enable(); } -- To view, visit https://review.coreboot.org/27349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f Gerrit-Change-Number: 27349 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: riscv: temporarily block multiple-threads
by Anonymous Coward (Code Review) 04 Jul '18

04 Jul '18

Anonymous Coward (1001664) has uploaded this change for review. ( https://review.coreboot.org/27348 Change subject: riscv: temporarily block multiple-threads ...................................................................... riscv: temporarily block multiple-threads Sometime needs to temporarily block multiple-threads. So add this code. Change-Id: Iedf58db6cddd44cfc17f5dfb3a5ccc0e12a49536 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A src/arch/riscv/include/smp.h 1 file changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27348/1 diff --git a/src/arch/riscv/include/smp.h b/src/arch/riscv/include/smp.h new file mode 100644 index 0000000..6253768 --- /dev/null +++ b/src/arch/riscv/include/smp.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, + * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _SMP_H +#define _SMP_H + +#include <atomic.h> + +#define barrier() {asm volatile ("fence" ::: "memory"); } + +/* + * If your code needs to temporarily block multiple-threads, do this: + * if(RUNNING_ON_HART(active)) // `active` is hartid of working thread + * { + * ... single-threaded work ... + * } + * SMP_SYNC(); + * //`SMP_SYNC` is optional. + * // if other hart need to wait for the single-threaded work to complete. + * ... multi-threaded work ... + */ + + +#define RUNNING_ON_HART(active) ((active) == read_csr(mhartid)) + +#define SMP_SYNC() do {\ +static int counter;\ +atomic_add(&counter, 1);\ +do { barrier(); } while (counter < CONFIG_HART_NUM);\ +} while (0) + +#endif //_SMP_H -- To view, visit https://review.coreboot.org/27348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iedf58db6cddd44cfc17f5dfb3a5ccc0e12a49536 Gerrit-Change-Number: 27348 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward (1001664)

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