coreboot-gerrit July 2018

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Change in coreboot[master]: riscv: add spin lock support
by Jonathan Neuschäfer (Code Review) 05 Jul '18

05 Jul '18

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Change in coreboot[master]: riscv: add spin lock support
by Jonathan Neuschäfer (Code Review) 05 Jul '18

05 Jul '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27356 ) Change subject: riscv: add spin lock support ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/27356/2/src/arch/riscv/include/arch/smp/spi… File src/arch/riscv/include/arch/smp/spinlock.h: https://review.coreboot.org/#/c/27356/2/src/arch/riscv/include/arch/smp/spi… PS2, Line 30: } while (atomic_cas(&lock->lock, 0, -1)); As far as I understand it, CAS is not a native operation on RISC-V. What does this compile to? https://review.coreboot.org/#/c/27356/2/src/arch/riscv/include/arch/smp/spi… PS2, Line 39: Some primitives are missing, compared to the x86 pendant, but I think it's ok to add them later, when they're needed. -- To view, visit https://review.coreboot.org/27356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Gerrit-Change-Number: 27356 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward (1001664) Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Jul 2018 10:46:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: temporarily block multiple-threads
by Anonymous Coward (Code Review) 05 Jul '18

05 Jul '18

Anonymous Coward (1001664) has uploaded this change for review. ( https://review.coreboot.org/27358 Change subject: riscv: temporarily block multiple-threads ...................................................................... riscv: temporarily block multiple-threads Sometime needs to temporarily block multiple-threads. So add this code. Change-Id: Ia0eeed51e0952c66a9a9f25a90105fe471ffa70e Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/arch/smp/smp.h 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27358/1 diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h index bdf8ec4..2672595 100644 --- a/src/arch/riscv/include/arch/smp/smp.h +++ b/src/arch/riscv/include/arch/smp/smp.h @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2018 HardenedLinux. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -10,3 +12,31 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#ifndef _SMP_H +#define _SMP_H + +#include <arch/smp/atomic.h> +#include <arch/smp/spinlock.h> + + /* + * If your code needs to temporarily block multiple-threads, do this: + * if(RUNNING_ON_HART(active)) // `active` is hartid of working thread + * { + * ... single-threaded work ... + * } + * SMP_SYNC(); + * //`SMP_SYNC` is not required, if other hart not need to wait for + * //the single-threaded work to complete. + * ... multi-threaded work ... + */ + + +#define RUNNING_ON_HART(active) ((active) == read_csr(mhartid)) + +#define SMP_SYNC() do {\ +static int counter;\ +atomic_add(&counter, 1);\ +do { barrier(); } while (counter < CONFIG_HART_NUM);\ +} while (0) + + #endif //_SMP_H -- To view, visit https://review.coreboot.org/27358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia0eeed51e0952c66a9a9f25a90105fe471ffa70e Gerrit-Change-Number: 27358 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward (1001664)

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Change in coreboot[master]: riscv: adjust directory structure
by Jonathan Neuschäfer (Code Review) 05 Jul '18

05 Jul '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27355 ) Change subject: riscv: adjust directory structure ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/27355/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27355/1//COMMIT_MSG@7 PS1, Line 7: riscv: adjust directory structure "riscv: adjust directory structure" doesn't say much. How about something like "riscv: add include/arch/smp/ directory" ? -- To view, visit https://review.coreboot.org/27355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I27aee55f24d96ba9e7d8f2e6653f6c9c5e85c66a Gerrit-Change-Number: 27355 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward (1001664) Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Jul 2018 10:28:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/cbfstool/compiler: __attribute redefinition
by Frans Hendriks (Code Review) 05 Jul '18

05 Jul '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/27357 Change subject: util/cbfstool/compiler: __attribute redefinition ...................................................................... util/cbfstool/compiler: __attribute redefinition In Windows Cygwin enviroment, compiler reports redefinition error at cbfstool/ifwitool.c on _packed and __aligned. Skip new defines when vales are already defined. Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M util/cbfstool/compiler.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27357/1 diff --git a/util/cbfstool/compiler.h b/util/cbfstool/compiler.h index fc6a36b..cf043d5 100644 --- a/util/cbfstool/compiler.h +++ b/util/cbfstool/compiler.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2017 Google Inc. + * Copyright (c) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,14 +19,18 @@ #if !defined(__FreeBSD__) +#if !defined(__packed) #if defined(__WIN32) || defined(__WIN64) #define __packed __attribute__((gcc_struct, packed)) #else #define __packed __attribute__((packed)) #endif +#endif +#if !defined(__aligned) #define __aligned(x) __attribute__((aligned(x))) #endif +#endif #define __always_unused __attribute__((unused)) #define __must_check __attribute__((warn_unused_result)) -- To view, visit https://review.coreboot.org/27357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce Gerrit-Change-Number: 27357 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: riscv: add spin lock support
by Anonymous Coward (Code Review) 05 Jul '18

05 Jul '18

Anonymous Coward (1001664) has uploaded a new patch set (#2). ( https://review.coreboot.org/27356 ) Change subject: riscv: add spin lock support ...................................................................... riscv: add spin lock support Add spin lock support for riscv. Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/arch/smp/atomic.h M src/arch/riscv/include/arch/smp/spinlock.h 2 files changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/27356/2 -- To view, visit https://review.coreboot.org/27356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Gerrit-Change-Number: 27356 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward (1001664)

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Change in coreboot[master]: riscv: add spin lock support
by Anonymous Coward (Code Review) 05 Jul '18

05 Jul '18

Anonymous Coward (1001664) has uploaded this change for review. ( https://review.coreboot.org/27356 Change subject: riscv: add spin lock support ...................................................................... riscv: add spin lock support Add spin lock support for riscv. Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/include/arch/smp/atomic.h M src/arch/riscv/include/arch/smp/spinlock.h 2 files changed, 26 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/27356/1 diff --git a/src/arch/riscv/include/arch/smp/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h index 15702e4..f1d8e45 100644 --- a/src/arch/riscv/include/arch/smp/atomic.h +++ b/src/arch/riscv/include/arch/smp/atomic.h @@ -33,9 +33,6 @@ #define disable_irqsave() clear_csr(mstatus, MSTATUS_MIE) #define enable_irqrestore(flags) set_csr(mstatus, (flags) & MSTATUS_MIE) -typedef struct { int lock; } spinlock_t; -#define SPINLOCK_INIT {0} - #define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val) #define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr)) diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h index bdf8ec4..089ab9f 100644 --- a/src/arch/riscv/include/arch/smp/spinlock.h +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -10,3 +10,29 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#ifndef _SPINLOCK_H_ +#define _SPINLOCK_H_ + +#include <arch/encoding.h> +#include <arch/smp/atomic.h> + +#define barrier() { asm volatile ("fence" ::: "memory"); } + +typedef struct { + volatile unsigned int lock; +} spinlock_t; + +static inline void spinlock_lock(spinlock_t *lock) +{ + do { + } while (atomic_cas(&lock->lock, 0, -1)); + barrier(); +} + +static inline void spinlock_unlock(spinlock_t *lock) +{ + barrier(); + atomic_set(&lock->lock, 0); +} + +#endif //_SPINLOCK_H_ -- To view, visit https://review.coreboot.org/27356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Gerrit-Change-Number: 27356 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward (1001664)

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Change in coreboot[master]: riscv: adjust directory structure
by Anonymous Coward (Code Review) 05 Jul '18

05 Jul '18

Anonymous Coward (1001664) has uploaded this change for review. ( https://review.coreboot.org/27355 Change subject: riscv: adjust directory structure ...................................................................... riscv: adjust directory structure Replicate directory layout from x86 for SMP. Change-Id: I27aee55f24d96ba9e7d8f2e6653f6c9c5e85c66a Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- R src/arch/riscv/include/arch/smp/atomic.h A src/arch/riscv/include/arch/smp/smp.h A src/arch/riscv/include/arch/smp/spinlock.h M src/arch/riscv/include/mcall.h M src/arch/riscv/mcall.c 5 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/27355/1 diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h similarity index 100% rename from src/arch/riscv/include/atomic.h rename to src/arch/riscv/include/arch/smp/atomic.h diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h new file mode 100644 index 0000000..bdf8ec4 --- /dev/null +++ b/src/arch/riscv/include/arch/smp/smp.h @@ -0,0 +1,12 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h new file mode 100644 index 0000000..bdf8ec4 --- /dev/null +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -0,0 +1,12 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index e4bc36f..f3f8e13 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -26,7 +26,7 @@ #ifndef __ASSEMBLER__ #include <arch/encoding.h> -#include <atomic.h> +#include <arch/smp/atomic.h> #include <stdint.h> typedef struct { diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index 030accf..92515a3 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -27,7 +27,7 @@ #include <arch/barrier.h> #include <arch/errno.h> -#include <atomic.h> +#include <arch/smp/atomic.h> #include <console/console.h> #include <mcall.h> #include <string.h> -- To view, visit https://review.coreboot.org/27355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I27aee55f24d96ba9e7d8f2e6653f6c9c5e85c66a Gerrit-Change-Number: 27355 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward (1001664)

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Change in coreboot[master]: 3rdparty/blobs: Update to include new Intel model 306ax microcode
by Martin Kepplinger (Code Review) 05 Jul '18

05 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27354 to look at the new patch set (#2). Change subject: 3rdparty/blobs: Update to include new Intel model 306ax microcode ...................................................................... 3rdparty/blobs: Update to include new Intel model 306ax microcode Change-Id: I0a8dd5fd2860fff0d293667b1c37dc23c00665ac Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/27354/2 -- To view, visit https://review.coreboot.org/27354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0a8dd5fd2860fff0d293667b1c37dc23c00665ac Gerrit-Change-Number: 27354 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: 3rdparty/blobs: Update to include new Intel model 306ax microcode
by Martin Kepplinger (Code Review) 05 Jul '18

05 Jul '18

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/27354 Change subject: 3rdparty/blobs: Update to include new Intel model 306ax microcode ...................................................................... 3rdparty/blobs: Update to include new Intel model 306ax microcode Change-Id: I0a8dd5fd2860fff0d293667b1c37dc23c00665ac Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/27354/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 3854ad2..1b3e127 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 3854ad29e7b767001d4f6dd93eba0d79aedda9c3 +Subproject commit 1b3e127e7f8e60018f91040d9fe20a89851bac44 -- To view, visit https://review.coreboot.org/27354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0a8dd5fd2860fff0d293667b1c37dc23c00665ac Gerrit-Change-Number: 27354 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de>

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coreboot-gerrit July 2018