coreboot-gerrit July 2018

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Change in coreboot[master]: payloads/LinuxBoot: Add ARM64 support
by Philipp Deppenwiese (Code Review) 06 Jul '18

06 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/25152 ) Change subject: payloads/LinuxBoot: Add ARM64 support ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/25152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c Gerrit-Change-Number: 25152 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Jul 2018 15:46:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/cbfstool/compiler: __attribute redefinition
by Patrick Georgi (Code Review) 06 Jul '18

06 Jul '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27357 ) Change subject: util/cbfstool/compiler: __attribute redefinition ...................................................................... util/cbfstool/compiler: __attribute redefinition In Windows Cygwin enviroment, compiler reports redefinition error at cbfstool/ifwitool.c on _packed and __aligned. Skip new defines when vales are already defined. Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/27357 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/cbfstool/compiler.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/util/cbfstool/compiler.h b/util/cbfstool/compiler.h index fc6a36b..cf043d5 100644 --- a/util/cbfstool/compiler.h +++ b/util/cbfstool/compiler.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2017 Google Inc. + * Copyright (c) 2017-2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,14 +19,18 @@ #if !defined(__FreeBSD__) +#if !defined(__packed) #if defined(__WIN32) || defined(__WIN64) #define __packed __attribute__((gcc_struct, packed)) #else #define __packed __attribute__((packed)) #endif +#endif +#if !defined(__aligned) #define __aligned(x) __attribute__((aligned(x))) #endif +#endif #define __always_unused __attribute__((unused)) #define __must_check __attribute__((warn_unused_result)) -- To view, visit https://review.coreboot.org/27357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce Gerrit-Change-Number: 27357 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/cbfstool/compiler: __attribute redefinition
by Patrick Georgi (Code Review) 06 Jul '18

06 Jul '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/27357 ) Change subject: util/cbfstool/compiler: __attribute redefinition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3af3c6b8fc57eee345afcef2f871b897138f78ce Gerrit-Change-Number: 27357 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Jul 2018 13:10:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/d945gclf/romstage.c: Remove unneeded includes
by Patrick Georgi (Code Review) 06 Jul '18

06 Jul '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27345 ) Change subject: mb/intel/d945gclf/romstage.c: Remove unneeded includes ...................................................................... mb/intel/d945gclf/romstage.c: Remove unneeded includes Change-Id: I3bdb93e51cabbfc14fe992ccdb6556e344e03c2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/27345 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/d945gclf/romstage.c 1 file changed, 1 insertion(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 27c1e3e..57f32c2 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -16,17 +16,12 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> -#include <string.h> -#include <arch/io.h> #include <device/pci_def.h> +#include <arch/io.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <lib.h> -#include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <superio/smsc/lpc47m15x/lpc47m15x.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> -- To view, visit https://review.coreboot.org/27345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3bdb93e51cabbfc14fe992ccdb6556e344e03c2f Gerrit-Change-Number: 27345 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/ibase/mb899: Remove unneeded includes
by Patrick Georgi (Code Review) 06 Jul '18

06 Jul '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27344 ) Change subject: mb/ibase/mb899: Remove unneeded includes ...................................................................... mb/ibase/mb899: Remove unneeded includes Change-Id: Iee237206f309409be64307d2daee044da52a05e1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/27344 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/ibase/mb899/mainboard.c M src/mainboard/ibase/mb899/romstage.c 2 files changed, 8 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index 0629d33..d4d05c3 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -13,17 +13,10 @@ * GNU General Public License for more details. */ -#include <types.h> #include <device/device.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> -#include <arch/io.h> -#include <arch/interrupt.h> #include "superio_hwm.h" - - // mainboard_enable is executed as first thing after // enumerate_buses(). diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index dd384ac..78ec5ed 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -16,25 +16,20 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> -#include <string.h> +#include <halt.h> #include <arch/io.h> +#include <timestamp.h> +#include <console/console.h> +#include <cpu/intel/romstage.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <lib.h> -#include <arch/acpi.h> -#include <cbmem.h> -#include <timestamp.h> -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627ehg/w83627ehg.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627ehg/w83627ehg.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) -- To view, visit https://review.coreboot.org/27344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iee237206f309409be64307d2daee044da52a05e1 Gerrit-Change-Number: 27344 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google: Use proper ACPI ID for Semtech chips: STH
by Patrick Georgi (Code Review) 06 Jul '18

06 Jul '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/27347 ) Change subject: google: Use proper ACPI ID for Semtech chips: STH ...................................................................... google: Use proper ACPI ID for Semtech chips: STH Change-Id: I85cd567a923cccd2504f351aae276b5f0d9db4de Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Reviewed-on: https://review.coreboot.org/27347 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt Delco <delco(a)google.com> Reviewed-by: Seunghwan Kim <sh_.kim(a)samsung.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/i2c/sx9310/sx9310.c M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/zoombini/variants/meowth/devicetree.cb 3 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Seunghwan Kim: Looks good to me, but someone else must approve Matt Delco: Looks good to me, but someone else must approve diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index 5f63734..3443f5c 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -22,7 +22,7 @@ #include <string.h> #include "chip.h" -#define I2C_SX9310_ACPI_ID "SX9310" +#define I2C_SX9310_ACPI_ID "STH9310" #define I2C_SX9310_ACPI_NAME "Semtech SX9310" #define REGISTER(NAME) acpi_dp_add_integer(dsd, \ diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 68246c6..b2617e5 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -330,7 +330,7 @@ end # I2C #1 device pci 15.2 on chip drivers/i2c/generic - register "hid" = ""SX9321"" + register "hid" = ""STH9321"" register "name" = ""SEMTECH SX9321"" register "desc" = ""SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A18_IRQ)" diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index adeedea..bbff695 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -107,7 +107,7 @@ end # I2C #0 device pci 15.1 on chip drivers/i2c/generic - register "hid" = ""SX9310"" + register "hid" = ""STH9310"" register "name" = ""SEMTECH SX9310"" register "desc" = ""Left SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C3_IRQ)" @@ -145,7 +145,7 @@ device pci 19.0 on end # I2C #4 device pci 19.1 on chip drivers/i2c/generic - register "hid" = ""SX9310"" + register "hid" = ""STH9310"" register "name" = ""SEMTECH SX9310"" register "desc" = ""Right SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C4_IRQ)" -- To view, visit https://review.coreboot.org/27347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I85cd567a923cccd2504f351aae276b5f0d9db4de Gerrit-Change-Number: 27347 Gerrit-PatchSet: 3 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Matt Delco <delco(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: [WIP] enable microcode update
by Rizwan Qureshi (Code Review) 06 Jul '18

06 Jul '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/27370 Change subject: soc/intel/skylake: [WIP] enable microcode update ...................................................................... soc/intel/skylake: [WIP] enable microcode update Change-Id: Ic492a8600c7400055ce4b950408f33c6463e0f92 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/romstage/romstage_fsp20.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27370/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3e0158b..fdf78f5 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -74,6 +74,8 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC + select INTEL_HAS_TOP_SWAP + select INTEL_ADD_TOP_SWAP_BOOTBLOCK config MAINBOARD_USES_FSP2_0 bool @@ -348,5 +350,7 @@ config IFD_CHIPSET string default "sklkbl" - +config INTEL_TOP_SWAP_FIT_ENTRY + string + default "RW_UCODE_STAGED" endif diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 64f9d7d..d4d27b1 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -38,6 +38,7 @@ #include <string.h> #include <timestamp.h> #include <security/vboot/vboot_common.h> +#include <soc/ucode_update.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -142,6 +143,7 @@ struct chipset_power_state *ps; console_init(); + check_and_update_ucode(); /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); -- To view, visit https://review.coreboot.org/27370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic492a8600c7400055ce4b950408f33c6463e0f92 Gerrit-Change-Number: 27370 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: [WIP] Library for working with RW_UCODE_UPDATE NV ...
by Rizwan Qureshi (Code Review) 06 Jul '18

06 Jul '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/27368 Change subject: soc/intel/skylake: [WIP] Library for working with RW_UCODE_UPDATE NV region ...................................................................... soc/intel/skylake: [WIP] Library for working with RW_UCODE_UPDATE NV region Change-Id: I40e8d315618962b50d6fed97fa094b941246c934 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/skylake/Makefile.inc A src/soc/intel/skylake/fw_update_nv.c A src/soc/intel/skylake/include/soc/fw_update_nv.h 3 files changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27368/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 89e48f1..fe687ce 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -28,6 +28,7 @@ verstage-y += spi.c verstage-$(CONFIG_UART_DEBUG) += uart.c +romstage-y += fw_update_nv.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c diff --git a/src/soc/intel/skylake/fw_update_nv.c b/src/soc/intel/skylake/fw_update_nv.c new file mode 100644 index 0000000..fced985 --- /dev/null +++ b/src/soc/intel/skylake/fw_update_nv.c @@ -0,0 +1,63 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <string.h> +#include <fmap.h> +#include <ip_checksum.h> +#include <soc/fw_update_nv.h> + +int get_update_nv_storage(struct region_device *rdev) +{ + if (fmap_locate_area_as_rdev_rw("RW_UPDATE_STATE", rdev)){ + printk(BIOS_ERR, "%s: failed to locate UPDATE NVRAM\n", __func__); + return 1; + } + return 0; +} + +int get_update_state(struct region_device *rdev, + struct fw_update_nv *update_state) { + + /* read the nvdata and write it to the cache */ + if (rdev_readat(rdev, (void *) update_state, INIT_OFFSET, + FW_UPDATE_NV_DATA_SIZE) < 0) { + printk(BIOS_ERR, "failed to read nvdata\n"); + return 1; + } + printk (BIOS_ERR, "ucode: 0x%x\ncse: 0x%x\n", + update_state->ucode_state, + update_state->cse_state); + return 0; +} + +int set_update_state(struct region_device *rdev, + struct fw_update_nv *update_state) { + + update_state->checksum = compute_ip_checksum( + (void *)update_state, + FW_UPDATE_NV_DATA_SIZE); + + if (rdev_writeat(rdev, update_state, 0, FW_UPDATE_NV_DATA_SIZE) != + FW_UPDATE_NV_DATA_SIZE) { + printk(BIOS_ERR, "failed to Write nvdata\n"); + return 1; + } + return 0; +} + diff --git a/src/soc/intel/skylake/include/soc/fw_update_nv.h b/src/soc/intel/skylake/include/soc/fw_update_nv.h new file mode 100644 index 0000000..b120aa5 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/fw_update_nv.h @@ -0,0 +1,28 @@ +#define FW_UPDATE_NV_DATA_SIZE 16 +#define ERASE_VALUE 0xff + +enum update_state { + UPDATE_VERIFIED, + UPDATE_START, + UPDATE_WRITE_COMPLETE +}; + +enum update_nv_offsets { + INIT_OFFSET, + UCODE_UPDATE_NV_OFFSET=1, + CSE_UPDATE_NV_OFFSET=2, +}; + +struct fw_update_nv { + char initialized; + enum update_state ucode_state; + enum update_state cse_state; + uint16_t checksum; + char unused[5]; +}; + +int get_update_nv_storage(struct region_device *rdev); +int get_update_state(struct region_device *rdev, + struct fw_update_nv *update_state); +int set_update_state(struct region_device *rdev, + struct fw_update_nv *update_state); -- To view, visit https://review.coreboot.org/27368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I40e8d315618962b50d6fed97fa094b941246c934 Gerrit-Change-Number: 27368 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: [WIP] Add support for updating microcode in the field
by Rizwan Qureshi (Code Review) 06 Jul '18

06 Jul '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/27369 Change subject: soc/intel/skylake: [WIP] Add support for updating microcode in the field ...................................................................... soc/intel/skylake: [WIP] Add support for updating microcode in the field Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- A src/soc/intel/skylake/include/soc/ucode_update.h M src/soc/intel/skylake/romstage/Makefile.inc A src/soc/intel/skylake/romstage/ucode_update.c 3 files changed, 287 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/1 diff --git a/src/soc/intel/skylake/include/soc/ucode_update.h b/src/soc/intel/skylake/include/soc/ucode_update.h new file mode 100644 index 0000000..4a8e67b --- /dev/null +++ b/src/soc/intel/skylake/include/soc/ucode_update.h @@ -0,0 +1 @@ +int check_and_update_ucode(void); diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 8bfbfea..aa70488 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -2,3 +2,4 @@ romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += systemagent.c +romstage-y += ucode_update.c diff --git a/src/soc/intel/skylake/romstage/ucode_update.c b/src/soc/intel/skylake/romstage/ucode_update.c new file mode 100644 index 0000000..9a74c0a --- /dev/null +++ b/src/soc/intel/skylake/romstage/ucode_update.c @@ -0,0 +1,285 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <arch/early_variables.h> +#include <arch/io.h> +#include <arch/symbols.h> +#include <assert.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cbmem.h> +#include <chip.h> +#include <console/console.h> +#include <cpu/intel/microcode.h> +#include <fmap.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <string.h> +#include <stdlib.h> +#include <stdint.h> +#include <timestamp.h> +#include <security/vboot/vboot_common.h> +#include <ec/google/chromeec/ec.h> +#include <reset.h> +#include <intelblocks/lpc_lib.h> +#include <soc/ucode_update.h> +#include <intelblocks/rtc.h> +#include <lib.h> +#include <soc/fw_update_nv.h> + +/* convert a pointer to flash area into the offset inside the flash */ +static inline u32 to_flash_offset(void *p) { + return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); +} + +static void _hard_reset (void){ + hard_reset(); +} + +static int init_state_nv_storage(struct region_device *update_nv, + struct fw_update_nv *update_state) +{ + char empty_nv[FW_UPDATE_NV_DATA_SIZE]; + int i; + + if (get_update_nv_storage(update_nv)) { + printk (BIOS_ERR, "Update NV could not be init\n"); + return 1; + } + + if (get_update_state(update_nv, update_state)) { + printk (BIOS_ERR, "Error reading update state\n"); + return 1; + } + /* if empty, set initial state. This should be done only during first boot */ + for (i=0;i<FW_UPDATE_NV_DATA_SIZE;i++) + empty_nv[i] = ERASE_VALUE; + + hexdump((void *)update_state, FW_UPDATE_NV_DATA_SIZE); + + if (!memcmp((void *)&empty_nv, (void *)update_state, + FW_UPDATE_NV_DATA_SIZE)) { + printk (BIOS_ERR, "Initializing NV\n"); + update_state->ucode_state = UPDATE_VERIFIED; + update_state->cse_state = UPDATE_VERIFIED; + update_state->initialized = 1; + if (set_update_state(update_nv, update_state)) { + printk (BIOS_ERR, "Couldn't write to NV region\n"); + return 1; + } + } + return 0; +} + +static int write_ucode(struct region_device *rdev, void *ucode_stage, + void *cbfs_ucode) +{ + struct spi_flash flash; + + spi_init(); + + if (spi_flash_probe(0, 0, &flash)) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return 1; + } + + if (spi_flash_erase(&flash, + to_flash_offset(ucode_stage) & 0xFFFFFF, + region_device_sz(rdev))){ + printk (BIOS_ERR, + "Failed to erase staging ucode\n"); + return 1; + /*TODO: reset*/ + } + + if(spi_flash_write(&flash, + to_flash_offset(ucode_stage) & 0xFFFFFF, + (size_t) get_microcode_size(cbfs_ucode), cbfs_ucode)){ + printk (BIOS_ERR, + "Failed to update staging ucode\n"); + return 1; + /*TODO: reset*/ + } + + return 0; +} + +static void *get_ucode_staging_area(struct region_device *rdev) +{ + void *ucode_stage = NULL; + + /* Get staging microcode */ + if (fmap_locate_area_as_rdev(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY, + rdev) == 0) { + ucode_stage = rdev_mmap_full(rdev); + if (ucode_stage == NULL ) + printk(BIOS_DEBUG, "ucode staging could not be mapped\n"); + } else { + printk(BIOS_ERR, "ucode stage not found"); + } + + return ucode_stage; +} + +#if 0 +static int is_microcode_header_empty(void * microcode) +{ + char empty_ucode_header[48]; + int i; + + /* if empty, set initial state. This should be done only during first boot */ + for (i = 0; i < 48; i++) + empty_ucode_header[i] = ERASE_VALUE; + + hexdump(microcode, 48); + hexdump((void*)&empty_ucode_header, 48); + if (memcmp((void*)&empty_ucode_header, microcode, 48)) + return 0; + else + return 1; + +} +#endif + +int check_and_update_ucode(void) +{ + uint32_t current_ucode, slot_rev, staging_rev, version_mismatch = 0; + struct region_device rdev; + struct region_device upd_state_nv; + struct fw_update_nv upd_state; + const void *slot_microcode = NULL; + const void *staging_microcode = NULL; + + if (init_state_nv_storage(&upd_state_nv, &upd_state)){ + die("Failed to Initialize update state NV\n"); + } + + /* Get top swap status */ + enum ts_config ts_strap = get_rtc_buc_top_swap_status(); + /* Get recovery mode */ + int rec_mode = vboot_recovery_mode_enabled(); + + /* Get Ucode versions */ + current_ucode = get_current_microcode_rev(); + + slot_microcode = intel_microcode_find(); + slot_rev = get_microcode_rev(slot_microcode) - 1; + + staging_microcode = get_ucode_staging_area(&rdev); + if (staging_microcode == NULL) + return 1; + + staging_rev = get_microcode_rev(staging_microcode) - 1; + + printk(BIOS_DEBUG, "Top Swap: 0x%x\n", ts_strap); + printk(BIOS_DEBUG, "Recovery Mode: 0x%x\n", rec_mode); + printk(BIOS_DEBUG, "Current ucode version: 0x%x\n", current_ucode); + printk(BIOS_DEBUG, "Slot ucode version: 0x%x\n", slot_rev); + printk(BIOS_DEBUG, "Staging area ucode: 0x%x\n", staging_rev); + printk(BIOS_DEBUG, "Update State: 0x%x\n", upd_state.ucode_state); + + if (staging_rev != current_ucode || current_ucode != slot_rev || + staging_rev != slot_rev) + version_mismatch = 1; + + printk(BIOS_DEBUG, "Mismatch: 0x%x\n", version_mismatch); + + if (!rec_mode) { + switch (upd_state.ucode_state) { + case UPDATE_VERIFIED: + if (version_mismatch) { + if (!ts_strap) { + /* We are using a RO ucode, switch to + * top swap FIT. + */ + configure_rtc_buc_top_swap(TS_ENABLE); + _hard_reset(); + } + /* New ucode available, start update process */ + upd_state.ucode_state = UPDATE_START; + if (set_update_state(&upd_state_nv, &upd_state)) + return 1; + if (write_ucode(&rdev, (void *)staging_microcode, + (void *)slot_microcode)) { + printk (BIOS_ERR, "Write failed\n"); + return 1; + } + /* Finished writing, reset */ + upd_state.ucode_state = UPDATE_WRITE_COMPLETE; + if (set_update_state(&upd_state_nv, &upd_state)) { + return 1; + } + _hard_reset(); + } + break; + case UPDATE_WRITE_COMPLETE: + if (version_mismatch) { + if (!ts_strap) { + /* We are using a RO ucode, switch to + * top swap FIT. + */ + configure_rtc_buc_top_swap(TS_ENABLE); + _hard_reset(); + } else { + /* The right ucode could not be loaded + * even after the update. Fallback to + * the previous slot. + */ + } + } else { + /* Update is good, mark verified and continue */ + upd_state.ucode_state = UPDATE_VERIFIED; + if (set_update_state(&upd_state_nv, &upd_state)) + return 1; + } + break; + case UPDATE_START: + /* The previous update did not complete, retry */ + if (!ts_strap) { + /* We are using a RO ucode, switch to + * top swap FIT. + */ + configure_rtc_buc_top_swap(TS_ENABLE); + _hard_reset(); + } + if (write_ucode(&rdev, (void *)staging_microcode, + (void *)slot_microcode)) { + printk (BIOS_ERR, "Write failed\n"); + return 1; + } + upd_state.ucode_state = UPDATE_WRITE_COMPLETE; + if (set_update_state(&upd_state_nv, &upd_state)) { + return 1; + } + _hard_reset(); + } + } else { + /*In recovery, make sure topswap is disabled */ + if (ts_strap) { + configure_rtc_buc_top_swap(TS_DISABLE); + _hard_reset(); + } + } + /* Protect the RW ucode staging area */ + if (spi_flash_ctrlr_protect_region(boot_device_spi_flash(), + &rdev.region) < 0) { + printk(BIOS_ERR, "ERROR setting FPR for staging.\n"); + return 1; + } + + return 0; +} + -- To view, visit https://review.coreboot.org/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: mb/google/poppy: [WIP] Add a region for storing update state
by Rizwan Qureshi (Code Review) 06 Jul '18

06 Jul '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/27367 Change subject: mb/google/poppy: [WIP] Add a region for storing update state ...................................................................... mb/google/poppy: [WIP] Add a region for storing update state Change-Id: I62c9e1238eb0ce0bda5c267b74b16b65b90bc6ab Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/poppy/chromeos.fmd 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/27367/1 diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd index faf50e2..b312fc9 100644 --- a/src/mainboard/google/poppy/chromeos.fmd +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -27,7 +27,8 @@ } RW_VPD@0x48000 0x2000 RW_NVRAM@0x4a000 0x6000 - RW_UPDATE_STATE@0x50000 0x1000 + RW_UPDATE_STATE@0x50000 0x100 + RW_UNUSED@0x50100 0xF00 } RW_LEGACY(CBFS)@0x821000 0x1DF000 WP_RO@0xa00000 0x400000 { -- To view, visit https://review.coreboot.org/27367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I62c9e1238eb0ce0bda5c267b74b16b65b90bc6ab Gerrit-Change-Number: 27367 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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