coreboot-gerrit July 2018

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Jonathan Neuschäfer (Code Review) 07 Jul '18

07 Jul '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27397 ) Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... Patch Set 4: Ok, I remember. My idea for the MBR code was to act like ZSBL to keep the rest of the code simpler because the memory layout upon bootblock entry stays exactly the same: 1. Initialize L2LIM, if it isn't usable right after reset 2. Copy the bootblock from memory-mapped SPI flash to the beginning of L2LIM 3. Jump into L2LIM It may also be possible to execute the bootblock in place, but then you need to change bootblock.S or a linker script or something else to place the stack in L2LIM, not just after the bootblock as it currently is. -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Jul 2018 13:44:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Documentation/mb/sifive: Update TODO list; UART driver has been merged
by Jonathan Neuschäfer (Code Review) 07 Jul '18

07 Jul '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/27398 Change subject: Documentation/mb/sifive: Update TODO list; UART driver has been merged ...................................................................... Documentation/mb/sifive: Update TODO list; UART driver has been merged See 894e3a9ec8 ("drivers/uart: Add a driver for SiFive's UART"). Change-Id: I035c238beba28ecafd296f18c0ccda167126ab94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/mainboard/sifive/hifive-unleashed.md 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/27398/1 diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index bdf5e3c..62ee824 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -12,7 +12,6 @@ The following things are still missing from this coreboot port: - Trampoline in the MBR block to support boot mode 1 -- SiFive UART driver - CBMEM support - FU540 clock configuration - FU540 RAM init -- To view, visit https://review.coreboot.org/27398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I035c238beba28ecafd296f18c0ccda167126ab94 Gerrit-Change-Number: 27398 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Jonathan Neuschäfer (Code Review) 07 Jul '18

07 Jul '18

1 0

Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Jonathan Neuschäfer (Code Review) 07 Jul '18

07 Jul '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27397 ) Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/27397/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27397/3//COMMIT_MSG@11 PS3, Line 11: issues. > The trampoline part contains the location of the bootblock, so if the change is split, the jump woul […] But how is the stack alignment related to the position of the bootblock? I haven't looked at these details of the RISC-V port in a while, and I don't know it, so I think others reading this commit message won't know that either, and it should be explained in the commit message. About splitting the commit: If you do the alignment change first, then you don't need to add a jump instruction and change it later. -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Jul 2018 12:42:53 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Philipp Hug (Code Review) 07 Jul '18

07 Jul '18

Hello Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27397 to look at the new patch set (#4). Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... riscv: add trampoline in MBR block to support boot mode 1 Add "j pc + 0x1000" at the beginning of the MBR to jump to bootblock. Changed first usable LBA to 4 (0x1000) to prevent stack alignment issues. Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M Documentation/mainboard/sifive/hifive-unleashed.md M util/riscv/sifive-gpt.py 2 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27397/4 -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Jonathan Neuschäfer (Code Review) 07 Jul '18

07 Jul '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27397 ) Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/27397/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27397/3//COMMIT_MSG@7 PS3, Line 7: riscv: add trampoline in MBR block to support boot mode 1 There's currently a TODO item about this in Documentation/mainboard/sifive/hifive-unleashed.md. Please remove it so the TODO list stays up to date. -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Jul 2018 12:31:21 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Philipp Hug (Code Review) 07 Jul '18

07 Jul '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/27397 ) Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/27397/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27397/3//COMMIT_MSG@11 PS3, Line 11: issues. > Stack alignment? How is that influenced? […] The trampoline part contains the location of the bootblock, so if the change is split, the jump would need to change as well. The reason for this is, that the same code can be run directly and also when copied by the ZSBL. And the linker complains when putting the stack at a non 0x1000-aligned address. /home/user/dev/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-ld.bfd: stack must be aligned to 4096! -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Jul 2018 12:16:55 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Jonathan Neuschäfer (Code Review) 07 Jul '18

07 Jul '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27397 ) Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... Patch Set 3: (1 comment) Thanks! https://review.coreboot.org/#/c/27397/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27397/3//COMMIT_MSG@11 PS3, Line 11: issues. Stack alignment? How is that influenced? I'd prefer if you split this part out, into a second patch, because it's less obvious. -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Jul 2018 11:44:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Philipp Hug (Code Review) 07 Jul '18

07 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27397 to look at the new patch set (#3). Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... riscv: add trampoline in MBR block to support boot mode 1 Add "j pc + 0x1000" at the beginning of the MBR to jump to bootblock. Changed first usable LBA to 4 (0x1000) to prevent stack alignment issues. Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M util/riscv/sifive-gpt.py 1 file changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27397/3 -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Philipp Hug (Code Review) 07 Jul '18

07 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27397 to look at the new patch set (#2). Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... riscv: add trampoline in MBR block to support boot mode 1 Add "j pc + 0x1000" at the beginning of the MBR to jump to bootblock. Changed first usable LBA to 4 (0x1000) to prevent stack alignment issues. Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 --- M util/riscv/sifive-gpt.py 1 file changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27397/2 -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit July 2018