coreboot-gerrit July 2018

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Change in coreboot[master]: src/mb: Use "foo *bar" instead of "foo* bar"
by Elyes HAOUAS (Code Review) 08 Jul '18

08 Jul '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27406 Change subject: src/mb: Use "foo *bar" instead of "foo* bar" ...................................................................... src/mb: Use "foo *bar" instead of "foo* bar" Change-Id: Iedc2e48349e40e94863c8080d11e11dbe6084c9d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/kcma-d8/acpi_tables.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kgpe-d16/acpi_tables.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/supermicro/h8scm_fam10/acpi_tables.c 6 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/27406/1 diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c index c5f2c33..bd4d558 100644 --- a/src/mainboard/asus/kcma-d8/acpi_tables.c +++ b/src/mainboard/asus/kcma-d8/acpi_tables.c @@ -66,7 +66,7 @@ return current; } -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { uint8_t *p; diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 02dd671..3410762 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -247,7 +247,7 @@ uint32_t x; uint32_t y; uint32_t z; - uint32_t* dataptr; + uint32_t *dataptr; uint32_t readback; uint32_t start = 0x300000; printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); @@ -317,7 +317,7 @@ static spinlock_t printk_spinlock CAR_GLOBAL; -spinlock_t* romstage_console_lock(void) +spinlock_t *romstage_console_lock(void) { return car_get_var_ptr(&printk_spinlock); } @@ -329,7 +329,7 @@ static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL; -spinlock_t* romstage_nvram_cbfs_lock(void) +spinlock_t *romstage_nvram_cbfs_lock(void) { return car_get_var_ptr(&nvram_cbfs_spinlock); } @@ -341,7 +341,7 @@ static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL; -spinlock_t* romstage_microcode_cbfs_lock(void) +spinlock_t *romstage_microcode_cbfs_lock(void) { return car_get_var_ptr(&microcode_cbfs_spinlock); } diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c index c5f2c33..bd4d558 100644 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c @@ -66,7 +66,7 @@ return current; } -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { uint8_t *p; diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index f882bae..6188fcc 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -288,7 +288,7 @@ uint32_t x; uint32_t y; uint32_t z; - uint32_t* dataptr; + uint32_t *dataptr; uint32_t readback; uint32_t start = 0x300000; printk(BIOS_DEBUG, "Writing test pattern 1 to memory...\n"); @@ -358,7 +358,7 @@ static spinlock_t printk_spinlock CAR_GLOBAL; -spinlock_t* romstage_console_lock(void) +spinlock_t *romstage_console_lock(void) { return car_get_var_ptr(&printk_spinlock); } @@ -370,7 +370,7 @@ static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL; -spinlock_t* romstage_nvram_cbfs_lock(void) +spinlock_t *romstage_nvram_cbfs_lock(void) { return car_get_var_ptr(&nvram_cbfs_spinlock); } @@ -382,7 +382,7 @@ static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL; -spinlock_t* romstage_microcode_cbfs_lock(void) +spinlock_t *romstage_microcode_cbfs_lock(void) { return car_get_var_ptr(&microcode_cbfs_spinlock); } diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 1676fb0..9030698 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -28,7 +28,7 @@ #include "memory.c" -void * asmlinkage romstage_main(unsigned long bist) +void *asmlinkage romstage_main(unsigned long bist) { int cbmem_was_initted; diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index 165fd81..7305cf8 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -61,7 +61,7 @@ return current; } -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { uint8_t *p; -- To view, visit https://review.coreboot.org/27406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iedc2e48349e40e94863c8080d11e11dbe6084c9d Gerrit-Change-Number: 27406 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/{device, drivers}: Use "foo *bar" instead of "foo* bar"
by build bot (Jenkins) (Code Review) 08 Jul '18

08 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27404 ) Change subject: src/{device,drivers}: Use "foo *bar" instead of "foo* bar" ...................................................................... Patch Set 1: (36 comments) https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h File src/device/oprom/yabel/compat/of.h: https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 38: #define p32cast (int) (unsigned long) (void *) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 53: phandle_t of_peer(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 54: phandle_t of_child(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 55: phandle_t of_parent(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 60: ihandle_t of_open(const char *); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 67: void of_release(void *, unsigned int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 67: void of_release(void *, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 70: void *of_set_callback(void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/27404/1/src/device/oprom/yabel/compat/of.h@… PS1, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'unsigned short' should also have an identifier name -- To view, visit https://review.coreboot.org/27404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic1c9b1edd8d3206a68854107ddcbc5c51cb487c3 Gerrit-Change-Number: 27404 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 08 Jul 2018 10:38:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/{ec, include, lib}: Use "foo *bar" instead of "foo* bar"
by Elyes HAOUAS (Code Review) 08 Jul '18

08 Jul '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27405 Change subject: src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar" ...................................................................... src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar" Change-Id: I447aaa1850b7e8b514a8c4c04bf5b426d3d1cd0a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/crosec_proto.c M src/include/cpu/amd/car.h M src/lib/rtc.c 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/27405/1 diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index 1a8ffb9..2529854 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -24,7 +24,7 @@ #include "ec_message.h" /* Common utilities */ -void * __weak crosec_get_buffer(size_t size, int req) +void *__weak crosec_get_buffer(size_t size, int req) { printk(BIOS_DEBUG, "crosec_get_buffer() implementation required.\n"); return NULL; diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 288edb2..359fa6b 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -4,14 +4,14 @@ #include <arch/cpu.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -asmlinkage void * post_cache_as_ram(void); +asmlinkage void *post_cache_as_ram(void); asmlinkage void cache_as_ram_new_stack(void); void disable_cache_as_ram(void); void asmlinkage early_all_cores(void); -void * asmlinkage romstage_main(unsigned long bist); +void *asmlinkage romstage_main(unsigned long bist); void asmlinkage romstage_after_car(void); #endif diff --git a/src/lib/rtc.c b/src/lib/rtc.c index bd98590..c5c157f 100644 --- a/src/lib/rtc.c +++ b/src/lib/rtc.c @@ -31,7 +31,7 @@ 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 }; -static const char * const weekdays[] = { +static const char *const weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", }; -- To view, visit https://review.coreboot.org/27405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I447aaa1850b7e8b514a8c4c04bf5b426d3d1cd0a Gerrit-Change-Number: 27405 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/{device, drivers}: Use "foo *bar" instead of "foo* bar"
by Elyes HAOUAS (Code Review) 08 Jul '18

08 Jul '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27404 Change subject: src/{device,drivers}: Use "foo *bar" instead of "foo* bar" ...................................................................... src/{device,drivers}: Use "foo *bar" instead of "foo* bar" Change-Id: Ic1c9b1edd8d3206a68854107ddcbc5c51cb487c3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/device.c M src/device/oprom/include/x86emu/regs.h M src/device/oprom/yabel/compat/of.h M src/device/oprom/yabel/debug.c M src/device/oprom/yabel/debug.h M src/device/oprom/yabel/vbe.c M src/drivers/amd/agesa/oem_s3.c M src/drivers/amd/agesa/romstage.c M src/drivers/amd/agesa/state_machine.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/i2c/tpm/tpm.c M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/drivers/intel/fsp1_0/hob.c M src/drivers/intel/gma/edid.c M src/drivers/intel/i210/i210.c M src/drivers/pc80/tpm/tis.c M src/drivers/usb/ehci_debug.c M src/drivers/usb/gadget.c M src/drivers/xgi/common/xgi_coreboot.c 21 files changed, 67 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/27404/1 diff --git a/src/device/device.c b/src/device/device.c index 79dceaa..7ba9d0a 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -195,7 +195,7 @@ return val; } -static const char * resource2str(struct resource *res) +static const char *resource2str(struct resource *res) { if (res->flags & IORESOURCE_IO) return "io"; diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index 8eec112..51e9719 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -306,7 +306,7 @@ unsigned long mem_base; unsigned long mem_size; unsigned long abseg; - void* private; + void *private; X86EMU_regs x86; } X86EMU_sysEnv; diff --git a/src/device/oprom/yabel/compat/of.h b/src/device/oprom/yabel/compat/of.h index 31c9b59..ce910f7 100644 --- a/src/device/oprom/yabel/compat/of.h +++ b/src/device/oprom/yabel/compat/of.h @@ -35,7 +35,7 @@ #ifndef OF_H #define OF_H #define p32 int -#define p32cast (int) (unsigned long) (void*) +#define p32cast (int) (unsigned long) (void *) #define phandle_t p32 #define ihandle_t p32 @@ -50,27 +50,27 @@ phandle_t of_finddevice (const char *); -phandle_t of_peer (phandle_t); -phandle_t of_child (phandle_t); -phandle_t of_parent (phandle_t); -int of_getprop (phandle_t, const char *, void *, int); -void * of_call_method_3 (const char *, ihandle_t, int); +phandle_t of_peer(phandle_t); +phandle_t of_child(phandle_t); +phandle_t of_parent(phandle_t); +int of_getprop(phandle_t, const char *, void *, int); +void *of_call_method_3(const char *, ihandle_t, int); -ihandle_t of_open (const char *); +ihandle_t of_open(const char *); void of_close(ihandle_t); -int of_read (ihandle_t , void*, int); -int of_write (ihandle_t, void*, int); -int of_seek (ihandle_t, int, int); +int of_read(ihandle_t, void *, int); +int of_write(ihandle_t, void *, int); +int of_seek(ihandle_t, int, int); -void * of_claim(void *, unsigned int , unsigned int ); -void of_release(void *, unsigned int ); +void *of_claim(void *, unsigned int, unsigned int); +void of_release(void *, unsigned int); int of_yield(void); -void * of_set_callback(void *); +void *of_set_callback(void *); -int vpd_read(unsigned int , unsigned int , char *); -int vpd_write(unsigned int , unsigned int , char *); -int write_mm_log(char *, unsigned int , unsigned short ); +int vpd_read(unsigned int, unsigned int, char *); +int vpd_write(unsigned int, unsigned int, char *); +int write_mm_log(char *, unsigned int, unsigned short); #endif diff --git a/src/device/oprom/yabel/debug.c b/src/device/oprom/yabel/debug.c index daa263e..fc226fe 100644 --- a/src/device/oprom/yabel/debug.c +++ b/src/device/oprom/yabel/debug.c @@ -37,7 +37,7 @@ u32 debug_flags = 0; void -dump(u8 * addr, u32 len) +dump(u8 *addr, u32 len) { printf("\n%s(%p, %x):\n", __func__, addr, len); while (len) { diff --git a/src/device/oprom/yabel/debug.h b/src/device/oprom/yabel/debug.h index b1a8600..20db261 100644 --- a/src/device/oprom/yabel/debug.h +++ b/src/device/oprom/yabel/debug.h @@ -130,6 +130,6 @@ #endif //DEBUG -void dump(u8 * addr, u32 len); +void dump(u8 *addr, u32 len); #endif diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 5402ddf..c8b99d5 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -321,7 +321,7 @@ } static u8 -vbe_get_color(u16 color_number, u32 * color_value) +vbe_get_color(u16 color_number, u32 *color_value) { vbe_prepare(); // call VBE function 09h (Set/Get Palette Data Function) diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 1ca6e5b..ad193e1 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -161,5 +161,5 @@ if (!size) return NULL; - return (void*)(pos + sizeof(UINT32)); + return (void *)(pos + sizeof(UINT32)); } diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index c427927..90fa059 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -54,7 +54,7 @@ agesa_set_interface(cb); } -void * asmlinkage romstage_main(unsigned long bist) +void *asmlinkage romstage_main(unsigned long bist) { struct postcar_frame pcf; struct sysinfo romstage_state; diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index b73c124..673bf9b 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -53,7 +53,7 @@ image = LibAmdLocateImage(agesa, agesa + file_size, 4096, ModuleIdentifier); - StdHeader->ImageBasePtr = (void*) image; + StdHeader->ImageBasePtr = (void *) image; #endif } @@ -66,10 +66,10 @@ if (IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI)) { agesa_locate_image(&cb->StdHeader); AMD_IMAGE_HEADER *image = - (void*)(uintptr_t)cb->StdHeader.ImageBasePtr; + (void *)(uintptr_t)cb->StdHeader.ImageBasePtr; ASSERT(image); AMD_MODULE_HEADER *module = - (void*)(uintptr_t)image->ModuleInfoOffset; + (void *)(uintptr_t)image->ModuleInfoOffset; ASSERT(module && module->ModuleDispatcher); } } @@ -83,8 +83,8 @@ dispatcher = AmdAgesaDispatcher; #endif #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI) - AMD_IMAGE_HEADER *image = (void*)(uintptr_t)StdHeader->ImageBasePtr; - AMD_MODULE_HEADER *module = (void*)(uintptr_t)image->ModuleInfoOffset; + AMD_IMAGE_HEADER *image = (void *)(uintptr_t)StdHeader->ImageBasePtr; + AMD_MODULE_HEADER *module = (void *)(uintptr_t)image->ModuleInfoOffset; dispatcher = module->ModuleDispatcher; #endif diff --git a/src/drivers/aspeed/common/aspeed_coreboot.h b/src/drivers/aspeed/common/aspeed_coreboot.h index 5a208e6..b974840 100644 --- a/src/drivers/aspeed/common/aspeed_coreboot.h +++ b/src/drivers/aspeed/common/aspeed_coreboot.h @@ -73,7 +73,7 @@ }; static inline void *kzalloc(size_t size, int flags) { - void* ptr = malloc(size); + void *ptr = malloc(size); memset(ptr, 0, size); return ptr; } diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 7d69861..447fc24 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -65,7 +65,7 @@ UNKNOWN, }; -static const char * const chip_name[] = { +static const char *const chip_name[] = { [SLB9635] = "slb9635tt", [SLB9645] = "slb9645tt", [UNKNOWN] = "unknown/fallback to slb9635", diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index 906b356..76241c8 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -224,7 +224,7 @@ #endif /* !defined(__PRE_RAM__) */ -void * find_and_set_fastboot_cache(void) +void *find_and_set_fastboot_cache(void) { struct mrc_data_container *mrc_cache = NULL; if (((mrc_cache = find_current_mrc_cache()) == NULL) || diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index 5a6321d..c19c1a1 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -75,7 +75,7 @@ UPD_DATA_REGION fsp_upd_data; #endif - memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); + memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP; FspInitParams.NvsBufferPtr = NULL; @@ -100,7 +100,7 @@ } #endif /* __PRE_RAM__ */ -volatile u8 * find_fsp () +volatile u8 *find_fsp() { #ifdef __PRE_RAM__ @@ -175,7 +175,7 @@ * @param hob_list_ptr pointer to the start of the hob list * @return pointer to saved CAR MEM or NULL if not found. */ -void * find_saved_temp_mem(void *hob_list_ptr) +void *find_saved_temp_mem(void *hob_list_ptr) { EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; EFI_HOB_GUID_TYPE *saved_mem_hob = @@ -194,7 +194,7 @@ * @param hob_list_ptr pointer to the start of the hob list * @return pointer to the start of the FSP reserved memory or NULL if not found. */ -void * find_fsp_reserved_mem(void *hob_list_ptr) +void *find_fsp_reserved_mem(void *hob_list_ptr) { EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = @@ -221,7 +221,8 @@ } if (FspHobListPtr == NULL) { - FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER)); + FspHobListPtr = (void *)*((u32 *) + cbmem_find(CBMEM_ID_HOB_POINTER)); } printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr); @@ -294,7 +295,7 @@ static void find_fsp_hob_update_mrc(void *unused) { /* Set the global HOB list pointer */ - FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER)); + FspHobListPtr = (void *)*((u32 *) cbmem_find(CBMEM_ID_HOB_POINTER)); if (!FspHobListPtr){ printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n"); diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index a3a7dd3..594a259 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -22,10 +22,10 @@ #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) int save_mrc_data(void *hob_start); -void * find_and_set_fastboot_cache(void); +void *find_and_set_fastboot_cache(void); #endif -volatile u8 * find_fsp(void); +volatile u8 *find_fsp(void); void fsp_early_init(FSP_INFO_HEADER *fsp_info); void FspNotify(u32 Phase); void FspNotifyReturnPoint(EFI_STATUS Status, VOID *HobListPtr); @@ -34,16 +34,16 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); -void * find_saved_temp_mem(void *hob_list_ptr); -void * find_fsp_reserved_mem(void *hob_list_ptr); +void *find_saved_temp_mem(void *hob_list_ptr); +void *find_fsp_reserved_mem(void *hob_list_ptr); /* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); void print_hob_type_structure(u16 Hobtype, void *Hoblistptr); void print_hob_resource_attributes(void *Hobptr); void print_guid_type_attributes(void *Hobptr); -const char * get_hob_type_string(void *Hobptr); -void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1); +const char *get_hob_type_string(void *Hobptr); +void *find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1); uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2); void printguid(EFI_GUID *guid); @@ -90,10 +90,10 @@ #define FSP_SIG 0x48505346 /* 'FSPH' */ #define ERROR_NO_FV_SIG 1 -#define ERROR_NO_FFS_GUID 2 +#define ERROR_NO_FFS_GUID 2 #define ERROR_NO_INFO_HEADER 3 #define ERROR_IMAGEBASE_MISMATCH 4 -#define ERROR_INFO_HEAD_SIG_MISMATCH 5 +#define ERROR_INFO_HEAD_SIG_MISMATCH 5 #define ERROR_FSP_SIG_MISMATCH 6 #ifndef __PRE_RAM__ diff --git a/src/drivers/intel/fsp1_0/hob.c b/src/drivers/intel/fsp1_0/hob.c index 1c6d0bb..9334893 100644 --- a/src/drivers/intel/fsp1_0/hob.c +++ b/src/drivers/intel/fsp1_0/hob.c @@ -42,7 +42,7 @@ EFI_MEMORY_TYPE Hobmemtype = HobMemoryPtr->AllocDescriptor.MemoryType; u64 Hobmemaddr = HobMemoryPtr->AllocDescriptor.MemoryBaseAddress; u64 Hobmemlength = HobMemoryPtr->AllocDescriptor.MemoryLength; - const char * Hobmemtypenames[15]; + const char *Hobmemtypenames[15]; Hobmemtypenames[0] = "EfiReservedMemoryType"; Hobmemtypenames[1] = "EfiLoaderCode"; @@ -104,7 +104,7 @@ (unsigned long)Hobresaddr, (unsigned long)Hobreslength); } -const char * get_hob_type_string(void *Hobptr) +const char *get_hob_type_string(void *Hobptr) { EFI_HOB_GENERIC_HEADER *HobHeaderPtr = (EFI_HOB_GENERIC_HEADER *)Hobptr; u16 Hobtype = HobHeaderPtr->HobType; @@ -215,7 +215,7 @@ * @param guid the GUID of the HOB entry to find * @return pointer to the start of the requested HOB or NULL if not found. */ -void * find_hob_by_guid(void *current_hob, EFI_GUID *guid) +void *find_hob_by_guid(void *current_hob, EFI_GUID *guid) { do { switch (((EFI_HOB_GENERIC_HEADER *)current_hob)->HobType) { @@ -255,8 +255,8 @@ */ uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2) { - uint64_t* guid_1 = (void *) guid1; - uint64_t* guid_2 = (void *) guid2; + uint64_t *guid_1 = (void *) guid1; + uint64_t *guid_2 = (void *) guid2; if ((*(guid_1) != *(guid_2)) || (*(guid_1 + 1) != *(guid_2 + 1))) return 0; diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 316e869..13b301f 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -39,7 +39,7 @@ } } -static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) +static void intel_gmbus_stop_bus(u8 *mmio, u8 bus) { wait_rdy(mmio); write32(GMBUS0_ADDR, bus); diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 2eae6a9..32d27f7 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -26,7 +26,7 @@ /* This is a private function to wait for a bit mask in a given register */ /* To avoid endless loops, a time-out is implemented here. */ -static int wait_done(uint32_t* reg, uint32_t mask) +static int wait_done(uint32_t *reg, uint32_t mask) { uint32_t timeout = I210_POLL_TIMEOUT_US; @@ -58,7 +58,7 @@ bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); if ((!bar) || ((address + count) > 0x40)) return I210_INVALID_PARAM; - eeprd = (uint32_t*)(bar + I210_REG_EEREAD); + eeprd = (uint32_t *)(bar + I210_REG_EEREAD); /* Prior to start ensure flash interface is ready by checking DONE-bit */ if (wait_done(eeprd, I210_DONE)) return I210_NOT_READY; @@ -122,8 +122,8 @@ bar = pci_read_config32(dev, 0x10); if ((!bar) || ((address + count) > 0x40)) return I210_INVALID_PARAM; - eepwr = (uint32_t*)(bar + I210_REG_EEWRITE); - eectrl = (uint32_t*)(bar + I210_REG_EECTRL); + eepwr = (uint32_t *)(bar + I210_REG_EEWRITE); + eectrl = (uint32_t *)(bar + I210_REG_EECTRL); /* Prior to start ensure flash interface is ready by checking DONE-bit */ if (wait_done(eepwr, I210_DONE)) return I210_NOT_READY; @@ -166,7 +166,7 @@ return I210_READ_ERROR; /* Copy the address into destination. This is done because of possible */ /* not matching alignment for destination to uint16_t boundary. */ - memcpy(mac_adr, (uint8_t*)adr, 6); + memcpy(mac_adr, (uint8_t *)adr, 6); return I210_SUCCESS; } @@ -181,7 +181,7 @@ if (!dev || !mac_adr) return I210_INVALID_PARAM; /* Copy desired address into a local buffer to avoid alignment issues */ - memcpy((uint8_t*)adr, mac_adr, 6); + memcpy((uint8_t *)adr, mac_adr, 6); return write_flash(dev, 0, 3, adr); } diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 3549173..495bb4a 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -109,13 +109,13 @@ */ struct device_name { u16 dev_id; - const char * const dev_name; + const char *const dev_name; }; struct vendor_name { u16 vendor_id; - const char * vendor_name; - const struct device_name* dev_names; + const char *vendor_name; + const struct device_name *dev_names; }; static const struct device_name atmel_devices[] = { @@ -443,7 +443,7 @@ * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does * not accept the entire command). */ -static u32 tis_senddata(const u8 * const data, u32 len) +static u32 tis_senddata(const u8 *const data, u32 len) { u32 offset = 0; u16 burst = 0; diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index fcc5223..52b4bdd 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -631,7 +631,7 @@ diff = (unsigned)dbg_info->ehci_base - ehci_base; dbg_info->ehci_debug -= diff; - dbg_info->ehci_base = (void*)ehci_base; + dbg_info->ehci_base = (void *)ehci_base; for (i=0; i<DBGP_MAX_ENDPOINTS; i++) if (dbg_info->ep_pipe[i].status & DBGP_EP_VALID) diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index 37e97a3..3254a8a 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -29,7 +29,7 @@ #define USB_HUB_C_PORT_RESET 20 -static int hub_port_status(const char * buf, int feature) +static int hub_port_status(const char *buf, int feature) { return !!(buf[feature>>3] & (1<<(feature&0x7))); } diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index 9cd634c..47320fd 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -130,8 +130,9 @@ hw_info->ulVideoMemorySize = xgifb_info->video_size; - xgifb_info->video_vbase = hw_info->pjVideoMemoryAddress = (void*)(intptr_t)xgifb_info->video_base; - xgifb_info->mmio_vbase = (void*)(intptr_t)xgifb_info->mmio_base; + xgifb_info->video_vbase = hw_info->pjVideoMemoryAddress = + (void *)(intptr_t)xgifb_info->video_base; + xgifb_info->mmio_vbase = (void *)(intptr_t)xgifb_info->mmio_base; dev_info(&pdev->dev, "Framebuffer at 0x%Lx, mapped to 0x%p, size %dk\n", -- To view, visit https://review.coreboot.org/27404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic1c9b1edd8d3206a68854107ddcbc5c51cb487c3 Gerrit-Change-Number: 27404 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/{arch, commonlib, cpu}: Use "foo *bar" instead of "foo* bar"
by build bot (Jenkins) (Code Review) 08 Jul '18

08 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26942 ) Change subject: src/{arch,commonlib,cpu}: Use "foo *bar" instead of "foo* bar" ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/26942/15/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/26942/15/src/cpu/amd/family_10h-family_15h/… PS15, Line 380: void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); line over 80 characters -- To view, visit https://review.coreboot.org/26942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Gerrit-Change-Number: 26942 Gerrit-PatchSet: 15 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 08 Jul 2018 10:33:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Philipp Hug (Code Review) 07 Jul '18

07 Jul '18

Hello Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27397 to look at the new patch set (#7). Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... riscv: add trampoline in MBR block to support boot mode 1 Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit. Further changes are needed in the bootblock Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M Documentation/mainboard/sifive/hifive-unleashed.md M util/riscv/sifive-gpt.py 2 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27397/7 -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 7 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Philipp Hug (Code Review) 07 Jul '18

07 Jul '18

Hello Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27397 to look at the new patch set (#6). Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... riscv: add trampoline in MBR block to support boot mode 1 Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Tested on hardware: boot mode 15: works as before boot mode 1: jump to bootblock works, but bootblock needs to be modified to move the stack to L2LIM. This will be in a separate commit. Further changes are needed in the bootblock Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M Documentation/mainboard/sifive/hifive-unleashed.md M util/riscv/sifive-gpt.py 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27397/6 -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Philipp Hug (Code Review) 07 Jul '18

07 Jul '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/27397 ) Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... Patch Set 5: I dropped the change of the bootblock. I'll have a look at the linker scripts / bootblock.S to always put the stack on L2LIM. If that doesn't work I'll revert to the copy to L2LIM approach which I wanted to avoid. Tested on hardware: boot mode 15: works as before boot mode 1: still doesn't work as more changes are needed -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Jul 2018 14:09:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Jonathan Neuschäfer (Code Review) 07 Jul '18

07 Jul '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27397 ) Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/27397/5//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/27397/5//COMMIT_MSG@10 PS5, Line 10: Please mention here (in the commit message) to which extend this has been tested and works. -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Jul 2018 14:06:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Philipp Hug (Code Review) 07 Jul '18

07 Jul '18

Hello Jonathan Neuschäfer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27397 to look at the new patch set (#5). Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... riscv: add trampoline in MBR block to support boot mode 1 Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock. Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M Documentation/mainboard/sifive/hifive-unleashed.md M util/riscv/sifive-gpt.py 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27397/5 -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit July 2018