coreboot-gerrit July 2018

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Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1
by Philipp Hug (Code Review) 07 Jul '18

07 Jul '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/27397 Change subject: riscv: add trampoline in MBR block to support boot mode 1 ...................................................................... riscv: add trampoline in MBR block to support boot mode 1 Add "J pc + 0x1000" at the beginning of the MBR to jump to bootlock. Changed first usable lba to 4 (0x1000) as prevent stack alignment issues. Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 --- M util/riscv/sifive-gpt.py 1 file changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27397/1 diff --git a/util/riscv/sifive-gpt.py b/util/riscv/sifive-gpt.py index cb77302..2619a21 100755 --- a/util/riscv/sifive-gpt.py +++ b/util/riscv/sifive-gpt.py @@ -25,6 +25,12 @@ # Size of the bootcode part of the MBR MBR_BOOTCODE_SIZE = 0x1be +# MBR trampoline to bootblock +MBR_BOOTCODE = bytes([ + # j pc + 0x1000 + 0x6f, 0x10, 0x00, 0x00, +]) + # A protecive MBR, without the bootcode part PROTECTIVE_MBR_FOOTER = bytes([ 0x00, 0x00, 0x02, 0x00, 0xee, 0xff, 0xff, 0xff, @@ -43,7 +49,7 @@ # [1]: https://en.wikipedia.org/wiki/GUID_Partition_Table#PROTECTIVE-MBR class ProtectiveMBR: def __init__(self): - self.bootcode = bytes(MBR_BOOTCODE_SIZE) + self.bootcode = MBR_BOOTCODE + bytes(MBR_BOOTCODE_SIZE - len(MBR_BOOTCODE)) def generate(self, stream): assert len(self.bootcode) == MBR_BOOTCODE_SIZE @@ -71,7 +77,7 @@ def __init__(self): self.current_lba = 1 self.backup_lba = 1 - self.first_usable_lba = 2 + self.first_usable_lba = 8 # hard-coded to match jump self.last_usable_lba = 0xff # dummy value self.uniq = DUMMY_GUID_DISK_UNIQUE self.part_entries_lba = 2 @@ -126,7 +132,7 @@ def __init__(self): self.mbr = ProtectiveMBR() self.header = GPTHeader() - self.partitions = [ GPTPartition() for i in range(8) ] + self.partitions = [ GPTPartition() for i in range(24) ] self.bootblock = b'' @@ -137,10 +143,6 @@ bootblock_size = (len(self.bootblock) + BLOCK_SIZE - 1) & ~BLOCK_MASK self.bootblock = self.bootblock.ljust(bootblock_size) - # Propagate the number of partition entries - self.header.part_entries_number = len(self.partitions) - self.header.first_usable_lba = 2 + self.header.part_entries_number // 4 - # Create a partition entry for the bootblock self.partitions[0].type = GUID_TYPE_FSBL self.partitions[0].uniq = DUMMY_GUID_PART_UNIQUE -- To view, visit https://review.coreboot.org/27397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86 Gerrit-Change-Number: 27397 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: src: Use "foo *bar" instead of "foo* bar"
by build bot (Jenkins) (Code Review) 07 Jul '18

07 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26942 ) Change subject: src: Use "foo *bar" instead of "foo* bar" ...................................................................... Patch Set 14: (73 comments) https://review.coreboot.org/#/c/26942/14/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/26942/14/src/cpu/amd/family_10h-family_15h/… PS14, Line 380: void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); line over 80 characters https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h File src/device/oprom/yabel/compat/of.h: https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 38: #define p32cast (int) (unsigned long) (void *) Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 53: phandle_t of_peer(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 54: phandle_t of_child(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 55: phandle_t of_parent(phandle_t); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'phandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 56: int of_getprop(phandle_t, const char *, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 57: void *of_call_method_3(const char *, ihandle_t, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 60: ihandle_t of_open(const char *); function definition argument 'const char *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 62: int of_read(ihandle_t, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 63: int of_write(ihandle_t, void *, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'ihandle_t' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 64: int of_seek(ihandle_t, int, int); function definition argument 'int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 66: void *of_claim(void *, unsigned int, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 67: void of_release(void *, unsigned int); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 67: void of_release(void *, unsigned int); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 70: void *of_set_callback(void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 72: int vpd_read(unsigned int, unsigned int, char *); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 73: int vpd_write(unsigned int, unsigned int, char *); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'char *' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'unsigned int' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/device/oprom/yabel/compat/of.h… PS14, Line 74: int write_mm_log(char *, unsigned int, unsigned short); function definition argument 'unsigned short' should also have an identifier name https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/mct_d.h: https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 1058: void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 1059: void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 1136: void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c: https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 320: static void read_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 349: static void write_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c: https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 258: void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 285: static void write_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 317: static void write_write_data_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 356: void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 390: void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 427: static void read_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 459: static void write_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 497: void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 531: void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 272: static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t *restored) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 306: void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_data) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 329: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 597: void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only) line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 611: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 655: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 666: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 722: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 761: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 826: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 871: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 912: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 929: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 967: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 986: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 1013: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 1037: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 1069: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/northbridge/amd/amdmct/mct_ddr… PS14, Line 1084: struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; line over 80 characters https://review.coreboot.org/#/c/26942/14/src/southbridge/amd/sr5650/sr5650.c File src/southbridge/amd/sr5650/sr5650.c: https://review.coreboot.org/#/c/26942/14/src/southbridge/amd/sr5650/sr5650.… PS14, Line 35: struct resource *sr5650_retrieve_cpu_mmio_resource() { open brace '{' following function declarations go on the next line https://review.coreboot.org/#/c/26942/14/src/southbridge/intel/i82870/ioapi… File src/southbridge/intel/i82870/ioapic.c: https://review.coreboot.org/#/c/26942/14/src/southbridge/intel/i82870/ioapi… PS14, Line 47: volatile uint32_t *pIndexRegister; /* io apic io memory space command address */ line over 80 characters https://review.coreboot.org/#/c/26942/14/src/southbridge/intel/i82870/ioapi… PS14, Line 48: volatile uint32_t *pWindowRegister; /* io apic io memory space data address */ line over 80 characters -- To view, visit https://review.coreboot.org/26942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8e4118c5c5d70719ad7dc5f9ff9f86d93fa498ac Gerrit-Change-Number: 26942 Gerrit-PatchSet: 14 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Jul 2018 06:55:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src: Use "foo *bar" instead of "foo* bar"
by build bot (Jenkins) (Code Review) 07 Jul '18

07 Jul '18

1 0

Change in coreboot[master]: ec/roda: pass ops to pnp_enable_devices instead of LDN-specific override
by Felix Held (Code Review) 07 Jul '18

07 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27396 Change subject: ec/roda: pass ops to pnp_enable_devices instead of LDN-specific override ...................................................................... ec/roda: pass ops to pnp_enable_devices instead of LDN-specific override Change-Id: Ic35a232a9867936d3d84aa275ae50e3e3dd9bf97 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/ec/roda/it8518/ec.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27396/1 diff --git a/src/ec/roda/it8518/ec.c b/src/ec/roda/it8518/ec.c index 99ce506..4e69d11 100644 --- a/src/ec/roda/it8518/ec.c +++ b/src/ec/roda/it8518/ec.c @@ -53,13 +53,12 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, 0, } + { NULL, 0, 0, 0, } }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations ec_roda_it8518_ops = { -- To view, visit https://review.coreboot.org/27396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic35a232a9867936d3d84aa275ae50e3e3dd9bf97 Gerrit-Change-Number: 27396 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: ec/quanta: pass ops to pnp_enable_devices instead of LDN-specific ove...
by Felix Held (Code Review) 07 Jul '18

07 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27395 Change subject: ec/quanta: pass ops to pnp_enable_devices instead of LDN-specific override ...................................................................... ec/quanta: pass ops to pnp_enable_devices instead of LDN-specific override Change-Id: I59eb60efeefcdbe8b2dc08e17453cf95bdfd39b1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/27395/1 diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index b25a51b..11a1cb8 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -154,13 +154,12 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, 0, } + { NULL, 0, 0, 0, } }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations ec_quanta_ene_kb3940q_ops = { diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 3a51733..e293f7c 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -167,13 +167,12 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, 0, } + { NULL, 0, 0, 0, } }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations ec_quanta_it8518_ops = { -- To view, visit https://review.coreboot.org/27395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I59eb60efeefcdbe8b2dc08e17453cf95bdfd39b1 Gerrit-Change-Number: 27395 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: ec/google: pass ops to pnp_enable_devices instead of LDN-specific ove...
by Felix Held (Code Review) 07 Jul '18

07 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27394 Change subject: ec/google: pass ops to pnp_enable_devices instead of LDN-specific override ...................................................................... ec/google: pass ops to pnp_enable_devices instead of LDN-specific override Change-Id: Id09c6cffb9a0cbbd9189c18801121449c9504422 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/ec/google/chromeec/ec_lpc.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/27394/1 diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 1700bd6..f584630 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -465,13 +465,12 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, 0, } + { NULL, 0, 0, 0, } }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations ec_google_chromeec_ops = { -- To view, visit https://review.coreboot.org/27394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id09c6cffb9a0cbbd9189c18801121449c9504422 Gerrit-Change-Number: 27394 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: ec/compal: pass ops to pnp_enable_devices instead of LDN-specific ove...
by Felix Held (Code Review) 07 Jul '18

07 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27393 Change subject: ec/compal: pass ops to pnp_enable_devices instead of LDN-specific override ...................................................................... ec/compal: pass ops to pnp_enable_devices instead of LDN-specific override Change-Id: I10e2c6da0043eb291a8c6266b251054dbe599653 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/ec/compal/ene932/ec.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/27393/1 diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 1ed3c9f..7d8880c 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -144,13 +144,12 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, 0, } + { NULL, 0, 0, 0, } }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations ec_compal_ene932_ops = { -- To view, visit https://review.coreboot.org/27393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I10e2c6da0043eb291a8c6266b251054dbe599653 Gerrit-Change-Number: 27393 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: sio/smsc/fdc37n972: add missing pnp_conf_mode field to ops struct
by Felix Held (Code Review) 07 Jul '18

07 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27392 to look at the new patch set (#2). Change subject: sio/smsc/fdc37n972: add missing pnp_conf_mode field to ops struct ...................................................................... sio/smsc/fdc37n972: add missing pnp_conf_mode field to ops struct This patch makes it possible to enter the config mode of the super IO chip, so that changes can be made to the configuration registers. Change-Id: I7e31eaf217b3af2226c1e7d2f14f2ef7b0d7ddbe Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/smsc/fdc37n972/superio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/27392/2 -- To view, visit https://review.coreboot.org/27392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e31eaf217b3af2226c1e7d2f14f2ef7b0d7ddbe Gerrit-Change-Number: 27392 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sio/smsc/fdc37n972: add missing pnp_conf_mode field to ops struct
by Felix Held (Code Review) 06 Jul '18

06 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27392 Change subject: sio/smsc/fdc37n972: add missing pnp_conf_mode field to ops struct ...................................................................... sio/smsc/fdc37n972: add missing pnp_conf_mode field to ops struct This patch makes it possible to enter the config mode of the super IO chip, so that changes can be made to the configuration registers. Change-Id: I7e31eaf217b3af2226c1e7d2f14f2ef7b0d7ddbe Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/smsc/fdc37n972/superio.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/27392/1 diff --git a/src/superio/smsc/fdc37n972/superio.c b/src/superio/smsc/fdc37n972/superio.c index 85e376d..e9e8043 100644 --- a/src/superio/smsc/fdc37n972/superio.c +++ b/src/superio/smsc/fdc37n972/superio.c @@ -43,6 +43,7 @@ .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/27392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e31eaf217b3af2226c1e7d2f14f2ef7b0d7ddbe Gerrit-Change-Number: 27392 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: superio/via: remove LDN-specific ops overrides
by Felix Held (Code Review) 06 Jul '18

06 Jul '18

Felix Held has uploaded this change for review. ( https://review.coreboot.org/27391 Change subject: superio/via: remove LDN-specific ops overrides ...................................................................... superio/via: remove LDN-specific ops overrides The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I14dbeda9832a25116cf53c36197615e9d02d5134 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/via/vt1211/superio.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/27391/1 diff --git a/src/superio/via/vt1211/superio.c b/src/superio/via/vt1211/superio.c index 28586ba..3468b63 100644 --- a/src/superio/via/vt1211/superio.c +++ b/src/superio/via/vt1211/superio.c @@ -167,18 +167,18 @@ /* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ static struct pnp_info pnp_dev_info[] = { - { &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, - { &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, 0xfffc, }, - { &ops, VT1211_GAME, PNP_IO0, 0xfff8, }, - { &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, - { &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, 0xff00, }, - { &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xff00, }, - { &ops, VT1211_ROM, }, + { NULL, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, VT1211_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, VT1211_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, + { NULL, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, 0xfffc, }, + { NULL, VT1211_GAME, PNP_IO0, 0xfff8, }, + { NULL, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, VT1211_WDG, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, VT1211_WUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, VT1211_HWM, PNP_IO0 | PNP_IRQ0, 0xff00, }, + { NULL, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xff00, }, + { NULL, VT1211_ROM, }, }; static void enable_dev(struct device *dev) -- To view, visit https://review.coreboot.org/27391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I14dbeda9832a25116cf53c36197615e9d02d5134 Gerrit-Change-Number: 27391 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit July 2018