coreboot-gerrit July 2018

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Change in coreboot[master]: mb/google/poppy:[WIP] Add RW_UCODE_STAGED region
by Rizwan Qureshi (Code Review) 06 Jul '18

06 Jul '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/27366 Change subject: mb/google/poppy:[WIP] Add RW_UCODE_STAGED region ...................................................................... mb/google/poppy:[WIP] Add RW_UCODE_STAGED region Add a 128K region RW_UCODE_STAGED, which will hold the rw microcode which inturn will be referenced by the FIT in top swap bootblock Change-Id: If275b3014bfb679bae980e4238e6a428f06c6e32 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/poppy/chromeos.fmd 1 file changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/27366/1 diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd index bdadcf7..faf50e2 100644 --- a/src/mainboard/google/poppy/chromeos.fmd +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -14,20 +14,22 @@ FW_MAIN_B(CBFS)@0x10000 0x3d7fc0 RW_FWID_B@0x3e7fc0 0x40 } - RW_MISC@0x7d0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x7d0000 0x51000 { + RW_UCODE_STAGED@0x0 0x20000 + UNIFIED_MRC_CACHE@0x20000 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { + RW_ELOG@0x40000 0x4000 + RW_SHARED@0x44000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 + RW_VPD@0x48000 0x2000 + RW_NVRAM@0x4a000 0x6000 + RW_UPDATE_STATE@0x50000 0x1000 } - RW_LEGACY(CBFS)@0x800000 0x200000 + RW_LEGACY(CBFS)@0x821000 0x1DF000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 -- To view, visit https://review.coreboot.org/27366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If275b3014bfb679bae980e4238e6a428f06c6e32 Gerrit-Change-Number: 27366 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: cpu/intel/microcode:[WIP] Add helper functions
by Rizwan Qureshi (Code Review) 06 Jul '18

06 Jul '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/27365 Change subject: cpu/intel/microcode:[WIP] Add helper functions ...................................................................... cpu/intel/microcode:[WIP] Add helper functions Add 4 helper functions: * get_current_microcode_rev return the the version of the currently running microcode. * get_microcode_rev extract microcode revision from the given patch. * get_microcode_size extract microcode size from the given patch. * get_microcode_checksum extract checksum from the given patch. Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/cpu/intel/microcode/microcode.c M src/include/cpu/intel/microcode.h 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27365/1 diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 272edb5..8cfcb95 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -113,6 +113,26 @@ #endif } +uint32_t get_current_microcode_rev(void) +{ + return read_microcode_rev(); +} + +uint32_t get_microcode_rev(const void *microcode) +{ + return ((struct microcode *)microcode)->rev; +} + +uint32_t get_microcode_size(const void *microcode) +{ + return ((struct microcode *)microcode)->total_size; +} + +uint32_t get_microcode_checksum(const void *microcode) +{ + return ((struct microcode *)microcode)->cksum; +} + const void *intel_microcode_find(void) { const struct microcode *ucode_updates; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 0783ace..9170c02 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -31,4 +31,13 @@ * required, will skip microcode update if true. */ int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id); +/* return the the version of the currently running microcode */ +uint32_t get_current_microcode_rev(void); + +/* extract microcode revision from the given patch */ +uint32_t get_microcode_rev(const void *microcode); +/* extract microcode size from the given patch */ +uint32_t get_microcode_size(const void *microcode); +/* extract checksum from the given patch */ +uint32_t get_microcode_checksum(const void *microcode); #endif -- To view, visit https://review.coreboot.org/27365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3 Gerrit-Change-Number: 27365 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: mb/{asus, getac, gigabyte, kontron}: Remove unneeded includes
by Elyes HAOUAS (Code Review) 06 Jul '18

06 Jul '18

Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/27364 ) Change subject: mb/{asus,getac,gigabyte,kontron}: Remove unneeded includes ...................................................................... mb/{asus,getac,gigabyte,kontron}: Remove unneeded includes Change-Id: I301affabb4199a7177fc0cb7698d7540a756037f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/kontron/ktqm77/romstage.c 8 files changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/27364/2 -- To view, visit https://review.coreboot.org/27364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I301affabb4199a7177fc0cb7698d7540a756037f Gerrit-Change-Number: 27364 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/{asus, getac, gigabyte, kontron}: Remoce unneeded includes
by Elyes HAOUAS (Code Review) 06 Jul '18

06 Jul '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27364 Change subject: mb/{asus,getac,gigabyte,kontron}: Remoce unneeded includes ...................................................................... mb/{asus,getac,gigabyte,kontron}: Remoce unneeded includes Change-Id: I301affabb4199a7177fc0cb7698d7540a756037f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/kontron/ktqm77/romstage.c 8 files changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/27364/1 diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index e1725d0..7d84f29 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -18,18 +18,13 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> -#include <string.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <lib.h> -#include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index e58ef1b..289768b 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -15,15 +15,10 @@ */ #include <stdint.h> -#include <string.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <lib.h> -#include <arch/acpi.h> -#include <cbmem.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 926a5a7..5a6b5fb 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -17,18 +17,13 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> -#include <string.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <lib.h> -#include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c index 90131ff..3156a23 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -16,21 +16,9 @@ */ #include <types.h> -#include <string.h> #include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <cbfs.h> static void mainboard_init(struct device *dev) { diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index cc32b99..f341b4e 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> #include <arch/io.h> #include <arch/interrupt.h> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index f7e8131..f5af574 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -16,16 +16,11 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> -#include <string.h> -#include <lib.h> -#include <arch/acpi.h> -#include <cbmem.h> #include <timestamp.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> #include "option_table.h" #include <console/console.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 3a37290..f25fb89 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -16,7 +16,6 @@ */ #include <types.h> -#include <string.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -24,8 +23,6 @@ #if IS_ENABLED(CONFIG_VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 2a674a5..894f161 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -15,24 +15,16 @@ */ #include <stdint.h> -#include <string.h> -#include <lib.h> #include <timestamp.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <cbmem.h> -#include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <halt.h> void pch_enable_lpc(void) -- To view, visit https://review.coreboot.org/27364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I301affabb4199a7177fc0cb7698d7540a756037f Gerrit-Change-Number: 27364 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src: Add missing license headers
by Werner Zeh (Code Review) 06 Jul '18

06 Jul '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/27362 ) Change subject: src: Add missing license headers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I464ddecb5eebe8c5b907f3dcfeab1b06501af6ab Gerrit-Change-Number: 27362 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Jul 2018 04:23:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: payloads/seabios: Update stable from 1.11.1 to 1.11.2
by Philipp Deppenwiese (Code Review) 06 Jul '18

06 Jul '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/27326 ) Change subject: payloads/seabios: Update stable from 1.11.1 to 1.11.2 ...................................................................... payloads/seabios: Update stable from 1.11.1 to 1.11.2 SeaBIOS 1.11.2 was tagged with the following changes: ``` f9626cc cbvga_set_mode: refine clear display logic f88297a qemu: add qemu ramfb support a2e4001 vgasrc: add allocate_pmm() 17b01f4 pmm: use tmp zone on oom 44b17d0 bochs_display_setup: return error on failure 4ba61fa cbvga_set_mode: disable clearmem in windows x86 emulator. dd69189 cbvga_list_modes: don't list current mode twice 5f0e7c9 cbvga_setup_modes: use real mode number instead of 0x140 961f67c qemu: add bochs-display support 767365e cbvga: factor out cbvga_setup_modes() 7906460 optionrom: enable non-vga display devices ``` Tested by running it on a Thinkpad X230. Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> Tested-by: Martin Kepplinger <martink(a)posteo.de> Reviewed-on: https://review.coreboot.org/27326 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/external/SeaBIOS/Kconfig M payloads/external/SeaBIOS/Makefile 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 63f91d6..52dc738 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.11.1" + bool "1.11.2" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index 7058a8d..4e2ecbd 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=0551a4be2ce599fb60e478b4c15e06ab6587822c +TAG-$(CONFIG_SEABIOS_STABLE)=f9626ccb91e771f990fbb2da92e427a399d7d918 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git -- To view, visit https://review.coreboot.org/27326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0 Gerrit-Change-Number: 27326 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: payloads/seabios: Update stable from 1.11.1 to 1.11.2
by Philipp Deppenwiese (Code Review) 06 Jul '18

06 Jul '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27326 ) Change subject: payloads/seabios: Update stable from 1.11.1 to 1.11.2 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/27326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0 Gerrit-Change-Number: 27326 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kevin O'Connor <kevin(a)koconnor.net> Gerrit-Reviewer: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Jul 2018 01:20:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Add missing license headers
by Martin Roth (Code Review) 06 Jul '18

06 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27362 Change subject: src: Add missing license headers ...................................................................... src: Add missing license headers These two files were added before I was able to get the updated linter committed. Updated/Add the headers so the stable header lint check can be updated. Change-Id: I464ddecb5eebe8c5b907f3dcfeab1b06501af6ab Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/lenovo/t530/gma-mainboard.ads M src/security/vboot/antirollback.h 2 files changed, 42 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/27362/1 diff --git a/src/mainboard/lenovo/t530/gma-mainboard.ads b/src/mainboard/lenovo/t530/gma-mainboard.ads index 736dce7..d4a5d7d 100644 --- a/src/mainboard/lenovo/t530/gma-mainboard.ads +++ b/src/mainboard/lenovo/t530/gma-mainboard.ads @@ -1,3 +1,17 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index be42f00..6ea2c13 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -1,7 +1,33 @@ /* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following disclaimer + * in the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google Inc. nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* * Functions for querying, manipulating and locking rollback indices * stored in the TPM NVRAM. */ -- To view, visit https://review.coreboot.org/27362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I464ddecb5eebe8c5b907f3dcfeab1b06501af6ab Gerrit-Change-Number: 27362 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: [WIP]util/autoport: Change the order in which chips and PCI devices a...
by Arthur Heymans (Code Review) 05 Jul '18

05 Jul '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27361 Change subject: [WIP]util/autoport: Change the order in which chips and PCI devices are added ...................................................................... [WIP]util/autoport: Change the order in which chips and PCI devices are added That way pci0.0-2.0 are places above chip southbridge/intel/bd82x6x Change-Id: Ib4c7c43dd209678aa3d37fe75a8d010192ae2803 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/autoport/main.go 1 file changed, 28 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/27361/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index 3071559..b039631 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -290,34 +290,6 @@ } for _, slot := range dev.PCISlots { - slotChip, ok := unmatchedPCIChips[slot.PCIAddr] - - if !ok { - continue - } - - if slot.additionalComment != "" && slotChip.Comment != "" { - slotChip.Comment = slot.additionalComment + " " + slotChip.Comment - } else { - slotChip.Comment = slot.additionalComment + slotChip.Comment - } - - delete(unmatchedPCIChips, slot.PCIAddr) - MatchDev(&slotChip) - dev.Children = append(dev.Children, slotChip) - } - - if dev.PCIController { - for slot, slotDev := range unmatchedPCIChips { - if slot.Bus == dev.ChildPCIBus { - delete(unmatchedPCIChips, slot) - MatchDev(&slotDev) - dev.Children = append(dev.Children, slotDev) - } - } - } - - for _, slot := range dev.PCISlots { slotDev, ok := unmatchedPCIDevices[slot.PCIAddr] if !ok { if slot.writeEmpty { @@ -355,6 +327,34 @@ delete(MissingChildren, dev.MissingParent) } + for _, slot := range dev.PCISlots { + slotChip, ok := unmatchedPCIChips[slot.PCIAddr] + + if !ok { + continue + } + + if slot.additionalComment != "" && slotChip.Comment != "" { + slotChip.Comment = slot.additionalComment + " " + slotChip.Comment + } else { + slotChip.Comment = slot.additionalComment + slotChip.Comment + } + + delete(unmatchedPCIChips, slot.PCIAddr) + MatchDev(&slotChip) + dev.Children = append(dev.Children, slotChip) + } + + if dev.PCIController { + for slot, slotDev := range unmatchedPCIChips { + if slot.Bus == dev.ChildPCIBus { + delete(unmatchedPCIChips, slot) + MatchDev(&slotDev) + dev.Children = append(dev.Children, slotDev) + } + } + } + if dev.PCIController { for slot, slotDev := range unmatchedPCIDevices { if slot.Bus == dev.ChildPCIBus { -- To view, visit https://review.coreboot.org/27361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4c7c43dd209678aa3d37fe75a8d010192ae2803 Gerrit-Change-Number: 27361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock...
by Piotr Król (Code Review) 05 Jul '18

05 Jul '18

Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/27359 to review the following change. Change subject: src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq in SD2.0 mode ...................................................................... src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq in SD2.0 mode According to BKDG for AMD Family 16h Models 30h-3Fh Processors SDR50 tuning should be disabled in 0xA8 register. Also fix clock frequency setting in 0xA4 for stepping >= A1 which caused reduced performance of SD cards transfer speed even by half. Change-Id: I80ca754b0c89e08aa90ff885467c7486a3efb999 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Piotr Król <piotr.krol(a)3mdeb.com> --- M src/southbridge/amd/pi/hudson/sd.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/27359/1 diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index a76ff92..a87367f 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -43,7 +43,8 @@ pci_write_config32(dev, 0xD0, 0x0000058B); } else { /* Stepping >= A1 */ - pci_write_config32(dev, 0xA4, 0x31FE3FB2); + pci_write_config32(dev, 0xA4, 0x31FE32B2); + pci_write_config32(dev, 0xA8, 0x00000070); pci_write_config32(dev, 0xB0, 0x01180C19); pci_write_config32(dev, 0xD0, 0x0000078B); } -- To view, visit https://review.coreboot.org/27359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I80ca754b0c89e08aa90ff885467c7486a3efb999 Gerrit-Change-Number: 27359 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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coreboot-gerrit July 2018