coreboot-gerrit July 2018

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Change in coreboot[master]: riscv: adjust directory structure
by Anonymous Coward (Code Review) 05 Jul '18

05 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27353 to look at the new patch set (#2). Change subject: riscv: adjust directory structure ...................................................................... riscv: adjust directory structure Replicate directory layout from x86 for SMP. Change-Id: I01f50a810155b8227911e8708b1d5ee90cdbe929 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- R src/arch/riscv/include/arch/smp/atomic.h A src/arch/riscv/include/arch/smp/smp.h A src/arch/riscv/include/arch/smp/spinlock.h M src/arch/riscv/include/mcall.h M src/arch/riscv/mcall.c 5 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/27353/2 -- To view, visit https://review.coreboot.org/27353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I01f50a810155b8227911e8708b1d5ee90cdbe929 Gerrit-Change-Number: 27353 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward (1001664) Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: adjust directory structure
by Anonymous Coward (Code Review) 05 Jul '18

05 Jul '18

Anonymous Coward (1001664) has uploaded this change for review. ( https://review.coreboot.org/27353 Change subject: riscv: adjust directory structure ...................................................................... riscv: adjust directory structure Replicate directory layout from x86 for SMP. Change-Id: I01f50a810155b8227911e8708b1d5ee90cdbe929 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- R src/arch/riscv/include/arch/smp/atomic.h A src/arch/riscv/include/arch/smp/smp.h A src/arch/riscv/include/arch/smp/spinlock.h M src/arch/riscv/include/mcall.h M src/arch/riscv/mcall.c 5 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/27353/1 diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h similarity index 100% rename from src/arch/riscv/include/atomic.h rename to src/arch/riscv/include/arch/smp/atomic.h diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h new file mode 100644 index 0000000..bdf8ec4 --- /dev/null +++ b/src/arch/riscv/include/arch/smp/smp.h @@ -0,0 +1,12 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h new file mode 100644 index 0000000..bdf8ec4 --- /dev/null +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -0,0 +1,12 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index e4bc36f..f3f8e13 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -26,7 +26,7 @@ #ifndef __ASSEMBLER__ #include <arch/encoding.h> -#include <atomic.h> +#include <arch/smp/atomic.h> #include <stdint.h> typedef struct { diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c index 030accf..421dd45 100644 --- a/src/arch/riscv/mcall.c +++ b/src/arch/riscv/mcall.c @@ -29,7 +29,7 @@ #include <arch/errno.h> #include <atomic.h> #include <console/console.h> -#include <mcall.h> +#include <arch/smp/mcall.h> #include <string.h> #include <vm.h> -- To view, visit https://review.coreboot.org/27353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I01f50a810155b8227911e8708b1d5ee90cdbe929 Gerrit-Change-Number: 27353 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward (1001664)

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Change in coreboot[master]: riscv: add spin lock support
by build bot (Jenkins) (Code Review) 05 Jul '18

05 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27351 ) Change subject: riscv: add spin lock support ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/27351/4/src/arch/riscv/include/arch/smp/spi… File src/arch/riscv/include/arch/smp/spinlock.h: https://review.coreboot.org/#/c/27351/4/src/arch/riscv/include/arch/smp/spi… PS4, Line 41: #endif //_SPINLOCK_H_ adding a line without newline at end of file -- To view, visit https://review.coreboot.org/27351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia53b358be46efefe9dca0c8216693c73533c32d7 Gerrit-Change-Number: 27351 Gerrit-PatchSet: 4 Gerrit-Owner: Anonymous Coward (1001664) Gerrit-Reviewer: Anonymous Coward (1001664) Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Jul 2018 08:13:37 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add spin lock support, modify the directory structure
by Anonymous Coward (Code Review) 05 Jul '18

05 Jul '18

Hello Shawn Chang, Jonathan Neuschäfer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27351 to look at the new patch set (#2). Change subject: riscv: add spin lock support, modify the directory structure ...................................................................... riscv: add spin lock support, modify the directory structure Add spin lock support for riscv. replicate directory layout from x86 for SMP. Change-Id: Ia53b358be46efefe9dca0c8216693c73533c32d7 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A src/arch/riscv/include/arch/smp/atomic.h A src/arch/riscv/include/arch/smp/smp.h A src/arch/riscv/include/arch/smp/spinlock.h D src/arch/riscv/include/atomic.h 4 files changed, 151 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/27351/2 -- To view, visit https://review.coreboot.org/27351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia53b358be46efefe9dca0c8216693c73533c32d7 Gerrit-Change-Number: 27351 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward (1001664) Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com>

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Change in coreboot[master]: riscv: add spin lock support, modify the directory structure
by Anonymous Coward (Code Review) 05 Jul '18

05 Jul '18

Anonymous Coward (1001664) has uploaded this change for review. ( https://review.coreboot.org/27351 Change subject: riscv: add spin lock support, modify the directory structure ...................................................................... riscv: add spin lock support, modify the directory structure Add spin lock support for riscv. replicate directory layout from x86 for SMP. Change-Id: Ia53b358be46efefe9dca0c8216693c73533c32d7 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A src/arch/riscv/include/arch/smp/atomic.h A src/arch/riscv/include/arch/smp/smp.h A src/arch/riscv/include/arch/smp/spinlock.h D src/arch/riscv/include/atomic.h 4 files changed, 150 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/27351/1 diff --git a/src/arch/riscv/include/arch/smp/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h new file mode 100644 index 0000000..81999ac --- /dev/null +++ b/src/arch/riscv/include/arch/smp/atomic.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, + * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#ifndef _RISCV_ATOMIC_H +#define _RISCV_ATOMIC_H + +#include <arch/encoding.h> + +#define disable_irqsave() clear_csr(mstatus, MSTATUS_MIE) +#define enable_irqrestore(flags) set_csr(mstatus, (flags) & MSTATUS_MIE) + +#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val) +#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr)) + +#ifdef __riscv_atomic +# define atomic_or(ptr, inc) __sync_fetch_and_or(ptr, inc) +# define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc) +# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp) +# define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp) +#else +# define atomic_or(ptr, inc) ({ \ +long flags = disable_irqsave(); \ +typeof(ptr) res = *(volatile typeof(ptr))(ptr); \ +*(volatile typeof(ptr))(ptr) = res | (inc); \ +enable_irqrestore(flags); \ +res; }) +# define atomic_add(ptr, inc) ({ \ +long flags = disable_irqsave(); \ +typeof(ptr) res = *(volatile typeof(ptr))(ptr); \ +*(volatile typeof(ptr))(ptr) = res + (inc); \ +enable_irqrestore(flags); \ +res; }) +# define atomic_swap(ptr, swp) ({ \ +long flags = disable_irqsave(); \ +typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \ +*(volatile typeof(ptr))(ptr) = (swp); \ +enable_irqrestore(flags); \ +res; }) +# define atomic_cas(ptr, cmp, swp) ({ \ +long flags = disable_irqsave(); \ +typeof(ptr) res = *(volatile typeof(ptr))(ptr); \ +*(volatile typeof(ptr))(ptr) = (res == (cmp) ? swp : res); \ +enable_irqrestore(flags); \ +res; }) +#endif + +#endif diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h new file mode 100644 index 0000000..4d227e2 --- /dev/null +++ b/src/arch/riscv/include/arch/smp/smp.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SMP_H +#define _SMP_H + +#include <arch/encoding.h> +#include <arch/smp/atomic.h> + +/* + * If your code needs to temporarily block multiple-threads, do this: + * if(RUNNING_ON_HART(active)) // `active` is hartid of working thread + * { + * ... single-threaded work ... + * } + * SMP_SYNC(); + * // `SMP_SYNC` is not required, if other hart not need to wait for + * // the single-threaded work to complete. + * ... multi-threaded work ... + */ + + +#define RUNNING_ON_HART(active) ((active) == read_csr(mhartid)) + +#define SMP_SYNC() do {\ +static int counter;\ +atomic_add(&counter, 1);\ +do { barrier(); } while (counter < CONFIG_HART_NUM);\ +} while (0) + +#endif //_SMP_H diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h new file mode 100644 index 0000000..724e7a9 --- /dev/null +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + #include <arch/encoding.h> + #include <arch/smp/atomic.h> + +#define barrier() { asm volatile ("fence" ::: "memory"); } + +typedef struct { + volatile unsigned int lock; +} spinlock_t; + +static inline void spinlock_lock(spinlock_t *lock) +{ + do { + } while (atomic_cas(&lock->lock, 0, -1)); + barrier(); +} + +static inline void spinlock_unlock(spinlock_t *lock) +{ + barrier(); + atomic_set(&lock->lock, 0); +} diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h deleted file mode 100644 index bc739fb..0000000 --- a/src/arch/riscv/include/atomic.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ - -#ifndef _RISCV_ATOMIC_H -#define _RISCV_ATOMIC_H - -#include <arch/encoding.h> - -#define disable_irqsave() clear_csr(mstatus, MSTATUS_MIE) -#define enable_irqrestore(flags) set_csr(mstatus, (flags) & MSTATUS_MIE) - -typedef struct { int lock; } spinlock_t; -#define SPINLOCK_INIT {0} - -#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val) -#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr)) - -#ifdef PK_ENABLE_ATOMICS -# define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc) -# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp) -# define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp) -#else -# define atomic_add(ptr, inc) ({ \ - long flags = disable_irqsave(); \ - typeof(ptr) res = *(volatile typeof(ptr))(ptr); \ - *(volatile typeof(ptr))(ptr) = res + (inc); \ - enable_irqrestore(flags); \ - res; }) -# define atomic_swap(ptr, swp) ({ \ - long flags = disable_irqsave(); \ - typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \ - *(volatile typeof(ptr))(ptr) = (swp); \ - enable_irqrestore(flags); \ - res; }) -# define atomic_cas(ptr, cmp, swp) ({ \ - long flags = disable_irqsave(); \ - typeof(ptr) res = *(volatile typeof(ptr))(ptr); \ - if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \ - enable_irqrestore(flags); \ - res; }) -#endif - -#endif -- To view, visit https://review.coreboot.org/27351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia53b358be46efefe9dca0c8216693c73533c32d7 Gerrit-Change-Number: 27351 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward (1001664)

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Change in coreboot[master]: google: Use proper ACPI ID for Semtech chips: STH
by Furquan Shaikh (Code Review) 05 Jul '18

05 Jul '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/27347 ) Change subject: google: Use proper ACPI ID for Semtech chips: STH ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I85cd567a923cccd2504f351aae276b5f0d9db4de Gerrit-Change-Number: 27347 Gerrit-PatchSet: 2 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Matt Delco <delco(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Jul 2018 00:55:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google: Use proper ACPI ID for Semtech chips: STH
by Seunghwan Kim (Code Review) 05 Jul '18

05 Jul '18

Seunghwan Kim has posted comments on this change. ( https://review.coreboot.org/27347 ) Change subject: google: Use proper ACPI ID for Semtech chips: STH ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/27347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I85cd567a923cccd2504f351aae276b5f0d9db4de Gerrit-Change-Number: 27347 Gerrit-PatchSet: 2 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Matt Delco <delco(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Jul 2018 00:45:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/ibase/mb899: Remove unneeded includes
by Arthur Heymans (Code Review) 05 Jul '18

05 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27344 ) Change subject: mb/ibase/mb899: Remove unneeded includes ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/27344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee237206f309409be64307d2daee044da52a05e1 Gerrit-Change-Number: 27344 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Jul 2018 00:18:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/intel/d945gclf/romstage.c: Remove unneeded includes
by Arthur Heymans (Code Review) 05 Jul '18

05 Jul '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/27345 ) Change subject: mb/intel/d945gclf/romstage.c: Remove unneeded includes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/27345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3bdb93e51cabbfc14fe992ccdb6556e344e03c2f Gerrit-Change-Number: 27345 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Jul 2018 00:16:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: temporarily block multiple-threads
by build bot (Jenkins) (Code Review) 04 Jul '18

04 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27348 ) Change subject: riscv: temporarily block multiple-threads ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/27348/5/src/arch/riscv/include/smp.h File src/arch/riscv/include/smp.h: https://review.coreboot.org/#/c/27348/5/src/arch/riscv/include/smp.h@42 PS5, Line 42: * //`SMP_SYNC` is not required， if other hart not need to wait for the single-threaded work line over 80 characters -- To view, visit https://review.coreboot.org/27348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iedf58db6cddd44cfc17f5dfb3a5ccc0e12a49536 Gerrit-Change-Number: 27348 Gerrit-PatchSet: 5 Gerrit-Owner: Anonymous Coward (1001664) Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward (1001664) Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Jul 2018 15:04:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit July 2018