coreboot-gerrit July 2018

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Change in coreboot[master]: google/sentry: Add as a variant of glados
by Matt DeVillier (Code Review) 09 Jul '18

09 Jul '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/27418 Change subject: google/sentry: Add as a variant of glados ...................................................................... google/sentry: Add as a variant of glados Add google/sentry (Lenovo Thinkpad 13 Chromebook) as a variant of glados Skylake reference board: - add sentry-specific DPTF, EC config, GPIO config, Kconfig, NHLT config, PEI data, VBT, SPD data, and devicetree - add sentry-specific GPIO determination of which audio codec is present Adapted from Chromium branch firmware-glados-7820.B, commit b0c3efe54d877246d07f2467b2dff51cc30348fa [soc/intel/skylake: Enable VMX] Test: build/boot google/sentry, verify correct functionality Change-Id: I783422aedac8b7fc52098eebd05b2061a1011b60 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/Kconfig.name M src/mainboard/google/glados/mainboard.c A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex A src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex A src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex A src/mainboard/google/glados/variants/sentry/Makefile.inc A src/mainboard/google/glados/variants/sentry/data.vbt A src/mainboard/google/glados/variants/sentry/devicetree.cb A src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl A src/mainboard/google/glados/variants/sentry/include/variant/acpi/mainboard.asl A src/mainboard/google/glados/variants/sentry/include/variant/ec.h A src/mainboard/google/glados/variants/sentry/include/variant/gpio.h A src/mainboard/google/glados/variants/sentry/variant.c 14 files changed, 901 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27418/1 diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 99e538f..8ff5472 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -39,6 +39,7 @@ default "Chell" if BOARD_GOOGLE_CHELL default "Glados" if BOARD_GOOGLE_GLADOS default "Lars" if BOARD_GOOGLE_LARS + default "Sentry" if BOARD_GOOGLE_SENTRY config MAINBOARD_FAMILY string @@ -49,12 +50,14 @@ default "chell" if BOARD_GOOGLE_CHELL default "glados" if BOARD_GOOGLE_GLADOS default "lars" if BOARD_GOOGLE_LARS + default "sentry" if BOARD_GOOGLE_SENTRY config DEVICETREE string default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS default "variants/lars/devicetree.cb" if BOARD_GOOGLE_LARS + default "variants/sentry/devicetree.cb" if BOARD_GOOGLE_SENTRY config MAX_CPUS int @@ -87,4 +90,5 @@ default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS default "LARS TEST 5001" if BOARD_GOOGLE_LARS + default "SENTRY TEST 6297" if BOARD_GOOGLE_SENTRY endif diff --git a/src/mainboard/google/glados/Kconfig.name b/src/mainboard/google/glados/Kconfig.name index 074d9c3..6ad8b19 100644 --- a/src/mainboard/google/glados/Kconfig.name +++ b/src/mainboard/google/glados/Kconfig.name @@ -17,3 +17,11 @@ select DRIVERS_GENERIC_MAX98357A select EXCLUDE_NATIVE_SD_INTERFACE select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_SENTRY + bool "-> Sentry (Lenovo Thinkpad 13 Chromebook)" + select BOARD_GOOGLE_BASEBOARD_GLADOS + select DRIVERS_GENERIC_MAX98357A + select NHLT_DMIC_4CH if INCLUDE_NHLT_BLOBS + select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS + select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 451b3d4..476bcf7 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -19,8 +19,10 @@ #include <baseboard/variant.h> #include <console/console.h> #include <device/device.h> +#include <gpio.h> #include <stdlib.h> #include <soc/nhlt.h> +#include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" @@ -32,6 +34,24 @@ mainboard_ec_init(); } +static uint8_t adi_codec_enable(void) +{ +#ifdef AUDIO_DB_ID + return gpio_get(AUDIO_DB_ID); +#else + return 1; +#endif +} + +static uint8_t max_codec_enable(void) +{ +#ifdef AUDIO_DB_ID + return gpio_get(AUDIO_DB_ID) ? 0 : 1; +#else + return 1; +#endif +} + static unsigned long mainboard_write_acpi_tables( struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { @@ -58,12 +78,12 @@ printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); /* ADI Smart Amps for left and right. */ - if (IS_ENABLED(CONFIG_NHLT_SSM4567)) + if (IS_ENABLED(CONFIG_NHLT_SSM4567) && adi_codec_enable()) if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add ssm4567.\n"); /* MAXIM Smart Amps for left and right. */ - if (IS_ENABLED(CONFIG_NHLT_MAX98357)) { + if (IS_ENABLED(CONFIG_NHLT_MAX98357) && max_codec_enable()) { if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add max98357.\n"); diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex new file mode 100644 index 0000000..b5db37c --- /dev/null +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 03 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 47 54 4D 4C 41 52 2D 4E +55 44 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex new file mode 100644 index 0000000..c9239c3 --- /dev/null +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4A 54 4D 4C 41 52 2D 4E +55 44 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex new file mode 100644 index 0000000..5291046 --- /dev/null +++ b/src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 00 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 55 00 00 00 00 00 +20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 +20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/variants/sentry/Makefile.inc b/src/mainboard/google/glados/variants/sentry/Makefile.inc new file mode 100644 index 0000000..0ebf605 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/Makefile.inc @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += variant.c +ramstage-y += variant.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = hynix_dimm_H9CCNNN8GTMLAR-NUD # 0b0000 Dual Channel 4GB +SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107-1G-1866 # 0b0001 Dual Channel 4GB +SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF # 0b0010 Dual Channel 4GB +SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 Dual Channel 8GB +SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107-2G-1866 # 0b0100 Dual Channel 8GB +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0101 Dual Channel 8GB +SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR-NUD # 0b0110 Dual Channel 4GB +SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0111 Dual Channel 8GB +SPD_SOURCES += empty # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += empty # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += empty # 0b1100 +SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 + + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/glados/variants/sentry/data.vbt b/src/mainboard/google/glados/variants/sentry/data.vbt new file mode 100644 index 0000000..0aac82c --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/data.vbt Binary files differ diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb new file mode 100644 index 0000000..8af8940 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -0,0 +1,311 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "2" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "4" # 4s + register "PmConfigSlpSusMinAssert" = "3" # 4s + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root port 1 and 5. + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (card) + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board) + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (card) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board) + + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # I2C0 is 3.3V + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_A7" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + device i2c 39 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_05" + device i2c 15 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 on + chip drivers/i2c/nau8825 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)" + register "jkdet_enable" = "1" + register "jkdet_pull_enable" = "1" + register "jkdet_pull_up" = "1" + register "jkdet_polarity" = "1" # ActiveLow + register "vref_impedance" = "2" # 125kOhm + register "micbias_voltage" = "6" # 2.754 + register "sar_threshold_num" = "4" + register "sar_threshold[0]" = "0x08" + register "sar_threshold[1]" = "0x12" + register "sar_threshold[2]" = "0x26" + register "sar_threshold[3]" = "0x73" + register "sar_hysteresis" = "0" + register "sar_voltage" = "6" + register "sar_compare_time" = "1" # 1us + register "sar_sampling_time" = "1" # 4us + register "short_key_debounce" = "3" # 30ms + register "jack_insert_debounce" = "7" # 512ms + register "jack_eject_debounce" = "0" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "uid" = "0" + register "device_present_gpio" = "GPP_E3" + device i2c 34 on end + end + chip drivers/i2c/generic + register "hid" = ""INT343B"" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "uid" = "1" + register "device_present_gpio" = "GPP_E3" + device i2c 35 on end + end + end # I2C #4 + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW0_16" + device pci 00.0 on end + end + end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" + register "device_present_gpio" = "GPP_E3" + register "device_present_gpio_invert" = "1" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..c991373 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/dptf.asl @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 98 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 77 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 70 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 120 +#define DPTF_TSR0_ACTIVE_AC1 110 +#define DPTF_TSR0_ACTIVE_AC2 47 +#define DPTF_TSR0_ACTIVE_AC3 44 +#define DPTF_TSR0_ACTIVE_AC4 41 +#define DPTF_TSR0_ACTIVE_AC5 38 +#define DPTF_TSR0_ACTIVE_AC6 35 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 70 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 70 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +#undef DPTF_ENABLE_FAN_CONTROL /*Disable DPTF Active policy*/ + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, + Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, + Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, + Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, + Package () {60, 0xFFFFFFFF, 3838, 90, 900}, + Package () {50, 0xFFFFFFFF, 3402, 65, 650}, + Package () {40, 0xFFFFFFFF, 2904, 45, 450}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40, + 35, 0, 0, 0 + } +}) +#endif + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 20, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 20, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 20, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 20, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 5000 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 18700, /* PowerLimitMinimum */ + 18700, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/include/variant/acpi/mainboard.asl diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/ec.h b/src/mainboard/google/glados/variants/sentry/include/variant/ec.h new file mode 100644 index 0000000..f56154b --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/include/variant/ec.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h new file mode 100644 index 0000000..600a319 --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_WLAN_WAKE GPE0_DW0_16 + +/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_TOUCHPAD_WAKE GPE0_DW0_05 + +/* Input device interrupt configuration */ +#define TOUCHPAD_INT_L GPP_B3_IRQ +#define TOUCHSCREEN_INT_L GPP_E7_IRQ +#define MIC_INT_L GPP_F10_IRQ + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +/* + * GPP_E3 is AUDIO_DB_ID. + * It is a dual purpose GPIO, used for Audio Daughter + * Board Identification & to control the shutdown mode pin + * of the Maxim amp. + */ +#define AUDIO_DB_ID GPP_E3 + +/* SD controller needs additional card detect GPIO to support RTD3 */ +#define GPIO_SD_CARD_DETECT GPP_A7 + +#ifndef __ACPI__ +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), +/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), +/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), +/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), +/* GYRO_INT */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), +/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), +/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), +/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), +/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), +/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), +/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), +/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), +/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), +/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), +/* USB_CTL */ PAD_CFG_NC(GPP_C7), +/* UART0_RXD */ PAD_CFG_NC(GPP_C8), +/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* NFC_RST* */ PAD_CFG_NC(GPP_C10), +/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), +/* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), +/* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), +/* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), +/* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), +/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), +/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), +/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), +/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), +/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), +/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), +/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), +/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), +/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), +/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), +/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), +/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), +/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), +/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), +/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PU, DEEP, NF1), +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7 */ PAD_CFG_NC(GPD7), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), +/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +}; + +#endif + +#endif diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c new file mode 100644 index 0000000..00f49fe --- /dev/null +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <baseboard/variant.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +#define K4E6E304EE_MEM_ID 0x3 + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 6, 5, 4, 7 }, + { 2, 3, 0, 1, 6, 7, 4, 5 } }; + + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; + + /* Strengthen the Rcomp Target Ctrl for K4E6E304EE_MEM_ID */ + const u16 StrengthendRcompTarget[5] = { 100, 40, 40, 21, 40 }; + + /* Default Rcomp Target assignment */ + const u16 *targeted_rcomp = RcompTarget; + + memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); + memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); + memcpy(pei_data->RcompResistor, RcompResistor, + sizeof(RcompResistor)); + + /* Override Rcomp Target assignment for specific SKU(s) */ + if (pei_data->mem_cfg_id == K4E6E304EE_MEM_ID) + targeted_rcomp = StrengthendRcompTarget; + + memcpy(pei_data->RcompTarget, targeted_rcomp, + sizeof(pei_data->RcompTarget)); +} -- To view, visit https://review.coreboot.org/27418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I783422aedac8b7fc52098eebd05b2061a1011b60 Gerrit-Change-Number: 27418 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: riscv: add spin lock support
by build bot (Jenkins) (Code Review) 09 Jul '18

09 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27356 ) Change subject: riscv: add spin lock support ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/27356/8/src/arch/riscv/include/arch/smp/ato… File src/arch/riscv/include/arch/smp/atomic.h: https://review.coreboot.org/#/c/27356/8/src/arch/riscv/include/arch/smp/ato… PS8, Line 45: # define atomic_cas(v, cmp, swp) __sync_val_compare_and_swap(&((v)->counter), cmp, swp) line over 80 characters -- To view, visit https://review.coreboot.org/27356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Gerrit-Change-Number: 27356 Gerrit-PatchSet: 8 Gerrit-Owner: Xiang Wang (1001664) Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang (1001664) Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 09 Jul 2018 13:55:43 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mediatek/mt8183: Add GPIO support
by Tristan Hsieh (Code Review) 09 Jul '18

09 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27417 to look at the new patch set (#2). Change subject: mediatek/mt8183: Add GPIO support ...................................................................... mediatek/mt8183: Add GPIO support This patch implements gpio_set_pull() and links the common mediatek GPIO code to support IO config for other drivers (ex. SPI) and the requested functions in src/include/gpio.h. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a Signed-off-by: jg_poxu <jg_poxu(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/gpio.h A src/soc/mediatek/mt8183/include/soc/pinmux.h 5 files changed, 555 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/27417/2 -- To view, visit https://review.coreboot.org/27417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a Gerrit-Change-Number: 27417 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mediatek/mt8183: Add GPIO support
by build bot (Jenkins) (Code Review) 09 Jul '18

09 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27417 ) Change subject: mediatek/mt8183: Add GPIO support ...................................................................... Patch Set 1: (182 comments) https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… File src/soc/mediatek/mt8183/include/soc/pinmux.h: https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 20: #define PINMUX_CONSTANTS(index, name, func1, func2, func3, func4, func5, func6, func7) \ line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 20: #define PINMUX_CONSTANTS(index, name, func1, func2, func3, func4, func5, func6, func7) \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 31: PINMUX_CONSTANTS(GPIO_PAD_0, PAD_EINT0, MRG_SYNC, PCM0_SYNC, TP_GPIO0_AO, SRCLKENAI0, SCP_SPI2_CS, I2S3_MCK, SPI2_CSB), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 32: PINMUX_CONSTANTS(GPIO_PAD_1, PAD_EINT1, MRG_CLK, PCM0_CLK, TP_GPIO1_AO, CLKM3, SCP_SPI2_MO, I2S3_BCK, SPI2_MO), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 33: PINMUX_CONSTANTS(GPIO_PAD_2, PAD_EINT2, MRG_DO, PCM0_DO, TP_GPIO2_AO, SCL6, SCP_SPI2_CK, I2S3_LRCK, SPI2_CLK), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 34: PINMUX_CONSTANTS(GPIO_PAD_3, PAD_EINT3, MRG_DI, PCM0_DI, TP_GPIO3_AO, SDA6, TDM_MCK, I2S3_DO, SCP_VREQ_VAO), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 35: PINMUX_CONSTANTS(GPIO_PAD_4, PAD_EINT4, PWM_B, I2S0_MCK, SSPM_UTXD_AO, MD_URXD1, TDM_BCK, TP_GPIO4_AO, DAP_MD32_SWD), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 36: PINMUX_CONSTANTS(GPIO_PAD_5, PAD_EINT5, PWM_C, I2S0_BCK, SSPM_URXD_AO, MD_UTXD1, TDM_LRCK, TP_GPIO5_AO, DAP_MD32_SWCK), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 37: PINMUX_CONSTANTS(GPIO_PAD_6, PAD_EINT6, PWM_A, I2S0_LRCK, IDDIG, MD_URXD0, TDM_DATA0, TP_GPIO6_AO, CMFLASH), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 38: PINMUX_CONSTANTS(GPIO_PAD_7, PAD_EINT7, SPI1_B_MI, I2S0_DI, USB_DRVVBUS, MD_UTXD0, TDM_DATA1, TP_GPIO7_AO, DVFSRC_EXT_REQ), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 39: PINMUX_CONSTANTS(GPIO_PAD_8, PAD_EINT8, SPI1_B_CSB, ANT_SEL3, SCL7, CONN_MCU_TRST_B, TDM_DATA2, MD_INT0, JTRSTN_SEL1), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 40: PINMUX_CONSTANTS(GPIO_PAD_9, PAD_EINT9, SPI1_B_MO, ANT_SEL4, CMMCLK2, CONN_MCU_DBGACK_N, SSPM_JTAG_TRSTN, IO_JTAG_TRSTN, DBG_MON_B10), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 41: PINMUX_CONSTANTS(GPIO_PAD_10, PAD_EINT10, SPI1_B_CLK, ANT_SEL5, CMMCLK3, CONN_MCU_DBGI_N, TDM_DATA3, EXT_FRAME_SYNC, DBG_MON_B11), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 42: PINMUX_CONSTANTS(GPIO_PAD_11, PAD_SCL6, TP_URXD1_AO, IDDIG, SCL6, UCTS1, UCTS0, SRCLKENAI1, I2S5_MCK), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 43: PINMUX_CONSTANTS(GPIO_PAD_12, PAD_SDA6, TP_UTXD1_AO, USB_DRVVBUS, SDA6, URTS1, URTS0, I2S2_DI2, I2S5_BCK), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 44: PINMUX_CONSTANTS(GPIO_PAD_13, PAD_DPI_D0, DBPI_D0, SPI5_MI, PCM0_SYNC, MD_URXD0, ANT_SEL3, I2S0_MCK, DBG_MON_B15), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 45: PINMUX_CONSTANTS(GPIO_PAD_14, PAD_DPI_D1, DBPI_D1, SPI5_CSB, PCM0_CLK, MD_UTXD0, ANT_SEL4, I2S0_BCK, DBG_MON_B16), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 46: PINMUX_CONSTANTS(GPIO_PAD_15, PAD_DPI_D2, DBPI_D2, SPI5_MO, PCM0_DO, MD_URXD1, ANT_SEL5, I2S0_LRCK, DBG_MON_B17), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 47: PINMUX_CONSTANTS(GPIO_PAD_16, PAD_DPI_D3, DBPI_D3, SPI5_CLK, PCM0_DI, MD_UTXD1, ANT_SEL6, I2S0_DI, DBG_MON_B23), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 48: PINMUX_CONSTANTS(GPIO_PAD_17, PAD_DPI_D4, DBPI_D4, SPI4_MI, CONN_MCU_TRST_B, MD_INT0, ANT_SEL7, I2S3_MCK, DBG_MON_A1), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 49: PINMUX_CONSTANTS(GPIO_PAD_18, PAD_DPI_D5, DBPI_D5, SPI4_CSB, CONN_MCU_DBGI_N, MD_INT0, SCP_VREQ_VAO, I2S3_BCK, DBG_MON_A2), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 50: PINMUX_CONSTANTS(GPIO_PAD_19, PAD_DPI_D6, DBPI_D6, SPI4_MO, CONN_MCU_TDO, MD_INT2_C2K_UIM1_HOT_PLUG, URXD1, I2S3_LRCK, DBG_MON_A3), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 51: PINMUX_CONSTANTS(GPIO_PAD_20, PAD_DPI_D7, DBPI_D7, SPI4_CLK, CONN_MCU_DBGACK_N, MD_INT1_C2K_UIM0_HOT_PLUG, UTXD1, I2S3_DO, DBG_MON_A19), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 52: PINMUX_CONSTANTS(GPIO_PAD_21, PAD_DPI_D8, DBPI_D8, SPI3_MI, CONN_MCU_TMS, DAP_MD32_SWD, CONN_MCU_AICE_TMSC, I2S2_MCK, DBG_MON_B5), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 53: PINMUX_CONSTANTS(GPIO_PAD_22, PAD_DPI_D9, DBPI_D9, SPI3_CSB, CONN_MCU_TCK, DAP_MD32_SWCK, CONN_MCU_AICE_TCKC, I2S2_BCK, DBG_MON_B6), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 54: PINMUX_CONSTANTS(GPIO_PAD_23, PAD_DPI_D10, DBPI_D10, SPI3_MO, CONN_MCU_TDI, UCTS1, EXT_FRAME_SYNC, I2S2_LRCK, DBG_MON_B7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 55: PINMUX_CONSTANTS(GPIO_PAD_24, PAD_DPI_D11, DBPI_D11, SPI3_CLK, SRCLKENAI0, URTS1, IO_JTAG_TCK, I2S2_DI, DBG_MON_B31), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 56: PINMUX_CONSTANTS(GPIO_PAD_25, PAD_DPI_HSYNC, DBPI_HSYNC, ANT_SEL0, SCL6, KPCOL2, IO_JTAG_TMS, I2S1_MCK, DBG_MON_B0), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 57: PINMUX_CONSTANTS(GPIO_PAD_26, PAD_DPI_VSYNC, DBPI_VSYNC, ANT_SEL1, SDA6, KPROW2, IO_JTAG_TDI, I2S1_BCK, DBG_MON_B1), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 58: PINMUX_CONSTANTS(GPIO_PAD_27, PAD_DPI_DE, DBPI_DE, ANT_SEL2, SCL7, DMIC_CLK, IO_JTAG_TDO, I2S1_LRCK, DBG_MON_B9), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 59: PINMUX_CONSTANTS(GPIO_PAD_28, PAD_DPI_CK, DBPI_CK, DVFSRC_EXT_REQ, SDA7, DMIC_DAT, IO_JTAG_TRSTN, I2S1_DO, DBG_MON_B32), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 60: PINMUX_CONSTANTS(GPIO_PAD_29, PAD_MSDC1_CLK, MSDC1_CLK, IO_JTAG_TCK, UDI_TCK, CONN_DSP_JCK, SSPM_JTAG_TCK, PCM1_CLK, DBG_MON_A6), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 61: PINMUX_CONSTANTS(GPIO_PAD_30, PAD_MSDC1_DAT3, MSDC1_DAT3, DAP_MD32_SWD, CONN_MCU_AICE_TMSC, CONN_DSP_JINTP, SSPM_JTAG_TRSTN, PCM1_DI, DBG_MON_A7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 62: PINMUX_CONSTANTS(GPIO_PAD_31, PAD_MSDC1_CMD, MSDC1_CMD, IO_JTAG_TMS, UDI_TMS, CONN_DSP_JMS, SSPM_JTAG_TMS, PCM1_SYNC, DBG_MON_A8), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 63: PINMUX_CONSTANTS(GPIO_PAD_32, PAD_MSDC1_DAT0, MSDC1_DAT0, IO_JTAG_TDI, UDI_TDI, CONN_DSP_JDI, SSPM_JTAG_TDI, PCM1_DO0, DBG_MON_A9), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 64: PINMUX_CONSTANTS(GPIO_PAD_33, PAD_MSDC1_DAT2, MSDC1_DAT2, IO_JTAG_TRSTN, UDI_NTRST, DAP_MD32_SWCK, CONN_MCU_AICE_TCKC, PCM1_DO2, DBG_MON_A10), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 65: PINMUX_CONSTANTS(GPIO_PAD_34, PAD_MSDC1_DAT1, MSDC1_DAT1, IO_JTAG_TDO, UDI_TDO, CONN_DSP_JDO, SSPM_JTAG_TDO, PCM1_DO1, DBG_MON_A11), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 66: PINMUX_CONSTANTS(GPIO_PAD_35, PAD_SIM2_SIO, MD1_SIM2_SIO, CCU_JTAG_TDO, MD1_SIM1_SIO, RES4, SCP_JTAG_TDO, CONN_DSP_JMS, DBG_MON_A28), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 67: PINMUX_CONSTANTS(GPIO_PAD_36, PAD_SIM2_SRST, MD1_SIM2_SRST, CCU_JTAG_TMS, MD1_SIM1_SRST, CONN_MCU_AICE_TMSC, SCP_JTAG_TMS, CONN_DSP_JINTP, DBG_MON_A29), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 68: PINMUX_CONSTANTS(GPIO_PAD_37, PAD_SIM2_SCLK, MD1_SIM2_SCLK, CCU_JTAG_TDI, MD1_SIM1_SCLK, RES4, SCP_JTAG_TDI, CONN_DSP_JDO, DBG_MON_A30), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 69: PINMUX_CONSTANTS(GPIO_PAD_38, PAD_SIM1_SCLK, MD1_SIM1_SCLK, RES2, MD1_SIM2_SCLK, CONN_MCU_AICE_TCKC, RES5, RES6, DBG_MON_A20), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 70: PINMUX_CONSTANTS(GPIO_PAD_39, PAD_SIM1_SRST, MD1_SIM1_SRST, CCU_JTAG_TCK, MD1_SIM2_SRST, RES4, SCP_JTAG_TCK, CONN_DSP_JCK, DBG_MON_A31), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 71: PINMUX_CONSTANTS(GPIO_PAD_40, PAD_SIM1_SIO, MD1_SIM1_SIO, CCU_JTAG_TRST, MD1_SIM2_SIO, RES4, SCP_JTAG_TRSTN, CONN_DSP_JDI, DBG_MON_A32), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 72: PINMUX_CONSTANTS(GPIO_PAD_41, PAD_IDDIG, IDDIG, URXD1, UCTS0, SSPM_UTXD_AO, EXT_FRAME_SYNC, DMIC_CLK, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 73: PINMUX_CONSTANTS(GPIO_PAD_42, PAD_DRVBUS, USB_DRVVBUS, UTXD1, URTS0, SSPM_URXD_AO, EXT_FRAME_SYNC, DMIC_DAT, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 74: PINMUX_CONSTANTS(GPIO_PAD_43, PAD_DISP_PWM, DISP_PWM, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 75: PINMUX_CONSTANTS(GPIO_PAD_44, PAD_DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 76: PINMUX_CONSTANTS(GPIO_PAD_45, PAD_LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 77: PINMUX_CONSTANTS(GPIO_PAD_46, PAD_INT_SIM2, MD_INT2_C2K_UIM1_HOT_PLUG, URXD1, UCTS1, CCU_UTXD_AO, TP_UCTS1_AO, IDDIG, I2S5_LRCK), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 78: PINMUX_CONSTANTS(GPIO_PAD_47, PAD_INT_SIM1, MD_INT1_C2K_UIM0_HOT_PLUG, UTXD1, URTS1, CCU_URXD_AO, TP_URTS1_AO, USB_DRVVBUS, I2S5_DO), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 79: PINMUX_CONSTANTS(GPIO_PAD_48, PAD_SCL5, SCL5, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 80: PINMUX_CONSTANTS(GPIO_PAD_49, PAD_SDA5, SDA5, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 81: PINMUX_CONSTANTS(GPIO_PAD_50, PAD_SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 82: PINMUX_CONSTANTS(GPIO_PAD_51, PAD_SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 83: PINMUX_CONSTANTS(GPIO_PAD_52, PAD_BPI_ANT2, BPI_ANT2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 84: PINMUX_CONSTANTS(GPIO_PAD_53, PAD_BPI_ANT0, BPI_ANT0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 85: PINMUX_CONSTANTS(GPIO_PAD_54, PAD_BPI_OLAT1, BPI_OLAT1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 86: PINMUX_CONSTANTS(GPIO_PAD_55, PAD_BPI_BUS8, BPI_BUS8, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 87: PINMUX_CONSTANTS(GPIO_PAD_56, PAD_BPI_BUS9, BPI_BUS9, SCL_6306, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 88: PINMUX_CONSTANTS(GPIO_PAD_57, PAD_BPI_BUS10, BPI_BUS10, SDA_6306, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 89: PINMUX_CONSTANTS(GPIO_PAD_58, PAD_RFIC0_BSI_D2, RFIC0_BSI_D2, SPM_BSI_D2, PWM_B, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 90: PINMUX_CONSTANTS(GPIO_PAD_59, PAD_RFIC0_BSI_D1, RFIC0_BSI_D1, SPM_BSI_D1, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 91: PINMUX_CONSTANTS(GPIO_PAD_60, PAD_RFIC0_BSI_D0, RFIC0_BSI_D0, SPM_BSI_D0, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 92: PINMUX_CONSTANTS(GPIO_PAD_61, PAD_MISC_BSI_DO_1, MIPI1_SDATA, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 93: PINMUX_CONSTANTS(GPIO_PAD_62, PAD_MISC_BSI_CK_1, MIPI1_SCLK, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 94: PINMUX_CONSTANTS(GPIO_PAD_63, PAD_MISC_BSI_DO_0, MIPI0_SDATA, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 95: PINMUX_CONSTANTS(GPIO_PAD_64, PAD_MISC_BSI_CK_0, MIPI0_SCLK, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 96: PINMUX_CONSTANTS(GPIO_PAD_65, PAD_MISC_BSI_DO_3, MIPI3_SDATA, BPI_OLAT2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 97: PINMUX_CONSTANTS(GPIO_PAD_66, PAD_MISC_BSI_CK_3, MIPI3_SCLK, BPI_OLAT3, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 98: PINMUX_CONSTANTS(GPIO_PAD_67, PAD_MISC_BSI_DO_2, MIPI2_SDATA, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 99: PINMUX_CONSTANTS(GPIO_PAD_68, PAD_MISC_BSI_CK_2, MIPI2_SCLK, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 100: PINMUX_CONSTANTS(GPIO_PAD_69, PAD_BPI_BUS7, BPI_BUS7, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 101: PINMUX_CONSTANTS(GPIO_PAD_70, PAD_BPI_BUS6, BPI_BUS6, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 102: PINMUX_CONSTANTS(GPIO_PAD_71, PAD_BPI_BUS5, BPI_BUS5, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 103: PINMUX_CONSTANTS(GPIO_PAD_72, PAD_BPI_BUS4, BPI_BUS4, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 104: PINMUX_CONSTANTS(GPIO_PAD_73, PAD_BPI_BUS3, BPI_BUS3, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 105: PINMUX_CONSTANTS(GPIO_PAD_74, PAD_BPI_BUS2, BPI_BUS2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 106: PINMUX_CONSTANTS(GPIO_PAD_75, PAD_BPI_BUS1, BPI_BUS1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 107: PINMUX_CONSTANTS(GPIO_PAD_76, PAD_BPI_BUS0, BPI_BUS0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 108: PINMUX_CONSTANTS(GPIO_PAD_77, PAD_BPI_ANT1, BPI_ANT1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 109: PINMUX_CONSTANTS(GPIO_PAD_78, PAD_BPI_OLAT0, BPI_OLAT0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 110: PINMUX_CONSTANTS(GPIO_PAD_79, PAD_BPI_PA_VM1, BPI_PA_VM1, MIPI4_SDATA, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 111: PINMUX_CONSTANTS(GPIO_PAD_80, PAD_BPI_PA_VM0, BPI_PA_VM0, MIPI4_SCLK, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 112: PINMUX_CONSTANTS(GPIO_PAD_81, PAD_SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 113: PINMUX_CONSTANTS(GPIO_PAD_82, PAD_SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 114: PINMUX_CONSTANTS(GPIO_PAD_83, PAD_SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 115: PINMUX_CONSTANTS(GPIO_PAD_84, PAD_SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 116: PINMUX_CONSTANTS(GPIO_PAD_85, PAD_SPI_MI, SPI0_MI, SCP_SPI0_MI, CLKM3, I2S1_BCK, MFG_DFD_JTAG_TDO, DFD_TDO, JTDO_SEL1), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 117: PINMUX_CONSTANTS(GPIO_PAD_86, PAD_SPI_CSB, SPI0_CSB, SCP_SPI0_CS, CLKM0, I2S1_LRCK, MFG_DFD_JTAG_TMS, DFD_TMS, JTMS_SEL1), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 118: PINMUX_CONSTANTS(GPIO_PAD_87, PAD_SPI_MO, SPI0_MO, SCP_SPI0_MO, SDA1, I2S1_DO, MFG_DFD_JTAG_TDI, DFD_TDI, JTDI_SEL1), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 119: PINMUX_CONSTANTS(GPIO_PAD_88, PAD_SPI_CLK, SPI0_CLK, SCP_SPI0_CK, SCL1, I2S1_MCK, MFG_DFD_JTAG_TCK, DFD_TCK_XI, JTCK_SEL1), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 120: PINMUX_CONSTANTS(GPIO_PAD_89, PAD_SRCLKENAI, SRCLKENAI0, PWM_C, I2S5_BCK, ANT_SEL6, SDA8, CMVREF0, DBG_MON_A21), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 121: PINMUX_CONSTANTS(GPIO_PAD_90, PAD_PWM_A, PWM_A, CMMCLK2, I2S5_LRCK, SCP_VREQ_VAO, SCL8, PTA_RXD, DBG_MON_A22), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 122: PINMUX_CONSTANTS(GPIO_PAD_91, PAD_KPROW1, KPROW1, PWM_B, I2S5_DO, ANT_SEL7, CMMCLK3, PTA_TXD, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 123: PINMUX_CONSTANTS(GPIO_PAD_92, PAD_KPROW0, KPROW0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 124: PINMUX_CONSTANTS(GPIO_PAD_93, PAD_KPCOL0, KPCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B27), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 125: PINMUX_CONSTANTS(GPIO_PAD_94, PAD_KPCOL1, KPCOL1, I2S2_DI2, I2S5_MCK, CMMCLK2, SCP_SPI2_MI, SRCLKENAI1, SPI2_MI), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 126: PINMUX_CONSTANTS(GPIO_PAD_95, PAD_URXD0, URXD0, UTXD0, MD_URXD0, MD_URXD1, SSPM_URXD_AO, CCU_URXD_AO, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 127: PINMUX_CONSTANTS(GPIO_PAD_96, PAD_UTXD0, UTXD0, URXD0, MD_UTXD0, MD_UTXD1, SSPM_UTXD_AO, CCU_UTXD_AO, DBG_MON_B2), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 128: PINMUX_CONSTANTS(GPIO_PAD_97, PAD_CAM_PDN0, UCTS0, I2S2_MCK, IDDIG, CONN_MCU_TDO, SSPM_JTAG_TDO, IO_JTAG_TDO, DBG_MON_B3), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 129: PINMUX_CONSTANTS(GPIO_PAD_98, PAD_CAM_PDN1, URTS0, I2S2_BCK, USB_DRVVBUS, CONN_MCU_TMS, SSPM_JTAG_TMS, IO_JTAG_TMS, DBG_MON_B4), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 130: PINMUX_CONSTANTS(GPIO_PAD_99, PAD_CAM_CLK0, CMMCLK0, RES2, RES3, CONN_MCU_AICE_TMSC, RES5, RES6, DBG_MON_B28), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 131: PINMUX_CONSTANTS(GPIO_PAD_100, PAD_CAM_CLK1, CMMCLK1, PWM_C, MD_INT1_C2K_UIM0_HOT_PLUG, CONN_MCU_AICE_TCKC, RES5, RES6, DBG_MON_B29), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 132: PINMUX_CONSTANTS(GPIO_PAD_101, PAD_CAM_RST0, CLKM2, I2S2_LRCK, CMVREF1, CONN_MCU_TCK, SSPM_JTAG_TCK, IO_JTAG_TCK, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 133: PINMUX_CONSTANTS(GPIO_PAD_102, PAD_CAM_RST1, CLKM1, I2S2_DI, DVFSRC_EXT_REQ, CONN_MCU_TDI, SSPM_JTAG_TDI, IO_JTAG_TDI, DBG_MON_B8), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 134: PINMUX_CONSTANTS(GPIO_PAD_103, PAD_SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 135: PINMUX_CONSTANTS(GPIO_PAD_104, PAD_SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 136: PINMUX_CONSTANTS(GPIO_PAD_105, PAD_SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 137: PINMUX_CONSTANTS(GPIO_PAD_106, PAD_SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 138: PINMUX_CONSTANTS(GPIO_PAD_107, PAD_CAM_PDN2, DMIC_CLK, ANT_SEL0, CLKM0, SDA7, EXT_FRAME_SYNC, PWM_A, DBG_MON_B12), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 139: PINMUX_CONSTANTS(GPIO_PAD_108, PAD_CAM_CLK2, CMMCLK2, ANT_SEL1, CLKM1, SCL8, DAP_MD32_SWD, PWM_B, DBG_MON_B13), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 140: PINMUX_CONSTANTS(GPIO_PAD_109, PAD_CAM_RST2, DMIC_DAT, ANT_SEL2, CLKM2, SDA8, DAP_MD32_SWCK, PWM_C, DBG_MON_B14), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 141: PINMUX_CONSTANTS(GPIO_PAD_110, PAD_CAM_PDN3, SCL7, ANT_SEL0, TP_URXD1_AO, USB_DRVVBUS, SRCLKENAI1, KPCOL2, URXD1), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 142: PINMUX_CONSTANTS(GPIO_PAD_111, PAD_CAM_CLK3, CMMCLK3, ANT_SEL1, SRCLKENAI0, SCP_VREQ_VAO, MD_INT2_C2K_UIM1_HOT_PLUG, RES6, DVFSRC_EXT_REQ), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 143: PINMUX_CONSTANTS(GPIO_PAD_112, PAD_CAM_RST3, SDA7, ANT_SEL2, TP_UTXD1_AO, IDDIG, AGPS_SYNC, KPROW2, UTXD1), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 144: PINMUX_CONSTANTS(GPIO_PAD_113, PAD_CONN_TOP_CLK, CONN_TOP_CLK, RES2, SCL6, AUXIF_CLK0, RES5, TP_UCTS1_AO, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 145: PINMUX_CONSTANTS(GPIO_PAD_114, PAD_CONN_TOP_DATA, CONN_TOP_DATA, RES2, SDA6, AUXIF_ST0, RES5, TP_URTS1_AO, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 146: PINMUX_CONSTANTS(GPIO_PAD_115, PAD_CONN_BT_CLK, CONN_BT_CLK, UTXD1, PTA_TXD, AUXIF_CLK1, DAP_MD32_SWD, TP_UTXD1_AO, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 147: PINMUX_CONSTANTS(GPIO_PAD_116, PAD_CONN_BT_DATA, CONN_BT_DATA, IPU_JTAG_TRST, RES3, AUXIF_ST1, DAP_MD32_SWCK, TP_URXD2_AO, DBG_MON_A0), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 148: PINMUX_CONSTANTS(GPIO_PAD_117, PAD_CONN_WF_CTRL0, CONN_WF_HB0, IPU_JTAG_TDO, RES3, RES4, RES5, TP_UTXD2_AO, DBG_MON_A4), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 149: PINMUX_CONSTANTS(GPIO_PAD_118, PAD_CONN_WF_CTRL1, CONN_WF_HB1, IPU_JTAG_TDI, RES3, RES4, SSPM_URXD_AO, TP_UCTS2_AO, DBG_MON_A5), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 150: PINMUX_CONSTANTS(GPIO_PAD_119, PAD_CONN_WF_CTRL2, CONN_WF_HB2, IPU_JTAG_TCK, RES3, RES4, SSPM_UTXD_AO, TP_URTS2_AO, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 151: PINMUX_CONSTANTS(GPIO_PAD_120, PAD_CONN_WB_PTA, CONN_WB_PTA, IPU_JTAG_TMS, RES3, RES4, CCU_URXD_AO, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 152: PINMUX_CONSTANTS(GPIO_PAD_121, PAD_CONN_HRST_B, CONN_HRST_B, URXD1, PTA_RXD, RES4, CCU_UTXD_AO, TP_URXD1_AO, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 153: PINMUX_CONSTANTS(GPIO_PAD_122, PAD_MSDC0_CMD, MSDC0_CMD, PWRMCU_URXD2_AO, ANT_SEL1, RES4, RES5, RES6, DBG_MON_A12), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 154: PINMUX_CONSTANTS(GPIO_PAD_123, PAD_MSDC0_DAT0, MSDC0_DAT0, RES2, ANT_SEL0, RES4, RES5, RES6, DBG_MON_A13), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 155: PINMUX_CONSTANTS(GPIO_PAD_124, PAD_MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A14), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 156: PINMUX_CONSTANTS(GPIO_PAD_125, PAD_MSDC0_DAT2, MSDC0_DAT2, RES2, MRG_CLK, RES4, RES5, RES6, DBG_MON_A15), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 157: PINMUX_CONSTANTS(GPIO_PAD_126, PAD_MSDC0_DAT4, MSDC0_DAT4, RES2, ANT_SEL5, RES4, RES5, UFS_MPHY_SCL, DBG_MON_A16), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 158: PINMUX_CONSTANTS(GPIO_PAD_127, PAD_MSDC0_DAT6, MSDC0_DAT6, RES2, ANT_SEL4, RES4, RES5, UFS_MPHY_SDA, DBG_MON_A17), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 159: PINMUX_CONSTANTS(GPIO_PAD_128, PAD_MSDC0_DAT1, MSDC0_DAT1, RES2, ANT_SEL2, RES4, RES5, UFS_UNIPRO_SDA, DBG_MON_A18), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 160: PINMUX_CONSTANTS(GPIO_PAD_129, PAD_MSDC0_DAT5, MSDC0_DAT5, RES2, ANT_SEL3, RES4, RES5, UFS_UNIPRO_SCL, DBG_MON_A23), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 161: PINMUX_CONSTANTS(GPIO_PAD_130, PAD_MSDC0_DAT7, MSDC0_DAT7, RES2, MRG_DO, RES4, RES5, RES6, DBG_MON_A24), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 162: PINMUX_CONSTANTS(GPIO_PAD_131, PAD_MSDC0_DSL, MSDC0_DSL, RES2, MRG_SYNC, RES4, RES5, RES6, DBG_MON_A25), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 163: PINMUX_CONSTANTS(GPIO_PAD_132, PAD_MSDC0_DAT3, MSDC0_DAT3, RES2, MRG_DI, RES4, RES5, RES6, DBG_MON_A26), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 164: PINMUX_CONSTANTS(GPIO_PAD_133, PAD_MSDC0_RSTB, MSDC0_RSTB, RES2, AGPS_SYNC, RES4, RES5, RES6, DBG_MON_A27), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 165: PINMUX_CONSTANTS(GPIO_PAD_134, PAD_RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 166: PINMUX_CONSTANTS(GPIO_PAD_135, PAD_WATCHDOG, WATCHDOG, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 167: PINMUX_CONSTANTS(GPIO_PAD_136, PAD_AUD_CLK_MOSI, AUD_CLK_MOSI, AUD_CLK_MISO, I2S1_MCK, RES4, RES5, UFS_UNIPRO_SCL, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 168: PINMUX_CONSTANTS(GPIO_PAD_137, PAD_AUD_SYNC_MOSI, AUD_SYNC_MOSI, AUD_SYNC_MISO, I2S1_BCK, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 169: PINMUX_CONSTANTS(GPIO_PAD_138, PAD_AUD_DAT_MOSI0, AUD_DAT_MOSI0, AUD_DAT_MISO0, I2S1_LRCK, RES4, RES5, RES6, DBG_MON_B24), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 170: PINMUX_CONSTANTS(GPIO_PAD_139, PAD_AUD_DAT_MOSI1, AUD_DAT_MOSI1, AUD_DAT_MISO1, I2S1_DO, RES4, RES5, UFS_MPHY_SDA, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 171: PINMUX_CONSTANTS(GPIO_PAD_140, PAD_AUD_CLK_MISO, AUD_CLK_MISO, AUD_CLK_MOSI, I2S0_MCK, RES4, RES5, UFS_UNIPRO_SDA, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 172: PINMUX_CONSTANTS(GPIO_PAD_141, PAD_AUD_SYNC_MISO, AUD_SYNC_MISO, AUD_SYNC_MOSI, I2S0_BCK, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 173: PINMUX_CONSTANTS(GPIO_PAD_142, PAD_AUD_DAT_MISO0, AUD_DAT_MISO0, AUD_DAT_MOSI0, I2S0_LRCK, VOW_DAT_MISO, RES5, RES6, DBG_MON_B25), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 174: PINMUX_CONSTANTS(GPIO_PAD_143, PAD_AUD_DAT_MISO1, AUD_DAT_MISO1, AUD_DAT_MOSI1, I2S0_DI, VOW_CLK_MISO, RES5, UFS_MPHY_SCL, DBG_MON_B26), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 175: PINMUX_CONSTANTS(GPIO_PAD_144, PAD_PWRAP_SPI0_MI, PWRAP_SPI0_MI, PWRAP_SPI0_MO, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 176: PINMUX_CONSTANTS(GPIO_PAD_145, PAD_PWRAP_SPI0_CSN, PWRAP_SPI0_CSN, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 177: PINMUX_CONSTANTS(GPIO_PAD_146, PAD_PWRAP_SPI0_MO, PWRAP_SPI0_MO, PWRAP_SPI0_MI, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 178: PINMUX_CONSTANTS(GPIO_PAD_147, PAD_PWRAP_SPI0_CK, PWRAP_SPI0_CK, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 179: PINMUX_CONSTANTS(GPIO_PAD_148, PAD_SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 180: PINMUX_CONSTANTS(GPIO_PAD_149, PAD_SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 181: PINMUX_CONSTANTS(GPIO_PAD_150, PAD_PERIPHERAL_EN0, PWM_A, CMFLASH, CLKM0, RES4, RES5, RES6, DBG_MON_B30), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 182: PINMUX_CONSTANTS(GPIO_PAD_151, PAD_PERIPHERAL_EN1, PWM_B, CMVREF0, CLKM1, RES4, RES5, RES6, DBG_MON_B20), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 183: PINMUX_CONSTANTS(GPIO_PAD_152, PAD_PERIPHERAL_EN2, PWM_C, CMFLASH, CLKM2, RES4, RES5, RES6, DBG_MON_B21), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 184: PINMUX_CONSTANTS(GPIO_PAD_153, PAD_PERIPHERAL_EN3, PWM_A, CMVREF0, CLKM3, RES4, RES5, RES6, DBG_MON_B22), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 185: PINMUX_CONSTANTS(GPIO_PAD_154, PAD_SCP_VREQ_VAO, SCP_VREQ_VAO, DVFSRC_EXT_REQ, RES3, RES4, RES5, RES6, DBG_MON_B18), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 186: PINMUX_CONSTANTS(GPIO_PAD_155, PAD_ANT_SEL0, ANT_SEL0, DVFSRC_EXT_REQ, CMVREF1, RES4, RES5, RES6, SCP_JTAG_TDI), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 187: PINMUX_CONSTANTS(GPIO_PAD_156, PAD_ANT_SEL1, ANT_SEL1, SRCLKENAI0, SCL6, KPCOL2, IDDIG, RES6, SCP_JTAG_TCK), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 188: PINMUX_CONSTANTS(GPIO_PAD_157, PAD_ANT_SEL2, ANT_SEL2, SRCLKENAI1, SDA6, KPROW2, USB_DRVVBUS, RES6, SCP_JTAG_TRSTN), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 189: PINMUX_CONSTANTS(GPIO_PAD_158, PAD_PERIPHERAL_EN6, ANT_SEL3, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 190: PINMUX_CONSTANTS(GPIO_PAD_159, PAD_PERIPHERAL_EN7, ANT_SEL4, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 191: PINMUX_CONSTANTS(GPIO_PAD_160, PAD_PERIPHERAL_EN8, ANT_SEL5, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 192: PINMUX_CONSTANTS(GPIO_PAD_161, PAD_SPI1_MI, SPI1_A_MI, SCP_SPI1_MI, IDDIG, ANT_SEL6, KPCOL2, PTA_RXD, DBG_MON_B19), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 193: PINMUX_CONSTANTS(GPIO_PAD_162, PAD_SPI1_CSB, SPI1_A_CSB, SCP_SPI1_CS, USB_DRVVBUS, ANT_SEL5, KPROW2, PTA_TXD, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 194: PINMUX_CONSTANTS(GPIO_PAD_163, PAD_SPI1_MO, SPI1_A_MO, SCP_SPI1_MO, SDA1, ANT_SEL4, CMMCLK2, DMIC_CLK, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 195: PINMUX_CONSTANTS(GPIO_PAD_164, PAD_SPI1_CLK, SPI1_A_CLK, SCP_SPI1_CK, SCL1, ANT_SEL3, CMMCLK3, DMIC_DAT, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 196: PINMUX_CONSTANTS(GPIO_PAD_165, PAD_PERIPHERAL_EN4, PWM_B, CMMCLK2, SCP_VREQ_VAO, RES4, RES5, TDM_MCK_2nd, SCP_JTAG_TDO), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 197: PINMUX_CONSTANTS(GPIO_PAD_166, PAD_PERIPHERAL_EN9, ANT_SEL6, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 198: PINMUX_CONSTANTS(GPIO_PAD_167, PAD_RFIC0_BSI_EN, RFIC0_BSI_EN, SPM_BSI_EN, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 199: PINMUX_CONSTANTS(GPIO_PAD_168, PAD_RFIC0_BSI_CK, RFIC0_BSI_CK, SPM_BSI_CK, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 200: PINMUX_CONSTANTS(GPIO_PAD_169, PAD_PERIPHERAL_EN5, PWM_C, CMMCLK3, CMVREF1, ANT_SEL7, AGPS_SYNC, TDM_BCK_2nd, SCP_JTAG_TMS), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 201: PINMUX_CONSTANTS(GPIO_PAD_170, PAD_I2S1_BCK, I2S1_BCK, I2S3_BCK, SCL7, I2S5_BCK, EXT_FRAME_SYNC, TDM_LRCK_2nd, ANT_SEL3), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 202: PINMUX_CONSTANTS(GPIO_PAD_171, PAD_I2S1_LRCK, I2S1_LRCK, I2S3_LRCK, SDA7, I2S5_LRCK, URXD1, TDM_DATA0_2nd, ANT_SEL4), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 203: PINMUX_CONSTANTS(GPIO_PAD_172, PAD_I2S1_DO, I2S1_DO, I2S3_DO, SCL8, I2S5_DO, UTXD1, TDM_DATA1_2nd, ANT_SEL5), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 204: PINMUX_CONSTANTS(GPIO_PAD_173, PAD_I2S1_MCK, I2S1_MCK, I2S3_MCK, SDA8, I2S5_MCK, UCTS0, TDM_DATA2_2nd, ANT_SEL6), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 205: PINMUX_CONSTANTS(GPIO_PAD_174, PAD_I2S2_DI, I2S2_DI, I2S0_DI, DVFSRC_EXT_REQ, I2S2_DI2, URTS0, TDM_DATA3_2nd, ANT_SEL7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 206: PINMUX_CONSTANTS(GPIO_PAD_175, PAD_PERIPHERAL_EN12, ANT_SEL7, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 207: PINMUX_CONSTANTS(GPIO_PAD_176, PAD_PERIPHERAL_EN13, RES1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 208: PINMUX_CONSTANTS(GPIO_PAD_177, PAD_PERIPHERAL_EN14, RES1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 209: PINMUX_CONSTANTS(GPIO_PAD_178, PAD_PERIPHERAL_EN10, RES1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27417/1/src/soc/mediatek/mt8183/include/soc… PS1, Line 210: PINMUX_CONSTANTS(GPIO_PAD_179, PAD_PERIPHERAL_EN11, RES1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters -- To view, visit https://review.coreboot.org/27417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a Gerrit-Change-Number: 27417 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Jul 2018 11:25:54 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mediatek: Share GPIO code among similar SOCs
by build bot (Jenkins) (Code Review) 09 Jul '18

09 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27416 ) Change subject: mediatek: Share GPIO code among similar SOCs ...................................................................... Patch Set 1: (135 comments) https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… File src/soc/mediatek/mt8173/include/soc/pinmux.h: https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 29: PINMUX_CONSTANTS(GPIO_PAD_0, EINT0, IRDA_PDN, I2S1_WS, AUD_SPDIF, UTXD0, RES5, RES6, DBG_MON_A_20), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 30: PINMUX_CONSTANTS(GPIO_PAD_1, EINT1, IRDA_RXD, I2S1_BCK, SDA5, URXD0, RES5, RES6, DBG_MON_A_21), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 31: PINMUX_CONSTANTS(GPIO_PAD_2, EINT2, IRDA_TXD, I2S1_MCK, SCL5, UTXD3, RES5, RES6, DBG_MON_A_22), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 32: PINMUX_CONSTANTS(GPIO_PAD_3, EINT3, DSI1_TE, I2S1_DO_1, SDA3, URXD3, RES5, RES6, DBG_MON_A_23), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 33: PINMUX_CONSTANTS(GPIO_PAD_4, EINT4, DISP_PWM1, I2S1_DO_2, SCL3, UCTS3, RES5, SFWP_B, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 34: PINMUX_CONSTANTS(GPIO_PAD_5, EINT5, PCM1_CLK, I2S2_WS, SPI_CK_3, URTS3, AP_MD32_JTAG_TMS, SFOUT, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 35: PINMUX_CONSTANTS(GPIO_PAD_6, EINT6, PCM1_SYNC, I2S2_BCK, SPI_MI_3, RES4, AP_MD32_JTAG_TCK, SFCS0, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 36: PINMUX_CONSTANTS(GPIO_PAD_7, EINT7, PCM1_DI, I2S2_DI_1, SPI_MO_3, RES4, AP_MD32_JTAG_TDI, SFHOLD, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 37: PINMUX_CONSTANTS(GPIO_PAD_8, EINT8, PCM1_DO, I2S2_DI_2, SPI_CS_3, AUD_SPDIF, AP_MD32_JTAG_TDO, SFIN, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 38: PINMUX_CONSTANTS(GPIO_PAD_9, EINT9, USB_DRVVBUS_P0, I2S2_MCK, RES3, USB_DRVVBUS_P1, AP_MD32_JTAG_TRST, SFCK, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 39: PINMUX_CONSTANTS(GPIO_PAD_10, EINT10, CLKM0, DSI1_TE, DISP_PWM1, PWM4, IRDA_RXD, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 40: PINMUX_CONSTANTS(GPIO_PAD_11, EINT11, CLKM1, I2S3_WS, USB_DRVVBUS_P0, PWM5, IRDA_TXD, USB_DRVVBUS_P1, DBG_MON_B_30), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 41: PINMUX_CONSTANTS(GPIO_PAD_12, EINT12, CLKM2, I2S3_BCK, SRCLKENA0, RES4, I2S2_WS, RES6, DBG_MON_B_32), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 42: PINMUX_CONSTANTS(GPIO_PAD_13, EINT13, CLKM3, I2S3_MCK, SRCLKENA0, RES4, I2S2_BCK, RES6, DBG_MON_A_32), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 43: PINMUX_CONSTANTS(GPIO_PAD_14, EINT14, CMDAT0, CMCSD0, RES3, CLKM2, RES5, RES6, DBG_MON_B_6), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 44: PINMUX_CONSTANTS(GPIO_PAD_15, EINT15, CMDAT1, CMCSD1, CMFLASH, CLKM3, RES5, RES6, DBG_MON_B_29), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 45: PINMUX_CONSTANTS(GPIO_PAD_16, IDDIG, IDDIG, CMFLASH, RES3, PWM5, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 46: PINMUX_CONSTANTS(GPIO_PAD_17, WATCHDOG, WATCHDOG_AO, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 47: PINMUX_CONSTANTS(GPIO_PAD_18, CEC, CEC, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 48: PINMUX_CONSTANTS(GPIO_PAD_19, HDMISCK, HDMISCK, HDCP_SCL, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 49: PINMUX_CONSTANTS(GPIO_PAD_20, HDMISD, HDMISD, HDCP_SDA, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 50: PINMUX_CONSTANTS(GPIO_PAD_21, HTPLG, HTPLG, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 51: PINMUX_CONSTANTS(GPIO_PAD_22, MSDC3_DAT0, MSDC3_DAT0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 52: PINMUX_CONSTANTS(GPIO_PAD_23, MSDC3_DAT1, MSDC3_DAT1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 53: PINMUX_CONSTANTS(GPIO_PAD_24, MSDC3_DAT2, MSDC3_DAT2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 54: PINMUX_CONSTANTS(GPIO_PAD_25, MSDC3_DAT3, MSDC3_DAT3, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 55: PINMUX_CONSTANTS(GPIO_PAD_26, MSDC3_CLK, MSDC3_CLK, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 56: PINMUX_CONSTANTS(GPIO_PAD_27, MSDC3_CMD, MSDC3_CMD, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 57: PINMUX_CONSTANTS(GPIO_PAD_28, MSDC3_DSL, MSDC3_DSL, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 58: PINMUX_CONSTANTS(GPIO_PAD_29, UCTS2, UCTS2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 59: PINMUX_CONSTANTS(GPIO_PAD_30, URTS2, URTS2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 60: PINMUX_CONSTANTS(GPIO_PAD_31, URXD2, URXD2, UTXD2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 61: PINMUX_CONSTANTS(GPIO_PAD_32, UTXD2, UTXD2, URXD2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 62: PINMUX_CONSTANTS(GPIO_PAD_33, DAICLK, MRG_CLK, PCM0_CLK, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 63: PINMUX_CONSTANTS(GPIO_PAD_34, DAIPCMIN, MRG_DI, PCM0_DI, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 64: PINMUX_CONSTANTS(GPIO_PAD_35, DAIPCMOUT, MRG_DO, PCM0_DO, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 65: PINMUX_CONSTANTS(GPIO_PAD_36, DAISYNC, MRG_SYNC, PCM0_SYNC, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 66: PINMUX_CONSTANTS(GPIO_PAD_37, EINT16, USB_DRVVBUS_P0, USB_DRVVBUS_P1, PWM0, PWM1, PWM2, CLKM0, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 67: PINMUX_CONSTANTS(GPIO_PAD_38, CONN_RST, USB_DRVVBUS_P0, USB_DRVVBUS_P1, RES3, RES4, RES5, CLKM1, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 68: PINMUX_CONSTANTS(GPIO_PAD_39, CM2MCLK, CM2MCLK, CMCSD0, RES3, RES4, RES5, RES6, DBG_MON_A_17), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 69: PINMUX_CONSTANTS(GPIO_PAD_40, CMPCLK, CMPCLK, CMCSK, CMCSD2, RES4, RES5, RES6, DBG_MON_A_18), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 70: PINMUX_CONSTANTS(GPIO_PAD_41, CMMCLK, CMMCLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_19), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 71: PINMUX_CONSTANTS(GPIO_PAD_42, DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 72: PINMUX_CONSTANTS(GPIO_PAD_43, SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 73: PINMUX_CONSTANTS(GPIO_PAD_44, SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 74: PINMUX_CONSTANTS(GPIO_PAD_45, SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 75: PINMUX_CONSTANTS(GPIO_PAD_46, SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 76: PINMUX_CONSTANTS(GPIO_PAD_47, RDN0_A, CMDAT2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 77: PINMUX_CONSTANTS(GPIO_PAD_48, RDP0_A, CMDAT3, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 78: PINMUX_CONSTANTS(GPIO_PAD_49, RDN1_A, CMDAT4, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 79: PINMUX_CONSTANTS(GPIO_PAD_50, RDP1_A, CMDAT5, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 80: PINMUX_CONSTANTS(GPIO_PAD_51, RCN_A, CMDAT6, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 81: PINMUX_CONSTANTS(GPIO_PAD_52, RCP_A, CMDAT7, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 82: PINMUX_CONSTANTS(GPIO_PAD_53, RDN2_A, CMDAT8, CMCSD3, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 83: PINMUX_CONSTANTS(GPIO_PAD_54, RDP2_A, CMDAT9, CMCSD2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 84: PINMUX_CONSTANTS(GPIO_PAD_55, RDN3_A, CMHSYNC, CMCSD1, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 85: PINMUX_CONSTANTS(GPIO_PAD_56, RDP3_A, CMVSYNC, CMCSD0, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 86: PINMUX_CONSTANTS(GPIO_PAD_57, MSDC0_DAT0, MSDC0_DAT0, I2S1_WS, RES3, RES4, RES5, RES6, DBG_MON_B_7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 87: PINMUX_CONSTANTS(GPIO_PAD_58, MSDC0_DAT1, MSDC0_DAT1, I2S1_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_8), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 88: PINMUX_CONSTANTS(GPIO_PAD_59, MSDC0_DAT2, MSDC0_DAT2, I2S1_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_9), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 89: PINMUX_CONSTANTS(GPIO_PAD_60, MSDC0_DAT3, MSDC0_DAT3, I2S1_DO_1, RES3, RES4, RES5, RES6, DBG_MON_B_10), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 90: PINMUX_CONSTANTS(GPIO_PAD_61, MSDC0_DAT4, MSDC0_DAT4, I2S1_DO_2, RES3, RES4, RES5, RES6, DBG_MON_B_11), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 91: PINMUX_CONSTANTS(GPIO_PAD_62, MSDC0_DAT5, MSDC0_DAT5, I2S2_WS, RES3, RES4, RES5, RES6, DBG_MON_B_12), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 92: PINMUX_CONSTANTS(GPIO_PAD_63, MSDC0_DAT6, MSDC0_DAT6, I2S2_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_13), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 93: PINMUX_CONSTANTS(GPIO_PAD_64, MSDC0_DAT7, MSDC0_DAT7, I2S2_DI_1, RES3, RES4, RES5, RES6, DBG_MON_B_14), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 94: PINMUX_CONSTANTS(GPIO_PAD_65, MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_16), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 95: PINMUX_CONSTANTS(GPIO_PAD_66, MSDC0_CMD, MSDC0_CMD, I2S2_DI_2, RES3, RES4, RES5, RES6, DBG_MON_B_15), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 96: PINMUX_CONSTANTS(GPIO_PAD_67, MSDC0_DSL, MSDC0_DSL, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_17), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 97: PINMUX_CONSTANTS(GPIO_PAD_68, MSDC0_RST, MSDC0_RSTB, I2S2_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_18), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 98: PINMUX_CONSTANTS(GPIO_PAD_69, SPI_CK, SPI_CK_0, I2S3_DO_1, PWM0, PWM5, I2S2_MCK, RES6, DBG_MON_B_19), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 99: PINMUX_CONSTANTS(GPIO_PAD_70, SPI_MI, SPI_MI_0, I2S3_DO_2, PWM1, SPI_MO_0, I2S2_DI_1, DSI1_TE, DBG_MON_B_20), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 100: PINMUX_CONSTANTS(GPIO_PAD_71, SPI_MO, SPI_MO_0, I2S3_DO_3, PWM2, SPI_MI_0, I2S2_DI_2, RES6, DBG_MON_B_21), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 101: PINMUX_CONSTANTS(GPIO_PAD_72, SPI_CS, SPI_CS_0, I2S3_DO_4, PWM3, PWM6, DISP_PWM1, RES6, DBG_MON_B_22), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 102: PINMUX_CONSTANTS(GPIO_PAD_73, MSDC1_DAT0, MSDC1_DAT0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_24), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 103: PINMUX_CONSTANTS(GPIO_PAD_74, MSDC1_DAT1, MSDC1_DAT1, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_25), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 104: PINMUX_CONSTANTS(GPIO_PAD_75, MSDC1_DAT2, MSDC1_DAT2, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_26), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 105: PINMUX_CONSTANTS(GPIO_PAD_76, MSDC1_DAT3, MSDC1_DAT3, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_27), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 106: PINMUX_CONSTANTS(GPIO_PAD_77, MSDC1_CLK, MSDC1_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_28), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 107: PINMUX_CONSTANTS(GPIO_PAD_78, MSDC1_CMD, MSDC1_CMD, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_23), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 108: PINMUX_CONSTANTS(GPIO_PAD_79, PWRAP_SPI0_MI, PWRAP_SPIMI, PWRAP_SPIMO, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 109: PINMUX_CONSTANTS(GPIO_PAD_80, PWRAP_SPI0_MO, PWRAP_SPIMO, PWRAP_SPIMI, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 110: PINMUX_CONSTANTS(GPIO_PAD_81, PWRAP_SPI0_CK, PWRAP_SPICK, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 111: PINMUX_CONSTANTS(GPIO_PAD_82, PWRAP_SPI0_CSN, PWRAP_SPICS, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 112: PINMUX_CONSTANTS(GPIO_PAD_83, AUD_CLK_MOSI, AUD_CLK_MOSI, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 113: PINMUX_CONSTANTS(GPIO_PAD_84, AUD_DAT_MISO, AUD_DAT_MISO, AUD_DAT_MOSI, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 114: PINMUX_CONSTANTS(GPIO_PAD_85, AUD_DAT_MOSI, AUD_DAT_MOSI, AUD_DAT_MISO, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 115: PINMUX_CONSTANTS(GPIO_PAD_86, RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 116: PINMUX_CONSTANTS(GPIO_PAD_87, DISP_PWM0, DISP_PWM0, DISP_PWM1, RES3, RES4, RES5, RES6, DBG_MON_B_31), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 117: PINMUX_CONSTANTS(GPIO_PAD_88, SRCLKENAI, SRCLKENAI, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 118: PINMUX_CONSTANTS(GPIO_PAD_89, SRCLKENAI2, SRCLKENAI2, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 119: PINMUX_CONSTANTS(GPIO_PAD_90, SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 120: PINMUX_CONSTANTS(GPIO_PAD_91, SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 121: PINMUX_CONSTANTS(GPIO_PAD_92, PCM_CLK, PCM1_CLK, I2S0_BCK, RES3, RES4, RES5, RES6, DBG_MON_A_24), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 122: PINMUX_CONSTANTS(GPIO_PAD_93, PCM_SYNC, PCM1_SYNC, I2S0_WS, RES3, RES4, RES5, RES6, DBG_MON_A_25), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 123: PINMUX_CONSTANTS(GPIO_PAD_94, PCM_RX, PCM1_DI, I2S0_DI, RES3, RES4, RES5, RES6, DBG_MON_A_26), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 124: PINMUX_CONSTANTS(GPIO_PAD_95, PCM_TX, PCM1_DO, I2S0_DO, RES3, RES4, RES5, RES6, DBG_MON_A_27), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 125: PINMUX_CONSTANTS(GPIO_PAD_96, URXD1, URXD1, UTXD1, RES3, RES4, RES5, RES6, DBG_MON_A_28), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 126: PINMUX_CONSTANTS(GPIO_PAD_97, UTXD1, UTXD1, URXD1, RES3, RES4, RES5, RES6, DBG_MON_A_29), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 127: PINMUX_CONSTANTS(GPIO_PAD_98, URTS1, URTS1, UCTS1, RES3, RES4, RES5, RES6, DBG_MON_A_30), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 128: PINMUX_CONSTANTS(GPIO_PAD_99, UCTS1, UCTS1, URTS1, RES3, RES4, RES5, RES6, DBG_MON_A_31), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 129: PINMUX_CONSTANTS(GPIO_PAD_100, MSDC2_DAT0, MSDC2_DAT0, RES2, USB_DRVVBUS_P0, SDA5, USB_DRVVBUS_P1, RES6, DBG_MON_B_0), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 130: PINMUX_CONSTANTS(GPIO_PAD_101, MSDC2_DAT1, MSDC2_DAT1, RES2, AUD_SPDIF, SCL5, RES5, RES6, DBG_MON_B_1), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 131: PINMUX_CONSTANTS(GPIO_PAD_102, MSDC2_DAT2, MSDC2_DAT2, RES2, UTXD0, RES4, PWM0, SPI_CK_1, DBG_MON_B_2), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 132: PINMUX_CONSTANTS(GPIO_PAD_103, MSDC2_DAT3, MSDC2_DAT3, RES2, URXD0, RES4, PWM1, SPI_MI_1, DBG_MON_B_3), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 133: PINMUX_CONSTANTS(GPIO_PAD_104, MSDC2_CLK, MSDC2_CLK, RES2, UTXD3, SDA3, PWM2, SPI_MO_1, DBG_MON_B_4), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 134: PINMUX_CONSTANTS(GPIO_PAD_105, MSDC2_CMD, MSDC2_CMD, RES2, URXD3, SCL3, PWM3, SPI_CS_1, DBG_MON_B_5), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 135: PINMUX_CONSTANTS(GPIO_PAD_106, SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 136: PINMUX_CONSTANTS(GPIO_PAD_107, SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 137: PINMUX_CONSTANTS(GPIO_PAD_108, JTMS, JTMS, MFG_JTAG_TMS, RES3, RES4, AP_MD32_JTAG_TMS, DFD_TMS, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 138: PINMUX_CONSTANTS(GPIO_PAD_109, JTCK, JTCK, MFG_JTAG_TCK, RES3, RES4, AP_MD32_JTAG_TCK, DFD_TCK, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 139: PINMUX_CONSTANTS(GPIO_PAD_110, JTDI, JTDI, MFG_JTAG_TDI, RES3, RES4, AP_MD32_JTAG_TDI, DFD_TDI, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 140: PINMUX_CONSTANTS(GPIO_PAD_111, JTDO, JTDO, MFG_JTAG_TDO, RES3, RES4, AP_MD32_JTAG_TDO, DFD_TDO, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 141: PINMUX_CONSTANTS(GPIO_PAD_112, JTRST_B, JTRST_B, MFG_JTAG_TRSTN, RES3, RES4, AP_MD32_JTAG_TRST, DFD_NTRST, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 142: PINMUX_CONSTANTS(GPIO_PAD_113, URXD0, URXD0, UTXD0, RES3, RES4, RES5, I2S2_WS, DBG_MON_A_0), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 143: PINMUX_CONSTANTS(GPIO_PAD_114, UTXD0, UTXD0, URXD0, RES3, RES4, RES5, I2S2_BCK, DBG_MON_A_1), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 144: PINMUX_CONSTANTS(GPIO_PAD_115, URTS0, URTS0, UCTS0, RES3, RES4, RES5, I2S2_MCK, DBG_MON_A_2), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 145: PINMUX_CONSTANTS(GPIO_PAD_116, UCTS0, UCTS0, URTS0, RES3, RES4, RES5, I2S2_DI_1, DBG_MON_A_3), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 146: PINMUX_CONSTANTS(GPIO_PAD_117, URXD3, URXD3, UTXD3, RES3, RES4, RES5, RES6, DBG_MON_A_9), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 147: PINMUX_CONSTANTS(GPIO_PAD_118, UTXD3, UTXD3, URXD3, RES3, RES4, RES5, RES6, DBG_MON_A_10), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 148: PINMUX_CONSTANTS(GPIO_PAD_119, KPROW0, KROW0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_11), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 149: PINMUX_CONSTANTS(GPIO_PAD_120, KPROW1, KROW1, RES2, PWM6, RES4, RES5, RES6, DBG_MON_A_12), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 150: PINMUX_CONSTANTS(GPIO_PAD_121, KPROW2, KROW2, IRDA_PDN, USB_DRVVBUS_P0, PWM4, USB_DRVVBUS_P1, RES6, DBG_MON_A_13), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 151: PINMUX_CONSTANTS(GPIO_PAD_122, KPCOL0, KCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_14), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 152: PINMUX_CONSTANTS(GPIO_PAD_123, KPCOL1, KCOL1, IRDA_RXD, PWM5, RES4, RES5, RES6, DBG_MON_A_15), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 153: PINMUX_CONSTANTS(GPIO_PAD_124, KPCOL2, KCOL2, IRDA_TXD, USB_DRVVBUS_P0, PWM3, USB_DRVVBUS_P1, RES6, DBG_MON_A_16), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 154: PINMUX_CONSTANTS(GPIO_PAD_125, SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 155: PINMUX_CONSTANTS(GPIO_PAD_126, SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 156: PINMUX_CONSTANTS(GPIO_PAD_127, LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 157: PINMUX_CONSTANTS(GPIO_PAD_128, I2S0_LRCK, I2S0_WS, I2S1_WS, I2S2_WS, RES4, SPI_CK_2, RES6, DBG_MON_A_4), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 158: PINMUX_CONSTANTS(GPIO_PAD_129, I2S0_BCK, I2S0_BCK, I2S1_BCK, I2S2_BCK, RES4, SPI_MI_2, RES6, DBG_MON_A_5), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 159: PINMUX_CONSTANTS(GPIO_PAD_130, I2S0_MCK, I2S0_MCK, I2S1_MCK, I2S2_MCK, RES4, SPI_MO_2, RES6, DBG_MON_A_6), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 160: PINMUX_CONSTANTS(GPIO_PAD_131, I2S0_DATA0, I2S0_DO, I2S1_DO_1, I2S2_DI_1, RES4, SPI_CS_2, RES6, DBG_MON_A_7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 161: PINMUX_CONSTANTS(GPIO_PAD_132, I2S0_DATA1, I2S0_DI, I2S1_DO_2, I2S2_DI_2, RES4, RES5, RES6, DBG_MON_A_8), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 162: PINMUX_CONSTANTS(GPIO_PAD_133, SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters https://review.coreboot.org/#/c/27416/1/src/soc/mediatek/mt8173/include/soc… PS1, Line 163: PINMUX_CONSTANTS(GPIO_PAD_134, SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7), line over 80 characters -- To view, visit https://review.coreboot.org/27416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Gerrit-Change-Number: 27416 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Jul 2018 11:25:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mediatek/mt8183: Add GPIO support
by Tristan Hsieh (Code Review) 09 Jul '18

09 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27417 Change subject: mediatek/mt8183: Add GPIO support ...................................................................... mediatek/mt8183: Add GPIO support This patch implements gpio_set_pull() and gpio_set_mode() to support IO config for other drivers (ex. SPI), and links the common mediatek GPIO code to implement the requested functions in src/include/gpio.h. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a Signed-off-by: jg_poxu <jg_poxu(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/gpio.h A src/soc/mediatek/mt8183/include/soc/pinmux.h 5 files changed, 555 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/27417/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 74b0ae8..b99664f 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y) bootblock-y += bootblock.c +bootblock-y += ../common/gpio.c gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += ../common/timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) @@ -8,17 +9,20 @@ endif bootblock-y += ../common/wdt.c +verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += spi.c verstage-y += ../common/timer.c verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c verstage-y += ../common/wdt.c +romstage-y += ../common/gpio.c gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += ../common/timer.c romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c romstage-y += ../common/wdt.c ramstage-y += ../common/cbmem.c emi.c +ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c new file mode 100644 index 0000000..cdb8e32 --- /dev/null +++ b/src/soc/mediatek/mt8183/gpio.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <gpio.h> + +enum { + EN_OFFSET = 0x60, + SEL_OFFSET = 0x80, +}; + +static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg = GPIO_GET_BASE(gpio) + GPIO_GET_OFFSET(gpio); + int bit = GPIO_GET_BIT(gpio); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + setbits_le32(reg, 1 << (bit + 2)); + else + clrbits_le32(reg, 1 << (bit + 2)); + } + + if (enable == GPIO_PULL_ENABLE) + clrsetbits_le32(reg, 1 << (bit + 1), 1 << bit); + else + clrbits_le32(reg, 3 << bit); +} + +static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg = GPIO_GET_BASE(gpio) + GPIO_GET_OFFSET(gpio); + int bit = GPIO_GET_BIT(gpio); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + clrbits_le32(reg + SEL_OFFSET, 1 << bit); + else + setbits_le32(reg + SEL_OFFSET, 1 << bit); + } + + if (enable == GPIO_PULL_ENABLE) + setbits_le32(reg + EN_OFFSET, 1 << bit); + else + clrbits_le32(reg + EN_OFFSET, 1 << bit); +} + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + if (GPIO_GET_FLAG(gpio)) + gpio_set_pull_pupd(gpio, enable, select); + else + gpio_set_pull_en_sel(gpio, enable, select); +} diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index a0d7f1c..f29931c 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -23,10 +23,19 @@ enum { INFRACFG_AO_BASE = IO_PHYS + 0x00001000, + GPIO_BASE = IO_PHYS + 0x00005000, SPM_BASE = IO_PHYS + 0x00006000, RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, UART0_BASE = IO_PHYS + 0x01002000, + IOCFG_RT_BASE = IO_PHYS + 0x01C50000, + IOCFG_RM_BASE = IO_PHYS + 0x01D20000, + IOCFG_RB_BASE = IO_PHYS + 0x01D30000, + IOCFG_LB_BASE = IO_PHYS + 0x01E70000, + IOCFG_LM_BASE = IO_PHYS + 0x01E80000, + IOCFG_BL_BASE = IO_PHYS + 0x01E90000, + IOCFG_LT_BASE = IO_PHYS + 0x01F20000, + IOCFG_TL_BASE = IO_PHYS + 0x01F30000, SMI_BASE = IO_PHYS + 0x04019000, }; diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h new file mode 100644 index 0000000..9897ee0 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/gpio.h @@ -0,0 +1,260 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_GPIO_H +#define SOC_MEDIATEK_MT8183_GPIO_H + +#include <soc/addressmap.h> +#include <types.h> + +enum { + MAX_GPIO_REG_BITS = 32, + MAX_GPIO_MODE_PER_REG = 8, + GPIO_MODE_BITS = 4, +}; + +enum pull_enable { + GPIO_PULL_DISABLE = 0, + GPIO_PULL_ENABLE = 1, +}; + +enum pull_select { + GPIO_PULL_DOWN = 0, + GPIO_PULL_UP = 1, +}; + +#define IOCFG_TO_GPIO_BASE(x) ((x >> 16) & 0xff) +#define GPIO_TO_IOCFG_BASE(x) ((void *)0x11000000 + ((x & 0xff) << 16)) + +#define GPIO(id, flag, bit, base, offset) \ + (((id & 0xff) << 0) | \ + ((flag & 0x7) << 8) | \ + ((bit & 0x1f) << 11) | \ + ((IOCFG_TO_GPIO_BASE(base) & 0xff) << 16) | \ + ((offset & 0xff) << 24)) + +#define GPIO_GET_ID(x) ((x >> 0) & 0xff) +#define GPIO_GET_FLAG(x) ((x >> 8) & 0x7) +#define GPIO_GET_BIT(x) ((x >> 11) & 0x1f) +#define GPIO_GET_BASE(x) (GPIO_TO_IOCFG_BASE((x >> 16) & 0xff)) +#define GPIO_GET_OFFSET(x) ((x >> 24) & 0xff) + +typedef enum { + GPIO_PAD_0 = GPIO(0, 0, 6, IOCFG_RM_BASE, 0x00), + GPIO_PAD_1 = GPIO(1, 0, 7, IOCFG_RM_BASE, 0x00), + GPIO_PAD_2 = GPIO(2, 0, 8, IOCFG_RM_BASE, 0x00), + GPIO_PAD_3 = GPIO(3, 0, 9, IOCFG_RM_BASE, 0x00), + GPIO_PAD_4 = GPIO(4, 0, 11, IOCFG_RM_BASE, 0x00), + GPIO_PAD_5 = GPIO(5, 0, 12, IOCFG_RM_BASE, 0x00), + GPIO_PAD_6 = GPIO(6, 0, 13, IOCFG_RM_BASE, 0x00), + GPIO_PAD_7 = GPIO(7, 0, 14, IOCFG_RM_BASE, 0x00), + GPIO_PAD_8 = GPIO(8, 0, 0, IOCFG_RM_BASE, 0x00), + GPIO_PAD_9 = GPIO(9, 0, 26, IOCFG_RM_BASE, 0x00), + GPIO_PAD_10 = GPIO(10, 0, 27, IOCFG_RM_BASE, 0x00), + GPIO_PAD_11 = GPIO(11, 0, 10, IOCFG_LT_BASE, 0x00), + GPIO_PAD_12 = GPIO(12, 0, 17, IOCFG_LT_BASE, 0x00), + GPIO_PAD_13 = GPIO(13, 0, 6, IOCFG_LM_BASE, 0x00), + GPIO_PAD_14 = GPIO(14, 0, 7, IOCFG_LM_BASE, 0x00), + GPIO_PAD_15 = GPIO(15, 0, 8, IOCFG_LM_BASE, 0x00), + GPIO_PAD_16 = GPIO(16, 0, 9, IOCFG_LM_BASE, 0x00), + GPIO_PAD_17 = GPIO(17, 0, 10, IOCFG_LM_BASE, 0x00), + GPIO_PAD_18 = GPIO(18, 0, 11, IOCFG_LM_BASE, 0x00), + GPIO_PAD_19 = GPIO(19, 0, 12, IOCFG_LM_BASE, 0x00), + GPIO_PAD_20 = GPIO(20, 0, 13, IOCFG_LM_BASE, 0x00), + GPIO_PAD_21 = GPIO(21, 0, 14, IOCFG_LM_BASE, 0x00), + GPIO_PAD_22 = GPIO(22, 0, 15, IOCFG_LM_BASE, 0x00), + GPIO_PAD_23 = GPIO(23, 0, 16, IOCFG_LM_BASE, 0x00), + GPIO_PAD_24 = GPIO(24, 0, 17, IOCFG_LM_BASE, 0x00), + GPIO_PAD_25 = GPIO(25, 0, 18, IOCFG_LM_BASE, 0x00), + GPIO_PAD_26 = GPIO(26, 0, 19, IOCFG_LM_BASE, 0x00), + GPIO_PAD_27 = GPIO(27, 0, 20, IOCFG_LM_BASE, 0x00), + GPIO_PAD_28 = GPIO(28, 0, 21, IOCFG_LM_BASE, 0x00), + GPIO_PAD_29 = GPIO(29, 1, 0, IOCFG_LM_BASE, 0xc0), + GPIO_PAD_30 = GPIO(30, 1, 4, IOCFG_LM_BASE, 0xc0), + GPIO_PAD_31 = GPIO(31, 1, 8, IOCFG_LM_BASE, 0xc0), + GPIO_PAD_32 = GPIO(32, 1, 12, IOCFG_LM_BASE, 0xc0), + GPIO_PAD_33 = GPIO(33, 1, 16, IOCFG_LM_BASE, 0xc0), + GPIO_PAD_34 = GPIO(34, 1, 20, IOCFG_LM_BASE, 0xc0), + GPIO_PAD_35 = GPIO(35, 1, 0, IOCFG_LB_BASE, 0xc0), + GPIO_PAD_36 = GPIO(36, 1, 4, IOCFG_LB_BASE, 0xc0), + GPIO_PAD_37 = GPIO(37, 1, 8, IOCFG_LB_BASE, 0xc0), + GPIO_PAD_38 = GPIO(38, 1, 12, IOCFG_LB_BASE, 0xc0), + GPIO_PAD_39 = GPIO(39, 1, 16, IOCFG_LB_BASE, 0xc0), + GPIO_PAD_40 = GPIO(40, 1, 20, IOCFG_LB_BASE, 0xc0), + GPIO_PAD_41 = GPIO(41, 1, 24, IOCFG_LB_BASE, 0xc0), + GPIO_PAD_42 = GPIO(42, 1, 28, IOCFG_LB_BASE, 0xc0), + GPIO_PAD_43 = GPIO(43, 0, 8, IOCFG_LB_BASE, 0x00), + GPIO_PAD_44 = GPIO(44, 0, 9, IOCFG_LB_BASE, 0x00), + GPIO_PAD_45 = GPIO(45, 0, 10, IOCFG_LB_BASE, 0x00), + GPIO_PAD_46 = GPIO(46, 0, 11, IOCFG_LB_BASE, 0x00), + GPIO_PAD_47 = GPIO(47, 0, 12, IOCFG_LB_BASE, 0x00), + GPIO_PAD_48 = GPIO(48, 0, 13, IOCFG_LB_BASE, 0x00), + GPIO_PAD_49 = GPIO(49, 0, 14, IOCFG_LB_BASE, 0x00), + GPIO_PAD_50 = GPIO(50, 0, 0, IOCFG_BL_BASE, 0x00), + GPIO_PAD_51 = GPIO(51, 0, 1, IOCFG_BL_BASE, 0x00), + GPIO_PAD_52 = GPIO(52, 0, 2, IOCFG_BL_BASE, 0x00), + GPIO_PAD_53 = GPIO(53, 0, 3, IOCFG_BL_BASE, 0x00), + GPIO_PAD_54 = GPIO(54, 0, 4, IOCFG_BL_BASE, 0x00), + GPIO_PAD_55 = GPIO(55, 0, 5, IOCFG_BL_BASE, 0x00), + GPIO_PAD_56 = GPIO(56, 0, 6, IOCFG_BL_BASE, 0x00), + GPIO_PAD_57 = GPIO(57, 0, 7, IOCFG_BL_BASE, 0x00), + GPIO_PAD_58 = GPIO(58, 0, 8, IOCFG_BL_BASE, 0x00), + GPIO_PAD_59 = GPIO(59, 0, 9, IOCFG_BL_BASE, 0x00), + GPIO_PAD_60 = GPIO(60, 0, 10, IOCFG_BL_BASE, 0x00), + GPIO_PAD_61 = GPIO(61, 0, 0, IOCFG_RB_BASE, 0x00), + GPIO_PAD_62 = GPIO(62, 0, 1, IOCFG_RB_BASE, 0x00), + GPIO_PAD_63 = GPIO(63, 0, 2, IOCFG_RB_BASE, 0x00), + GPIO_PAD_64 = GPIO(64, 0, 3, IOCFG_RB_BASE, 0x00), + GPIO_PAD_65 = GPIO(65, 0, 4, IOCFG_RB_BASE, 0x00), + GPIO_PAD_66 = GPIO(66, 0, 5, IOCFG_RB_BASE, 0x00), + GPIO_PAD_67 = GPIO(67, 0, 6, IOCFG_RB_BASE, 0x00), + GPIO_PAD_68 = GPIO(68, 0, 7, IOCFG_RB_BASE, 0x00), + GPIO_PAD_69 = GPIO(69, 0, 8, IOCFG_RB_BASE, 0x00), + GPIO_PAD_70 = GPIO(70, 0, 9, IOCFG_RB_BASE, 0x00), + GPIO_PAD_71 = GPIO(71, 0, 10, IOCFG_RB_BASE, 0x00), + GPIO_PAD_72 = GPIO(72, 0, 11, IOCFG_RB_BASE, 0x00), + GPIO_PAD_73 = GPIO(73, 0, 12, IOCFG_RB_BASE, 0x00), + GPIO_PAD_74 = GPIO(74, 0, 13, IOCFG_RB_BASE, 0x00), + GPIO_PAD_75 = GPIO(75, 0, 14, IOCFG_RB_BASE, 0x00), + GPIO_PAD_76 = GPIO(76, 0, 15, IOCFG_RB_BASE, 0x00), + GPIO_PAD_77 = GPIO(77, 0, 16, IOCFG_RB_BASE, 0x00), + GPIO_PAD_78 = GPIO(78, 0, 17, IOCFG_RB_BASE, 0x00), + GPIO_PAD_79 = GPIO(79, 0, 18, IOCFG_RB_BASE, 0x00), + GPIO_PAD_80 = GPIO(80, 0, 19, IOCFG_RB_BASE, 0x00), + GPIO_PAD_81 = GPIO(81, 0, 20, IOCFG_RB_BASE, 0x00), + GPIO_PAD_82 = GPIO(82, 0, 21, IOCFG_RB_BASE, 0x00), + GPIO_PAD_83 = GPIO(83, 0, 22, IOCFG_RB_BASE, 0x00), + GPIO_PAD_84 = GPIO(84, 0, 23, IOCFG_RB_BASE, 0x00), + GPIO_PAD_85 = GPIO(85, 0, 24, IOCFG_RB_BASE, 0x00), + GPIO_PAD_86 = GPIO(86, 0, 25, IOCFG_RB_BASE, 0x00), + GPIO_PAD_87 = GPIO(87, 0, 26, IOCFG_RB_BASE, 0x00), + GPIO_PAD_88 = GPIO(88, 0, 27, IOCFG_RB_BASE, 0x00), + GPIO_PAD_89 = GPIO(89, 0, 24, IOCFG_RM_BASE, 0x00), + GPIO_PAD_90 = GPIO(90, 0, 1, IOCFG_RM_BASE, 0x00), + GPIO_PAD_91 = GPIO(91, 1, 0, IOCFG_RM_BASE, 0xc0), + GPIO_PAD_92 = GPIO(92, 1, 4, IOCFG_RM_BASE, 0xc0), + GPIO_PAD_93 = GPIO(93, 1, 8, IOCFG_RM_BASE, 0xc0), + GPIO_PAD_94 = GPIO(94, 1, 12, IOCFG_RM_BASE, 0xc0), + GPIO_PAD_95 = GPIO(95, 0, 15, IOCFG_RM_BASE, 0x00), + GPIO_PAD_96 = GPIO(96, 0, 17, IOCFG_RM_BASE, 0x00), + GPIO_PAD_97 = GPIO(97, 0, 18, IOCFG_RM_BASE, 0x00), + GPIO_PAD_98 = GPIO(98, 0, 19, IOCFG_RM_BASE, 0x00), + GPIO_PAD_99 = GPIO(99, 0, 20, IOCFG_RM_BASE, 0x00), + GPIO_PAD_100 = GPIO(100, 0, 21, IOCFG_RM_BASE, 0x00), + GPIO_PAD_101 = GPIO(101, 0, 22, IOCFG_RM_BASE, 0x00), + GPIO_PAD_102 = GPIO(102, 0, 23, IOCFG_RM_BASE, 0x00), + GPIO_PAD_103 = GPIO(103, 0, 28, IOCFG_RM_BASE, 0x00), + GPIO_PAD_104 = GPIO(104, 0, 29, IOCFG_RM_BASE, 0x00), + GPIO_PAD_105 = GPIO(105, 0, 30, IOCFG_RM_BASE, 0x00), + GPIO_PAD_106 = GPIO(106, 0, 31, IOCFG_RM_BASE, 0x00), + GPIO_PAD_107 = GPIO(107, 0, 0, IOCFG_RT_BASE, 0x00), + GPIO_PAD_108 = GPIO(108, 0, 1, IOCFG_RT_BASE, 0x00), + GPIO_PAD_109 = GPIO(109, 0, 2, IOCFG_RT_BASE, 0x00), + GPIO_PAD_110 = GPIO(110, 0, 3, IOCFG_RT_BASE, 0x00), + GPIO_PAD_111 = GPIO(111, 0, 4, IOCFG_RT_BASE, 0x00), + GPIO_PAD_112 = GPIO(112, 0, 5, IOCFG_RT_BASE, 0x00), + GPIO_PAD_113 = GPIO(113, 0, 6, IOCFG_RT_BASE, 0x00), + GPIO_PAD_114 = GPIO(114, 0, 7, IOCFG_RT_BASE, 0x00), + GPIO_PAD_115 = GPIO(115, 0, 8, IOCFG_RT_BASE, 0x00), + GPIO_PAD_116 = GPIO(116, 0, 9, IOCFG_RT_BASE, 0x00), + GPIO_PAD_117 = GPIO(117, 0, 10, IOCFG_RT_BASE, 0x00), + GPIO_PAD_118 = GPIO(118, 0, 11, IOCFG_RT_BASE, 0x00), + GPIO_PAD_119 = GPIO(119, 0, 12, IOCFG_RT_BASE, 0x00), + GPIO_PAD_120 = GPIO(120, 0, 13, IOCFG_RT_BASE, 0x00), + GPIO_PAD_121 = GPIO(121, 0, 14, IOCFG_RT_BASE, 0x00), + GPIO_PAD_122 = GPIO(122, 1, 0, IOCFG_TL_BASE, 0xc0), + GPIO_PAD_123 = GPIO(123, 1, 4, IOCFG_TL_BASE, 0xc0), + GPIO_PAD_124 = GPIO(124, 1, 8, IOCFG_TL_BASE, 0xc0), + GPIO_PAD_125 = GPIO(125, 1, 12, IOCFG_TL_BASE, 0xc0), + GPIO_PAD_126 = GPIO(126, 1, 16, IOCFG_TL_BASE, 0xc0), + GPIO_PAD_127 = GPIO(127, 1, 20, IOCFG_TL_BASE, 0xc0), + GPIO_PAD_128 = GPIO(128, 1, 24, IOCFG_TL_BASE, 0xc0), + GPIO_PAD_129 = GPIO(129, 1, 28, IOCFG_TL_BASE, 0xc0), + GPIO_PAD_130 = GPIO(130, 1, 0, IOCFG_TL_BASE, 0xd0), + GPIO_PAD_131 = GPIO(131, 1, 4, IOCFG_TL_BASE, 0xd0), + GPIO_PAD_132 = GPIO(132, 1, 8, IOCFG_TL_BASE, 0xd0), + GPIO_PAD_133 = GPIO(133, 1, 12, IOCFG_TL_BASE, 0xd0), + GPIO_PAD_134 = GPIO(134, 0, 0, IOCFG_LT_BASE, 0x00), + GPIO_PAD_135 = GPIO(135, 0, 1, IOCFG_LT_BASE, 0x00), + GPIO_PAD_136 = GPIO(136, 0, 2, IOCFG_LT_BASE, 0x00), + GPIO_PAD_137 = GPIO(137, 0, 3, IOCFG_LT_BASE, 0x00), + GPIO_PAD_138 = GPIO(138, 0, 4, IOCFG_LT_BASE, 0x00), + GPIO_PAD_139 = GPIO(139, 0, 5, IOCFG_LT_BASE, 0x00), + GPIO_PAD_140 = GPIO(140, 0, 6, IOCFG_LT_BASE, 0x00), + GPIO_PAD_141 = GPIO(141, 0, 7, IOCFG_LT_BASE, 0x00), + GPIO_PAD_142 = GPIO(142, 0, 8, IOCFG_LT_BASE, 0x00), + GPIO_PAD_143 = GPIO(143, 0, 9, IOCFG_LT_BASE, 0x00), + GPIO_PAD_144 = GPIO(144, 0, 11, IOCFG_LT_BASE, 0x00), + GPIO_PAD_145 = GPIO(145, 0, 12, IOCFG_LT_BASE, 0x00), + GPIO_PAD_146 = GPIO(146, 0, 13, IOCFG_LT_BASE, 0x00), + GPIO_PAD_147 = GPIO(147, 0, 14, IOCFG_LT_BASE, 0x00), + GPIO_PAD_148 = GPIO(148, 0, 15, IOCFG_LT_BASE, 0x00), + GPIO_PAD_149 = GPIO(149, 0, 16, IOCFG_LT_BASE, 0x00), + GPIO_PAD_150 = GPIO(150, 0, 18, IOCFG_LT_BASE, 0x00), + GPIO_PAD_151 = GPIO(151, 0, 19, IOCFG_LT_BASE, 0x00), + GPIO_PAD_152 = GPIO(152, 0, 20, IOCFG_LT_BASE, 0x00), + GPIO_PAD_153 = GPIO(153, 0, 21, IOCFG_LT_BASE, 0x00), + GPIO_PAD_154 = GPIO(154, 0, 22, IOCFG_LT_BASE, 0x00), + GPIO_PAD_155 = GPIO(155, 0, 23, IOCFG_LT_BASE, 0x00), + GPIO_PAD_156 = GPIO(156, 0, 24, IOCFG_LT_BASE, 0x00), + GPIO_PAD_157 = GPIO(157, 0, 25, IOCFG_LT_BASE, 0x00), + GPIO_PAD_158 = GPIO(158, 0, 26, IOCFG_LT_BASE, 0x00), + GPIO_PAD_159 = GPIO(159, 0, 27, IOCFG_LT_BASE, 0x00), + GPIO_PAD_160 = GPIO(160, 0, 28, IOCFG_LT_BASE, 0x00), + GPIO_PAD_161 = GPIO(161, 0, 0, IOCFG_LM_BASE, 0x00), + GPIO_PAD_162 = GPIO(162, 0, 1, IOCFG_LM_BASE, 0x00), + GPIO_PAD_163 = GPIO(163, 0, 2, IOCFG_LM_BASE, 0x00), + GPIO_PAD_164 = GPIO(164, 0, 3, IOCFG_LM_BASE, 0x00), + GPIO_PAD_165 = GPIO(165, 0, 4, IOCFG_LM_BASE, 0x00), + GPIO_PAD_166 = GPIO(166, 0, 5, IOCFG_LM_BASE, 0x00), + GPIO_PAD_167 = GPIO(167, 0, 11, IOCFG_BL_BASE, 0x00), + GPIO_PAD_168 = GPIO(168, 0, 12, IOCFG_BL_BASE, 0x00), + GPIO_PAD_169 = GPIO(169, 0, 13, IOCFG_BL_BASE, 0x00), + GPIO_PAD_170 = GPIO(170, 0, 14, IOCFG_BL_BASE, 0x00), + GPIO_PAD_171 = GPIO(171, 0, 15, IOCFG_BL_BASE, 0x00), + GPIO_PAD_172 = GPIO(172, 0, 16, IOCFG_BL_BASE, 0x00), + GPIO_PAD_173 = GPIO(173, 0, 17, IOCFG_BL_BASE, 0x00), + GPIO_PAD_174 = GPIO(174, 0, 18, IOCFG_BL_BASE, 0x00), + GPIO_PAD_175 = GPIO(175, 0, 19, IOCFG_BL_BASE, 0x00), + GPIO_PAD_176 = GPIO(176, 0, 20, IOCFG_BL_BASE, 0x00), + GPIO_PAD_177 = GPIO(177, 0, 10, IOCFG_RM_BASE, 0x00), + GPIO_PAD_178 = GPIO(178, 0, 16, IOCFG_RM_BASE, 0x00), + GPIO_PAD_179 = GPIO(179, 0, 25, IOCFG_RM_BASE, 0x00), +} gpio_t; + +struct val_regs { + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t align; +}; + +struct gpio_regs { + struct val_regs dir[6]; + uint8_t rsv00[160]; + struct val_regs dout[6]; + uint8_t rsv01[160]; + struct val_regs din[6]; + uint8_t rsv02[160]; + struct val_regs mode[23]; +}; + +static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select); +void gpio_set_mode(gpio_t gpio, int mode); + +#endif diff --git a/src/soc/mediatek/mt8183/include/soc/pinmux.h b/src/soc/mediatek/mt8183/include/soc/pinmux.h new file mode 100644 index 0000000..56b3fe9 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/pinmux.h @@ -0,0 +1,213 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef SOC_MEDIATEK_MT8183_PINMUX_H +#define SOC_MEDIATEK_MT8183_PINMUX_H + +#include <soc/gpio.h> + +#define PINMUX_CONSTANTS(index, name, func1, func2, func3, func4, func5, func6, func7) \ + name = index, \ + name##_FUNC_##func1 = 1, \ + name##_FUNC_##func2 = 2, \ + name##_FUNC_##func3 = 3, \ + name##_FUNC_##func4 = 4, \ + name##_FUNC_##func5 = 5, \ + name##_FUNC_##func6 = 6, \ + name##_FUNC_##func7 = 7 + +enum { + PINMUX_CONSTANTS(GPIO_PAD_0, PAD_EINT0, MRG_SYNC, PCM0_SYNC, TP_GPIO0_AO, SRCLKENAI0, SCP_SPI2_CS, I2S3_MCK, SPI2_CSB), + PINMUX_CONSTANTS(GPIO_PAD_1, PAD_EINT1, MRG_CLK, PCM0_CLK, TP_GPIO1_AO, CLKM3, SCP_SPI2_MO, I2S3_BCK, SPI2_MO), + PINMUX_CONSTANTS(GPIO_PAD_2, PAD_EINT2, MRG_DO, PCM0_DO, TP_GPIO2_AO, SCL6, SCP_SPI2_CK, I2S3_LRCK, SPI2_CLK), + PINMUX_CONSTANTS(GPIO_PAD_3, PAD_EINT3, MRG_DI, PCM0_DI, TP_GPIO3_AO, SDA6, TDM_MCK, I2S3_DO, SCP_VREQ_VAO), + PINMUX_CONSTANTS(GPIO_PAD_4, PAD_EINT4, PWM_B, I2S0_MCK, SSPM_UTXD_AO, MD_URXD1, TDM_BCK, TP_GPIO4_AO, DAP_MD32_SWD), + PINMUX_CONSTANTS(GPIO_PAD_5, PAD_EINT5, PWM_C, I2S0_BCK, SSPM_URXD_AO, MD_UTXD1, TDM_LRCK, TP_GPIO5_AO, DAP_MD32_SWCK), + PINMUX_CONSTANTS(GPIO_PAD_6, PAD_EINT6, PWM_A, I2S0_LRCK, IDDIG, MD_URXD0, TDM_DATA0, TP_GPIO6_AO, CMFLASH), + PINMUX_CONSTANTS(GPIO_PAD_7, PAD_EINT7, SPI1_B_MI, I2S0_DI, USB_DRVVBUS, MD_UTXD0, TDM_DATA1, TP_GPIO7_AO, DVFSRC_EXT_REQ), + PINMUX_CONSTANTS(GPIO_PAD_8, PAD_EINT8, SPI1_B_CSB, ANT_SEL3, SCL7, CONN_MCU_TRST_B, TDM_DATA2, MD_INT0, JTRSTN_SEL1), + PINMUX_CONSTANTS(GPIO_PAD_9, PAD_EINT9, SPI1_B_MO, ANT_SEL4, CMMCLK2, CONN_MCU_DBGACK_N, SSPM_JTAG_TRSTN, IO_JTAG_TRSTN, DBG_MON_B10), + PINMUX_CONSTANTS(GPIO_PAD_10, PAD_EINT10, SPI1_B_CLK, ANT_SEL5, CMMCLK3, CONN_MCU_DBGI_N, TDM_DATA3, EXT_FRAME_SYNC, DBG_MON_B11), + PINMUX_CONSTANTS(GPIO_PAD_11, PAD_SCL6, TP_URXD1_AO, IDDIG, SCL6, UCTS1, UCTS0, SRCLKENAI1, I2S5_MCK), + PINMUX_CONSTANTS(GPIO_PAD_12, PAD_SDA6, TP_UTXD1_AO, USB_DRVVBUS, SDA6, URTS1, URTS0, I2S2_DI2, I2S5_BCK), + PINMUX_CONSTANTS(GPIO_PAD_13, PAD_DPI_D0, DBPI_D0, SPI5_MI, PCM0_SYNC, MD_URXD0, ANT_SEL3, I2S0_MCK, DBG_MON_B15), + PINMUX_CONSTANTS(GPIO_PAD_14, PAD_DPI_D1, DBPI_D1, SPI5_CSB, PCM0_CLK, MD_UTXD0, ANT_SEL4, I2S0_BCK, DBG_MON_B16), + PINMUX_CONSTANTS(GPIO_PAD_15, PAD_DPI_D2, DBPI_D2, SPI5_MO, PCM0_DO, MD_URXD1, ANT_SEL5, I2S0_LRCK, DBG_MON_B17), + PINMUX_CONSTANTS(GPIO_PAD_16, PAD_DPI_D3, DBPI_D3, SPI5_CLK, PCM0_DI, MD_UTXD1, ANT_SEL6, I2S0_DI, DBG_MON_B23), + PINMUX_CONSTANTS(GPIO_PAD_17, PAD_DPI_D4, DBPI_D4, SPI4_MI, CONN_MCU_TRST_B, MD_INT0, ANT_SEL7, I2S3_MCK, DBG_MON_A1), + PINMUX_CONSTANTS(GPIO_PAD_18, PAD_DPI_D5, DBPI_D5, SPI4_CSB, CONN_MCU_DBGI_N, MD_INT0, SCP_VREQ_VAO, I2S3_BCK, DBG_MON_A2), + PINMUX_CONSTANTS(GPIO_PAD_19, PAD_DPI_D6, DBPI_D6, SPI4_MO, CONN_MCU_TDO, MD_INT2_C2K_UIM1_HOT_PLUG, URXD1, I2S3_LRCK, DBG_MON_A3), + PINMUX_CONSTANTS(GPIO_PAD_20, PAD_DPI_D7, DBPI_D7, SPI4_CLK, CONN_MCU_DBGACK_N, MD_INT1_C2K_UIM0_HOT_PLUG, UTXD1, I2S3_DO, DBG_MON_A19), + PINMUX_CONSTANTS(GPIO_PAD_21, PAD_DPI_D8, DBPI_D8, SPI3_MI, CONN_MCU_TMS, DAP_MD32_SWD, CONN_MCU_AICE_TMSC, I2S2_MCK, DBG_MON_B5), + PINMUX_CONSTANTS(GPIO_PAD_22, PAD_DPI_D9, DBPI_D9, SPI3_CSB, CONN_MCU_TCK, DAP_MD32_SWCK, CONN_MCU_AICE_TCKC, I2S2_BCK, DBG_MON_B6), + PINMUX_CONSTANTS(GPIO_PAD_23, PAD_DPI_D10, DBPI_D10, SPI3_MO, CONN_MCU_TDI, UCTS1, EXT_FRAME_SYNC, I2S2_LRCK, DBG_MON_B7), + PINMUX_CONSTANTS(GPIO_PAD_24, PAD_DPI_D11, DBPI_D11, SPI3_CLK, SRCLKENAI0, URTS1, IO_JTAG_TCK, I2S2_DI, DBG_MON_B31), + PINMUX_CONSTANTS(GPIO_PAD_25, PAD_DPI_HSYNC, DBPI_HSYNC, ANT_SEL0, SCL6, KPCOL2, IO_JTAG_TMS, I2S1_MCK, DBG_MON_B0), + PINMUX_CONSTANTS(GPIO_PAD_26, PAD_DPI_VSYNC, DBPI_VSYNC, ANT_SEL1, SDA6, KPROW2, IO_JTAG_TDI, I2S1_BCK, DBG_MON_B1), + PINMUX_CONSTANTS(GPIO_PAD_27, PAD_DPI_DE, DBPI_DE, ANT_SEL2, SCL7, DMIC_CLK, IO_JTAG_TDO, I2S1_LRCK, DBG_MON_B9), + PINMUX_CONSTANTS(GPIO_PAD_28, PAD_DPI_CK, DBPI_CK, DVFSRC_EXT_REQ, SDA7, DMIC_DAT, IO_JTAG_TRSTN, I2S1_DO, DBG_MON_B32), + PINMUX_CONSTANTS(GPIO_PAD_29, PAD_MSDC1_CLK, MSDC1_CLK, IO_JTAG_TCK, UDI_TCK, CONN_DSP_JCK, SSPM_JTAG_TCK, PCM1_CLK, DBG_MON_A6), + PINMUX_CONSTANTS(GPIO_PAD_30, PAD_MSDC1_DAT3, MSDC1_DAT3, DAP_MD32_SWD, CONN_MCU_AICE_TMSC, CONN_DSP_JINTP, SSPM_JTAG_TRSTN, PCM1_DI, DBG_MON_A7), + PINMUX_CONSTANTS(GPIO_PAD_31, PAD_MSDC1_CMD, MSDC1_CMD, IO_JTAG_TMS, UDI_TMS, CONN_DSP_JMS, SSPM_JTAG_TMS, PCM1_SYNC, DBG_MON_A8), + PINMUX_CONSTANTS(GPIO_PAD_32, PAD_MSDC1_DAT0, MSDC1_DAT0, IO_JTAG_TDI, UDI_TDI, CONN_DSP_JDI, SSPM_JTAG_TDI, PCM1_DO0, DBG_MON_A9), + PINMUX_CONSTANTS(GPIO_PAD_33, PAD_MSDC1_DAT2, MSDC1_DAT2, IO_JTAG_TRSTN, UDI_NTRST, DAP_MD32_SWCK, CONN_MCU_AICE_TCKC, PCM1_DO2, DBG_MON_A10), + PINMUX_CONSTANTS(GPIO_PAD_34, PAD_MSDC1_DAT1, MSDC1_DAT1, IO_JTAG_TDO, UDI_TDO, CONN_DSP_JDO, SSPM_JTAG_TDO, PCM1_DO1, DBG_MON_A11), + PINMUX_CONSTANTS(GPIO_PAD_35, PAD_SIM2_SIO, MD1_SIM2_SIO, CCU_JTAG_TDO, MD1_SIM1_SIO, RES4, SCP_JTAG_TDO, CONN_DSP_JMS, DBG_MON_A28), + PINMUX_CONSTANTS(GPIO_PAD_36, PAD_SIM2_SRST, MD1_SIM2_SRST, CCU_JTAG_TMS, MD1_SIM1_SRST, CONN_MCU_AICE_TMSC, SCP_JTAG_TMS, CONN_DSP_JINTP, DBG_MON_A29), + PINMUX_CONSTANTS(GPIO_PAD_37, PAD_SIM2_SCLK, MD1_SIM2_SCLK, CCU_JTAG_TDI, MD1_SIM1_SCLK, RES4, SCP_JTAG_TDI, CONN_DSP_JDO, DBG_MON_A30), + PINMUX_CONSTANTS(GPIO_PAD_38, PAD_SIM1_SCLK, MD1_SIM1_SCLK, RES2, MD1_SIM2_SCLK, CONN_MCU_AICE_TCKC, RES5, RES6, DBG_MON_A20), + PINMUX_CONSTANTS(GPIO_PAD_39, PAD_SIM1_SRST, MD1_SIM1_SRST, CCU_JTAG_TCK, MD1_SIM2_SRST, RES4, SCP_JTAG_TCK, CONN_DSP_JCK, DBG_MON_A31), + PINMUX_CONSTANTS(GPIO_PAD_40, PAD_SIM1_SIO, MD1_SIM1_SIO, CCU_JTAG_TRST, MD1_SIM2_SIO, RES4, SCP_JTAG_TRSTN, CONN_DSP_JDI, DBG_MON_A32), + PINMUX_CONSTANTS(GPIO_PAD_41, PAD_IDDIG, IDDIG, URXD1, UCTS0, SSPM_UTXD_AO, EXT_FRAME_SYNC, DMIC_CLK, RES7), + PINMUX_CONSTANTS(GPIO_PAD_42, PAD_DRVBUS, USB_DRVVBUS, UTXD1, URTS0, SSPM_URXD_AO, EXT_FRAME_SYNC, DMIC_DAT, RES7), + PINMUX_CONSTANTS(GPIO_PAD_43, PAD_DISP_PWM, DISP_PWM, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_44, PAD_DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_45, PAD_LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_46, PAD_INT_SIM2, MD_INT2_C2K_UIM1_HOT_PLUG, URXD1, UCTS1, CCU_UTXD_AO, TP_UCTS1_AO, IDDIG, I2S5_LRCK), + PINMUX_CONSTANTS(GPIO_PAD_47, PAD_INT_SIM1, MD_INT1_C2K_UIM0_HOT_PLUG, UTXD1, URTS1, CCU_URXD_AO, TP_URTS1_AO, USB_DRVVBUS, I2S5_DO), + PINMUX_CONSTANTS(GPIO_PAD_48, PAD_SCL5, SCL5, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_49, PAD_SDA5, SDA5, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_50, PAD_SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_51, PAD_SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_52, PAD_BPI_ANT2, BPI_ANT2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_53, PAD_BPI_ANT0, BPI_ANT0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_54, PAD_BPI_OLAT1, BPI_OLAT1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_55, PAD_BPI_BUS8, BPI_BUS8, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_56, PAD_BPI_BUS9, BPI_BUS9, SCL_6306, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_57, PAD_BPI_BUS10, BPI_BUS10, SDA_6306, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_58, PAD_RFIC0_BSI_D2, RFIC0_BSI_D2, SPM_BSI_D2, PWM_B, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_59, PAD_RFIC0_BSI_D1, RFIC0_BSI_D1, SPM_BSI_D1, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_60, PAD_RFIC0_BSI_D0, RFIC0_BSI_D0, SPM_BSI_D0, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_61, PAD_MISC_BSI_DO_1, MIPI1_SDATA, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_62, PAD_MISC_BSI_CK_1, MIPI1_SCLK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_63, PAD_MISC_BSI_DO_0, MIPI0_SDATA, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_64, PAD_MISC_BSI_CK_0, MIPI0_SCLK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_65, PAD_MISC_BSI_DO_3, MIPI3_SDATA, BPI_OLAT2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_66, PAD_MISC_BSI_CK_3, MIPI3_SCLK, BPI_OLAT3, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_67, PAD_MISC_BSI_DO_2, MIPI2_SDATA, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_68, PAD_MISC_BSI_CK_2, MIPI2_SCLK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_69, PAD_BPI_BUS7, BPI_BUS7, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_70, PAD_BPI_BUS6, BPI_BUS6, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_71, PAD_BPI_BUS5, BPI_BUS5, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_72, PAD_BPI_BUS4, BPI_BUS4, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_73, PAD_BPI_BUS3, BPI_BUS3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_74, PAD_BPI_BUS2, BPI_BUS2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_75, PAD_BPI_BUS1, BPI_BUS1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_76, PAD_BPI_BUS0, BPI_BUS0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_77, PAD_BPI_ANT1, BPI_ANT1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_78, PAD_BPI_OLAT0, BPI_OLAT0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_79, PAD_BPI_PA_VM1, BPI_PA_VM1, MIPI4_SDATA, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_80, PAD_BPI_PA_VM0, BPI_PA_VM0, MIPI4_SCLK, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_81, PAD_SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_82, PAD_SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_83, PAD_SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_84, PAD_SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_85, PAD_SPI_MI, SPI0_MI, SCP_SPI0_MI, CLKM3, I2S1_BCK, MFG_DFD_JTAG_TDO, DFD_TDO, JTDO_SEL1), + PINMUX_CONSTANTS(GPIO_PAD_86, PAD_SPI_CSB, SPI0_CSB, SCP_SPI0_CS, CLKM0, I2S1_LRCK, MFG_DFD_JTAG_TMS, DFD_TMS, JTMS_SEL1), + PINMUX_CONSTANTS(GPIO_PAD_87, PAD_SPI_MO, SPI0_MO, SCP_SPI0_MO, SDA1, I2S1_DO, MFG_DFD_JTAG_TDI, DFD_TDI, JTDI_SEL1), + PINMUX_CONSTANTS(GPIO_PAD_88, PAD_SPI_CLK, SPI0_CLK, SCP_SPI0_CK, SCL1, I2S1_MCK, MFG_DFD_JTAG_TCK, DFD_TCK_XI, JTCK_SEL1), + PINMUX_CONSTANTS(GPIO_PAD_89, PAD_SRCLKENAI, SRCLKENAI0, PWM_C, I2S5_BCK, ANT_SEL6, SDA8, CMVREF0, DBG_MON_A21), + PINMUX_CONSTANTS(GPIO_PAD_90, PAD_PWM_A, PWM_A, CMMCLK2, I2S5_LRCK, SCP_VREQ_VAO, SCL8, PTA_RXD, DBG_MON_A22), + PINMUX_CONSTANTS(GPIO_PAD_91, PAD_KPROW1, KPROW1, PWM_B, I2S5_DO, ANT_SEL7, CMMCLK3, PTA_TXD, RES7), + PINMUX_CONSTANTS(GPIO_PAD_92, PAD_KPROW0, KPROW0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_93, PAD_KPCOL0, KPCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B27), + PINMUX_CONSTANTS(GPIO_PAD_94, PAD_KPCOL1, KPCOL1, I2S2_DI2, I2S5_MCK, CMMCLK2, SCP_SPI2_MI, SRCLKENAI1, SPI2_MI), + PINMUX_CONSTANTS(GPIO_PAD_95, PAD_URXD0, URXD0, UTXD0, MD_URXD0, MD_URXD1, SSPM_URXD_AO, CCU_URXD_AO, RES7), + PINMUX_CONSTANTS(GPIO_PAD_96, PAD_UTXD0, UTXD0, URXD0, MD_UTXD0, MD_UTXD1, SSPM_UTXD_AO, CCU_UTXD_AO, DBG_MON_B2), + PINMUX_CONSTANTS(GPIO_PAD_97, PAD_CAM_PDN0, UCTS0, I2S2_MCK, IDDIG, CONN_MCU_TDO, SSPM_JTAG_TDO, IO_JTAG_TDO, DBG_MON_B3), + PINMUX_CONSTANTS(GPIO_PAD_98, PAD_CAM_PDN1, URTS0, I2S2_BCK, USB_DRVVBUS, CONN_MCU_TMS, SSPM_JTAG_TMS, IO_JTAG_TMS, DBG_MON_B4), + PINMUX_CONSTANTS(GPIO_PAD_99, PAD_CAM_CLK0, CMMCLK0, RES2, RES3, CONN_MCU_AICE_TMSC, RES5, RES6, DBG_MON_B28), + PINMUX_CONSTANTS(GPIO_PAD_100, PAD_CAM_CLK1, CMMCLK1, PWM_C, MD_INT1_C2K_UIM0_HOT_PLUG, CONN_MCU_AICE_TCKC, RES5, RES6, DBG_MON_B29), + PINMUX_CONSTANTS(GPIO_PAD_101, PAD_CAM_RST0, CLKM2, I2S2_LRCK, CMVREF1, CONN_MCU_TCK, SSPM_JTAG_TCK, IO_JTAG_TCK, RES7), + PINMUX_CONSTANTS(GPIO_PAD_102, PAD_CAM_RST1, CLKM1, I2S2_DI, DVFSRC_EXT_REQ, CONN_MCU_TDI, SSPM_JTAG_TDI, IO_JTAG_TDI, DBG_MON_B8), + PINMUX_CONSTANTS(GPIO_PAD_103, PAD_SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_104, PAD_SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_105, PAD_SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_106, PAD_SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_107, PAD_CAM_PDN2, DMIC_CLK, ANT_SEL0, CLKM0, SDA7, EXT_FRAME_SYNC, PWM_A, DBG_MON_B12), + PINMUX_CONSTANTS(GPIO_PAD_108, PAD_CAM_CLK2, CMMCLK2, ANT_SEL1, CLKM1, SCL8, DAP_MD32_SWD, PWM_B, DBG_MON_B13), + PINMUX_CONSTANTS(GPIO_PAD_109, PAD_CAM_RST2, DMIC_DAT, ANT_SEL2, CLKM2, SDA8, DAP_MD32_SWCK, PWM_C, DBG_MON_B14), + PINMUX_CONSTANTS(GPIO_PAD_110, PAD_CAM_PDN3, SCL7, ANT_SEL0, TP_URXD1_AO, USB_DRVVBUS, SRCLKENAI1, KPCOL2, URXD1), + PINMUX_CONSTANTS(GPIO_PAD_111, PAD_CAM_CLK3, CMMCLK3, ANT_SEL1, SRCLKENAI0, SCP_VREQ_VAO, MD_INT2_C2K_UIM1_HOT_PLUG, RES6, DVFSRC_EXT_REQ), + PINMUX_CONSTANTS(GPIO_PAD_112, PAD_CAM_RST3, SDA7, ANT_SEL2, TP_UTXD1_AO, IDDIG, AGPS_SYNC, KPROW2, UTXD1), + PINMUX_CONSTANTS(GPIO_PAD_113, PAD_CONN_TOP_CLK, CONN_TOP_CLK, RES2, SCL6, AUXIF_CLK0, RES5, TP_UCTS1_AO, RES7), + PINMUX_CONSTANTS(GPIO_PAD_114, PAD_CONN_TOP_DATA, CONN_TOP_DATA, RES2, SDA6, AUXIF_ST0, RES5, TP_URTS1_AO, RES7), + PINMUX_CONSTANTS(GPIO_PAD_115, PAD_CONN_BT_CLK, CONN_BT_CLK, UTXD1, PTA_TXD, AUXIF_CLK1, DAP_MD32_SWD, TP_UTXD1_AO, RES7), + PINMUX_CONSTANTS(GPIO_PAD_116, PAD_CONN_BT_DATA, CONN_BT_DATA, IPU_JTAG_TRST, RES3, AUXIF_ST1, DAP_MD32_SWCK, TP_URXD2_AO, DBG_MON_A0), + PINMUX_CONSTANTS(GPIO_PAD_117, PAD_CONN_WF_CTRL0, CONN_WF_HB0, IPU_JTAG_TDO, RES3, RES4, RES5, TP_UTXD2_AO, DBG_MON_A4), + PINMUX_CONSTANTS(GPIO_PAD_118, PAD_CONN_WF_CTRL1, CONN_WF_HB1, IPU_JTAG_TDI, RES3, RES4, SSPM_URXD_AO, TP_UCTS2_AO, DBG_MON_A5), + PINMUX_CONSTANTS(GPIO_PAD_119, PAD_CONN_WF_CTRL2, CONN_WF_HB2, IPU_JTAG_TCK, RES3, RES4, SSPM_UTXD_AO, TP_URTS2_AO, RES7), + PINMUX_CONSTANTS(GPIO_PAD_120, PAD_CONN_WB_PTA, CONN_WB_PTA, IPU_JTAG_TMS, RES3, RES4, CCU_URXD_AO, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_121, PAD_CONN_HRST_B, CONN_HRST_B, URXD1, PTA_RXD, RES4, CCU_UTXD_AO, TP_URXD1_AO, RES7), + PINMUX_CONSTANTS(GPIO_PAD_122, PAD_MSDC0_CMD, MSDC0_CMD, PWRMCU_URXD2_AO, ANT_SEL1, RES4, RES5, RES6, DBG_MON_A12), + PINMUX_CONSTANTS(GPIO_PAD_123, PAD_MSDC0_DAT0, MSDC0_DAT0, RES2, ANT_SEL0, RES4, RES5, RES6, DBG_MON_A13), + PINMUX_CONSTANTS(GPIO_PAD_124, PAD_MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A14), + PINMUX_CONSTANTS(GPIO_PAD_125, PAD_MSDC0_DAT2, MSDC0_DAT2, RES2, MRG_CLK, RES4, RES5, RES6, DBG_MON_A15), + PINMUX_CONSTANTS(GPIO_PAD_126, PAD_MSDC0_DAT4, MSDC0_DAT4, RES2, ANT_SEL5, RES4, RES5, UFS_MPHY_SCL, DBG_MON_A16), + PINMUX_CONSTANTS(GPIO_PAD_127, PAD_MSDC0_DAT6, MSDC0_DAT6, RES2, ANT_SEL4, RES4, RES5, UFS_MPHY_SDA, DBG_MON_A17), + PINMUX_CONSTANTS(GPIO_PAD_128, PAD_MSDC0_DAT1, MSDC0_DAT1, RES2, ANT_SEL2, RES4, RES5, UFS_UNIPRO_SDA, DBG_MON_A18), + PINMUX_CONSTANTS(GPIO_PAD_129, PAD_MSDC0_DAT5, MSDC0_DAT5, RES2, ANT_SEL3, RES4, RES5, UFS_UNIPRO_SCL, DBG_MON_A23), + PINMUX_CONSTANTS(GPIO_PAD_130, PAD_MSDC0_DAT7, MSDC0_DAT7, RES2, MRG_DO, RES4, RES5, RES6, DBG_MON_A24), + PINMUX_CONSTANTS(GPIO_PAD_131, PAD_MSDC0_DSL, MSDC0_DSL, RES2, MRG_SYNC, RES4, RES5, RES6, DBG_MON_A25), + PINMUX_CONSTANTS(GPIO_PAD_132, PAD_MSDC0_DAT3, MSDC0_DAT3, RES2, MRG_DI, RES4, RES5, RES6, DBG_MON_A26), + PINMUX_CONSTANTS(GPIO_PAD_133, PAD_MSDC0_RSTB, MSDC0_RSTB, RES2, AGPS_SYNC, RES4, RES5, RES6, DBG_MON_A27), + PINMUX_CONSTANTS(GPIO_PAD_134, PAD_RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_135, PAD_WATCHDOG, WATCHDOG, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_136, PAD_AUD_CLK_MOSI, AUD_CLK_MOSI, AUD_CLK_MISO, I2S1_MCK, RES4, RES5, UFS_UNIPRO_SCL, RES7), + PINMUX_CONSTANTS(GPIO_PAD_137, PAD_AUD_SYNC_MOSI, AUD_SYNC_MOSI, AUD_SYNC_MISO, I2S1_BCK, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_138, PAD_AUD_DAT_MOSI0, AUD_DAT_MOSI0, AUD_DAT_MISO0, I2S1_LRCK, RES4, RES5, RES6, DBG_MON_B24), + PINMUX_CONSTANTS(GPIO_PAD_139, PAD_AUD_DAT_MOSI1, AUD_DAT_MOSI1, AUD_DAT_MISO1, I2S1_DO, RES4, RES5, UFS_MPHY_SDA, RES7), + PINMUX_CONSTANTS(GPIO_PAD_140, PAD_AUD_CLK_MISO, AUD_CLK_MISO, AUD_CLK_MOSI, I2S0_MCK, RES4, RES5, UFS_UNIPRO_SDA, RES7), + PINMUX_CONSTANTS(GPIO_PAD_141, PAD_AUD_SYNC_MISO, AUD_SYNC_MISO, AUD_SYNC_MOSI, I2S0_BCK, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_142, PAD_AUD_DAT_MISO0, AUD_DAT_MISO0, AUD_DAT_MOSI0, I2S0_LRCK, VOW_DAT_MISO, RES5, RES6, DBG_MON_B25), + PINMUX_CONSTANTS(GPIO_PAD_143, PAD_AUD_DAT_MISO1, AUD_DAT_MISO1, AUD_DAT_MOSI1, I2S0_DI, VOW_CLK_MISO, RES5, UFS_MPHY_SCL, DBG_MON_B26), + PINMUX_CONSTANTS(GPIO_PAD_144, PAD_PWRAP_SPI0_MI, PWRAP_SPI0_MI, PWRAP_SPI0_MO, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_145, PAD_PWRAP_SPI0_CSN, PWRAP_SPI0_CSN, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_146, PAD_PWRAP_SPI0_MO, PWRAP_SPI0_MO, PWRAP_SPI0_MI, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_147, PAD_PWRAP_SPI0_CK, PWRAP_SPI0_CK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_148, PAD_SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_149, PAD_SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_150, PAD_PERIPHERAL_EN0, PWM_A, CMFLASH, CLKM0, RES4, RES5, RES6, DBG_MON_B30), + PINMUX_CONSTANTS(GPIO_PAD_151, PAD_PERIPHERAL_EN1, PWM_B, CMVREF0, CLKM1, RES4, RES5, RES6, DBG_MON_B20), + PINMUX_CONSTANTS(GPIO_PAD_152, PAD_PERIPHERAL_EN2, PWM_C, CMFLASH, CLKM2, RES4, RES5, RES6, DBG_MON_B21), + PINMUX_CONSTANTS(GPIO_PAD_153, PAD_PERIPHERAL_EN3, PWM_A, CMVREF0, CLKM3, RES4, RES5, RES6, DBG_MON_B22), + PINMUX_CONSTANTS(GPIO_PAD_154, PAD_SCP_VREQ_VAO, SCP_VREQ_VAO, DVFSRC_EXT_REQ, RES3, RES4, RES5, RES6, DBG_MON_B18), + PINMUX_CONSTANTS(GPIO_PAD_155, PAD_ANT_SEL0, ANT_SEL0, DVFSRC_EXT_REQ, CMVREF1, RES4, RES5, RES6, SCP_JTAG_TDI), + PINMUX_CONSTANTS(GPIO_PAD_156, PAD_ANT_SEL1, ANT_SEL1, SRCLKENAI0, SCL6, KPCOL2, IDDIG, RES6, SCP_JTAG_TCK), + PINMUX_CONSTANTS(GPIO_PAD_157, PAD_ANT_SEL2, ANT_SEL2, SRCLKENAI1, SDA6, KPROW2, USB_DRVVBUS, RES6, SCP_JTAG_TRSTN), + PINMUX_CONSTANTS(GPIO_PAD_158, PAD_PERIPHERAL_EN6, ANT_SEL3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_159, PAD_PERIPHERAL_EN7, ANT_SEL4, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_160, PAD_PERIPHERAL_EN8, ANT_SEL5, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_161, PAD_SPI1_MI, SPI1_A_MI, SCP_SPI1_MI, IDDIG, ANT_SEL6, KPCOL2, PTA_RXD, DBG_MON_B19), + PINMUX_CONSTANTS(GPIO_PAD_162, PAD_SPI1_CSB, SPI1_A_CSB, SCP_SPI1_CS, USB_DRVVBUS, ANT_SEL5, KPROW2, PTA_TXD, RES7), + PINMUX_CONSTANTS(GPIO_PAD_163, PAD_SPI1_MO, SPI1_A_MO, SCP_SPI1_MO, SDA1, ANT_SEL4, CMMCLK2, DMIC_CLK, RES7), + PINMUX_CONSTANTS(GPIO_PAD_164, PAD_SPI1_CLK, SPI1_A_CLK, SCP_SPI1_CK, SCL1, ANT_SEL3, CMMCLK3, DMIC_DAT, RES7), + PINMUX_CONSTANTS(GPIO_PAD_165, PAD_PERIPHERAL_EN4, PWM_B, CMMCLK2, SCP_VREQ_VAO, RES4, RES5, TDM_MCK_2nd, SCP_JTAG_TDO), + PINMUX_CONSTANTS(GPIO_PAD_166, PAD_PERIPHERAL_EN9, ANT_SEL6, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_167, PAD_RFIC0_BSI_EN, RFIC0_BSI_EN, SPM_BSI_EN, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_168, PAD_RFIC0_BSI_CK, RFIC0_BSI_CK, SPM_BSI_CK, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_169, PAD_PERIPHERAL_EN5, PWM_C, CMMCLK3, CMVREF1, ANT_SEL7, AGPS_SYNC, TDM_BCK_2nd, SCP_JTAG_TMS), + PINMUX_CONSTANTS(GPIO_PAD_170, PAD_I2S1_BCK, I2S1_BCK, I2S3_BCK, SCL7, I2S5_BCK, EXT_FRAME_SYNC, TDM_LRCK_2nd, ANT_SEL3), + PINMUX_CONSTANTS(GPIO_PAD_171, PAD_I2S1_LRCK, I2S1_LRCK, I2S3_LRCK, SDA7, I2S5_LRCK, URXD1, TDM_DATA0_2nd, ANT_SEL4), + PINMUX_CONSTANTS(GPIO_PAD_172, PAD_I2S1_DO, I2S1_DO, I2S3_DO, SCL8, I2S5_DO, UTXD1, TDM_DATA1_2nd, ANT_SEL5), + PINMUX_CONSTANTS(GPIO_PAD_173, PAD_I2S1_MCK, I2S1_MCK, I2S3_MCK, SDA8, I2S5_MCK, UCTS0, TDM_DATA2_2nd, ANT_SEL6), + PINMUX_CONSTANTS(GPIO_PAD_174, PAD_I2S2_DI, I2S2_DI, I2S0_DI, DVFSRC_EXT_REQ, I2S2_DI2, URTS0, TDM_DATA3_2nd, ANT_SEL7), + PINMUX_CONSTANTS(GPIO_PAD_175, PAD_PERIPHERAL_EN12, ANT_SEL7, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_176, PAD_PERIPHERAL_EN13, RES1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_177, PAD_PERIPHERAL_EN14, RES1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_178, PAD_PERIPHERAL_EN10, RES1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_179, PAD_PERIPHERAL_EN11, RES1, RES2, RES3, RES4, RES5, RES6, RES7), +}; + +#endif /* SOC_MEDIATEK_MT8183_PINMUX_H */ -- To view, visit https://review.coreboot.org/27417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a Gerrit-Change-Number: 27417 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek: Share GPIO code among similar SOCs
by Tristan Hsieh (Code Review) 09 Jul '18

09 Jul '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27416 Change subject: mediatek: Share GPIO code among similar SOCs ...................................................................... mediatek: Share GPIO code among similar SOCs Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/oak/bootblock.c A src/soc/mediatek/common/gpio.c M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/gpio.c M src/soc/mediatek/mt8173/gpio_init.c M src/soc/mediatek/mt8173/include/soc/gpio.h M src/soc/mediatek/mt8173/include/soc/pinmux.h 7 files changed, 440 insertions(+), 293 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/27416/1 diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index fe9c9ba..8034526 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -44,9 +44,9 @@ * 3: 16mA */ /* EINT4: 0x10005B20[14:13] */ - clrsetbits_le16(&mt8173_gpio->drv_mode[2].val, 0xf << 12, 2 << 13); + clrsetbits_le16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13); /* EINT5~EINT9: 0x10005B30[2:1] */ - clrsetbits_le16(&mt8173_gpio->drv_mode[3].val, 0xf << 0, 2 << 1), + clrsetbits_le16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1), gpio_set_pull(PAD_EINT4, GPIO_PULL_ENABLE, GPIO_PULL_UP); gpio_set_pull(PAD_EINT5, GPIO_PULL_ENABLE, GPIO_PULL_UP); diff --git a/src/soc/mediatek/common/gpio.c b/src/soc/mediatek/common/gpio.c new file mode 100644 index 0000000..e6f99cb --- /dev/null +++ b/src/soc/mediatek/common/gpio.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <gpio.h> + +enum { + GPIO_DIRECTION_IN = 0, + GPIO_DIRECTION_OUT = 1, +}; + +enum { + GPIO_MODE = 0, +}; + +static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit) +{ + *pos = GPIO_GET_ID(gpio) / MAX_GPIO_REG_BITS; + *bit = GPIO_GET_ID(gpio) % MAX_GPIO_REG_BITS; +} + +static void pos_bit_calc_for_mode(gpio_t gpio, u32 *pos, u32 *bit) +{ + *pos = GPIO_GET_ID(gpio) / MAX_GPIO_MODE_PER_REG; + *bit = (GPIO_GET_ID(gpio) % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; +} + +static s32 gpio_set_dir(gpio_t gpio, u32 dir) +{ + u32 pos; + u32 bit; + u32 *reg; + + pos_bit_calc(gpio, &pos, &bit); + + if (dir == GPIO_DIRECTION_IN) + reg = &mtk_gpio->dir[pos].rst; + else + reg = &mtk_gpio->dir[pos].set; + + write32(reg, 1L << bit); + + return 0; +} + +void gpio_set_mode(gpio_t gpio, int mode) +{ + u32 pos; + u32 bit; + u32 mask = (1L << GPIO_MODE_BITS) - 1; + + pos_bit_calc_for_mode(gpio, &pos, &bit); + + clrsetbits_le32(&mtk_gpio->mode[pos].val, + mask << bit, mode << bit); +} + +int gpio_get(gpio_t gpio) +{ + u32 pos; + u32 bit; + u32 *reg; + u32 data; + + pos_bit_calc(gpio, &pos, &bit); + + reg = &mtk_gpio->din[pos].val; + data = read32(reg); + + return (data & (1L << bit)) ? 1 : 0; +} + +void gpio_set(gpio_t gpio, int output) +{ + u32 pos; + u32 bit; + u32 *reg; + + pos_bit_calc(gpio, &pos, &bit); + + if (output == 0) + reg = &mtk_gpio->dout[pos].rst; + else + reg = &mtk_gpio->dout[pos].set; + + write32(reg, 1L << bit); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + gpio_set_dir(gpio, GPIO_DIRECTION_IN); + gpio_set_mode(gpio, GPIO_MODE); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_dir(gpio, GPIO_DIRECTION_IN); + gpio_set_mode(gpio, GPIO_MODE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); + gpio_set_dir(gpio, GPIO_DIRECTION_IN); + gpio_set_mode(gpio, GPIO_MODE); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); + gpio_set(gpio, value); + gpio_set_dir(gpio, GPIO_DIRECTION_OUT); + gpio_set_mode(gpio, GPIO_MODE); +} diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 56c966a..ae7fd5b 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -27,7 +27,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c endif -bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c +bootblock-y += ../common/gpio.c gpio.c gpio_init.c pmic_wrap.c mt6391.c bootblock-y += ../common/wdt.c bootblock-y += mmu_operations.c @@ -42,7 +42,7 @@ verstage-y += timer.c verstage-y += ../common/wdt.c verstage-$(CONFIG_SPI_FLASH) += flash_controller.c -verstage-y += gpio.c +verstage-y += ../common/gpio.c gpio.c ################################################################################ @@ -54,7 +54,7 @@ romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c romstage-y += ../common/cbmem.c romstage-y += spi.c -romstage-y += gpio.c +romstage-y += ../common/gpio.c gpio.c romstage-y += pmic_wrap.c mt6391.c romstage-y += memory.c romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c @@ -73,7 +73,7 @@ ramstage-y += pmic_wrap.c mt6391.c i2c.c ramstage-y += mt6311.c ramstage-y += da9212.c -ramstage-y += gpio.c +ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/wdt.c ramstage-y += pll.c ramstage-y += rtc.c diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c index c5ca08b..f3bbeb2 100644 --- a/src/soc/mediatek/mt8173/gpio.c +++ b/src/soc/mediatek/mt8173/gpio.c @@ -14,80 +14,38 @@ */ #include <arch/io.h> #include <assert.h> -#include <console/console.h> #include <gpio.h> #include <types.h> -#include <soc/addressmap.h> -#include <soc/gpio.h> enum { - MAX_8173_GPIO = 134, - MAX_GPIO_REG_BITS = 16, - MAX_GPIO_MODE_PER_REG = 5, - GPIO_MODE_BITS = 3, + MAX_GPIO_NUMBER = 134, MAX_EINT_REG_BITS = 32, }; -enum { - GPIO_DIRECTION_IN = 0, - GPIO_DIRECTION_OUT = 1, -}; - -enum { - GPIO_MODE = 0, -}; - -static void pos_bit_calc(u32 pin, u32 *pos, u32 *bit) +static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit) { - *pos = pin / MAX_GPIO_REG_BITS; - *bit = pin % MAX_GPIO_REG_BITS; + *pos = GPIO_GET_ID(gpio) / MAX_GPIO_REG_BITS; + *bit = GPIO_GET_ID(gpio) % MAX_GPIO_REG_BITS; } -static void pos_bit_calc_for_mode(u32 pin, u32 *pos, u32 *bit) +static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit) { - *pos = pin / MAX_GPIO_MODE_PER_REG; - *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; + *pos = GPIO_GET_ID(gpio) / MAX_EINT_REG_BITS; + *bit = GPIO_GET_ID(gpio) % MAX_EINT_REG_BITS; } -static void pos_bit_calc_for_eint(u32 pin, u32 *pos, u32 *bit) -{ - *pos = pin / MAX_EINT_REG_BITS; - *bit = pin % MAX_EINT_REG_BITS; -} - -static s32 gpio_set_dir(u32 pin, u32 dir) -{ - u32 pos; - u32 bit; - u16 *reg; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); - - if (dir == GPIO_DIRECTION_IN) - reg = &mt8173_gpio->dir[pos].rst; - else - reg = &mt8173_gpio->dir[pos].set; - - write16(reg, 1L << bit); - - return 0; -} - -void gpio_set_pull(gpio_t pin, enum pull_enable enable, +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select) { u32 pos; u32 bit; - u16 *en_reg, *sel_reg; + u32 *en_reg, *sel_reg; + u32 pin = GPIO_GET_ID(gpio); - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); + pos_bit_calc(gpio, &pos, &bit); if (enable == GPIO_PULL_DISABLE) { - en_reg = &mt8173_gpio->pullen[pos].rst; + en_reg = &mtk_gpio->pullen[pos].rst; } else { /* These pins' pulls can't be set through GPIO controller. */ assert(pin < 22 || pin > 27); @@ -97,100 +55,21 @@ assert(pin < 100 || pin > 105); assert(pin < 119 || pin > 124); - en_reg = &mt8173_gpio->pullen[pos].set; + en_reg = &mtk_gpio->pullen[pos].set; sel_reg = (select == GPIO_PULL_DOWN) ? - (&mt8173_gpio->pullsel[pos].rst) : - (&mt8173_gpio->pullsel[pos].set); + (&mtk_gpio->pullsel[pos].rst) : + (&mtk_gpio->pullsel[pos].set); write16(sel_reg, 1L << bit); } write16(en_reg, 1L << bit); } -int gpio_get(gpio_t pin) -{ - u32 pos; - u32 bit; - u16 *reg; - s32 data; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); - - reg = &mt8173_gpio->din[pos].val; - data = read32(reg); - - return (data & (1L << bit)) ? 1 : 0; -} - -void gpio_set(gpio_t pin, int output) -{ - u32 pos; - u32 bit; - u16 *reg; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); - - if (output == 0) - reg = &mt8173_gpio->dout[pos].rst; - else - reg = &mt8173_gpio->dout[pos].set; - write16(reg, 1L << bit); -} - -void gpio_set_mode(gpio_t pin, int mode) -{ - u32 pos; - u32 bit; - u32 mask = (1L << GPIO_MODE_BITS) - 1; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc_for_mode(pin, &pos, &bit); - - clrsetbits_le32(&mt8173_gpio->mode[pos].val, - mask << bit, mode << bit); -} - -void gpio_input_pulldown(gpio_t gpio) -{ - gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - gpio_set_dir(gpio, GPIO_DIRECTION_IN); - gpio_set_mode(gpio, GPIO_MODE); -} - -void gpio_input_pullup(gpio_t gpio) -{ - gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); - gpio_set_dir(gpio, GPIO_DIRECTION_IN); - gpio_set_mode(gpio, GPIO_MODE); -} - -void gpio_input(gpio_t gpio) -{ - gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); - gpio_set_dir(gpio, GPIO_DIRECTION_IN); - gpio_set_mode(gpio, GPIO_MODE); -} - -void gpio_output(gpio_t gpio, int value) -{ - gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); - gpio_set(gpio, value); - gpio_set_dir(gpio, GPIO_DIRECTION_OUT); - gpio_set_mode(gpio, GPIO_MODE); -} - int gpio_eint_poll(gpio_t gpio) { u32 pos; u32 bit; u32 status; - assert(gpio <= MAX_8173_GPIO); - pos_bit_calc_for_eint(gpio, &pos, &bit); status = (read32(&mt8173_eint->sta.regs[pos]) >> bit) & 0x1; @@ -206,8 +85,6 @@ u32 pos; u32 bit, mask; - assert(gpio <= MAX_8173_GPIO); - pos_bit_calc_for_eint(gpio, &pos, &bit); mask = 1 << bit; diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index 7f8313a..79ed316 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -49,18 +49,18 @@ /* EXMD control reg */ if (ext_power == GPIO_EINT_1P8V) { /* exmd_ctrl[9:4] = b`000000, [3:0] = b`1010 */ - write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x3F5); - write16(&mt8173_gpio->exmd_ctrl[0].set, 0xA); + write16(&mtk_gpio->exmd_ctrl[0].rst, 0x3F5); + write16(&mtk_gpio->exmd_ctrl[0].set, 0xA); } else if (ext_power == GPIO_EINT_3P3V) { /* exmd_ctrl[9:4] = b`001100, [3:0] = b`1010 */ - write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x335); - write16(&mt8173_gpio->exmd_ctrl[0].set, 0xCA); + write16(&mtk_gpio->exmd_ctrl[0].rst, 0x335); + write16(&mtk_gpio->exmd_ctrl[0].set, 0xCA); } /* other R/TDSEL */ /* msdc2_ctrl5 , bit[3:0] = b`1010 */ - write16(&mt8173_gpio->msdc2_ctrl5.set, 0xA); - write16(&mt8173_gpio->msdc2_ctrl5.rst, 0x5); + write16(&mtk_gpio->msdc2_ctrl5.set, 0xA); + write16(&mtk_gpio->msdc2_ctrl5.rst, 0x5); } void gpio_init(enum external_power ext_power) diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index 1c05e48..46361ce 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -19,6 +19,12 @@ #include <stdlib.h> #include <soc/addressmap.h> +enum { + MAX_GPIO_REG_BITS = 16, + MAX_GPIO_MODE_PER_REG = 5, + GPIO_MODE_BITS = 3, +}; + enum pull_enable { GPIO_PULL_DISABLE = 0, GPIO_PULL_ENABLE = 1, @@ -34,15 +40,151 @@ GPIO_EINT_1P8V = 1, }; -typedef u32 gpio_t; +#define GPIO_GET_ID(x) (x) + +typedef enum { + GPIO_PAD_0 = 0, + GPIO_PAD_1 = 1, + GPIO_PAD_2 = 2, + GPIO_PAD_3 = 3, + GPIO_PAD_4 = 4, + GPIO_PAD_5 = 5, + GPIO_PAD_6 = 6, + GPIO_PAD_7 = 7, + GPIO_PAD_8 = 8, + GPIO_PAD_9 = 9, + GPIO_PAD_10 = 10, + GPIO_PAD_11 = 11, + GPIO_PAD_12 = 12, + GPIO_PAD_13 = 13, + GPIO_PAD_14 = 14, + GPIO_PAD_15 = 15, + GPIO_PAD_16 = 16, + GPIO_PAD_17 = 17, + GPIO_PAD_18 = 18, + GPIO_PAD_19 = 19, + GPIO_PAD_20 = 20, + GPIO_PAD_21 = 21, + GPIO_PAD_22 = 22, + GPIO_PAD_23 = 23, + GPIO_PAD_24 = 24, + GPIO_PAD_25 = 25, + GPIO_PAD_26 = 26, + GPIO_PAD_27 = 27, + GPIO_PAD_28 = 28, + GPIO_PAD_29 = 29, + GPIO_PAD_30 = 30, + GPIO_PAD_31 = 31, + GPIO_PAD_32 = 32, + GPIO_PAD_33 = 33, + GPIO_PAD_34 = 34, + GPIO_PAD_35 = 35, + GPIO_PAD_36 = 36, + GPIO_PAD_37 = 37, + GPIO_PAD_38 = 38, + GPIO_PAD_39 = 39, + GPIO_PAD_40 = 40, + GPIO_PAD_41 = 41, + GPIO_PAD_42 = 42, + GPIO_PAD_43 = 43, + GPIO_PAD_44 = 44, + GPIO_PAD_45 = 45, + GPIO_PAD_46 = 46, + GPIO_PAD_47 = 47, + GPIO_PAD_48 = 48, + GPIO_PAD_49 = 49, + GPIO_PAD_50 = 50, + GPIO_PAD_51 = 51, + GPIO_PAD_52 = 52, + GPIO_PAD_53 = 53, + GPIO_PAD_54 = 54, + GPIO_PAD_55 = 55, + GPIO_PAD_56 = 56, + GPIO_PAD_57 = 57, + GPIO_PAD_58 = 58, + GPIO_PAD_59 = 59, + GPIO_PAD_60 = 60, + GPIO_PAD_61 = 61, + GPIO_PAD_62 = 62, + GPIO_PAD_63 = 63, + GPIO_PAD_64 = 64, + GPIO_PAD_65 = 65, + GPIO_PAD_66 = 66, + GPIO_PAD_67 = 67, + GPIO_PAD_68 = 68, + GPIO_PAD_69 = 69, + GPIO_PAD_70 = 70, + GPIO_PAD_71 = 71, + GPIO_PAD_72 = 72, + GPIO_PAD_73 = 73, + GPIO_PAD_74 = 74, + GPIO_PAD_75 = 75, + GPIO_PAD_76 = 76, + GPIO_PAD_77 = 77, + GPIO_PAD_78 = 78, + GPIO_PAD_79 = 79, + GPIO_PAD_80 = 80, + GPIO_PAD_81 = 81, + GPIO_PAD_82 = 82, + GPIO_PAD_83 = 83, + GPIO_PAD_84 = 84, + GPIO_PAD_85 = 85, + GPIO_PAD_86 = 86, + GPIO_PAD_87 = 87, + GPIO_PAD_88 = 88, + GPIO_PAD_89 = 89, + GPIO_PAD_90 = 90, + GPIO_PAD_91 = 91, + GPIO_PAD_92 = 92, + GPIO_PAD_93 = 93, + GPIO_PAD_94 = 94, + GPIO_PAD_95 = 95, + GPIO_PAD_96 = 96, + GPIO_PAD_97 = 97, + GPIO_PAD_98 = 98, + GPIO_PAD_99 = 99, + GPIO_PAD_100 = 100, + GPIO_PAD_101 = 101, + GPIO_PAD_102 = 102, + GPIO_PAD_103 = 103, + GPIO_PAD_104 = 104, + GPIO_PAD_105 = 105, + GPIO_PAD_106 = 106, + GPIO_PAD_107 = 107, + GPIO_PAD_108 = 108, + GPIO_PAD_109 = 109, + GPIO_PAD_110 = 110, + GPIO_PAD_111 = 111, + GPIO_PAD_112 = 112, + GPIO_PAD_113 = 113, + GPIO_PAD_114 = 114, + GPIO_PAD_115 = 115, + GPIO_PAD_116 = 116, + GPIO_PAD_117 = 117, + GPIO_PAD_118 = 118, + GPIO_PAD_119 = 119, + GPIO_PAD_120 = 120, + GPIO_PAD_121 = 121, + GPIO_PAD_122 = 122, + GPIO_PAD_123 = 123, + GPIO_PAD_124 = 124, + GPIO_PAD_125 = 125, + GPIO_PAD_126 = 126, + GPIO_PAD_127 = 127, + GPIO_PAD_128 = 128, + GPIO_PAD_129 = 129, + GPIO_PAD_130 = 130, + GPIO_PAD_131 = 131, + GPIO_PAD_132 = 132, + GPIO_PAD_133 = 133, + GPIO_PAD_134 = 134, +} gpio_t; struct val_regs { - uint16_t val; - uint16_t align1; - uint16_t set; - uint16_t align2; - uint16_t rst; - uint16_t align3[3]; + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t align; }; struct gpio_regs { @@ -80,7 +222,7 @@ check_member(gpio_regs, msdc2_ctrl5, 0xcb0); check_member(gpio_regs, hsic_ctrl[3], 0xe50); -static struct gpio_regs *const mt8173_gpio = (void *)(GPIO_BASE); +static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select); diff --git a/src/soc/mediatek/mt8173/include/soc/pinmux.h b/src/soc/mediatek/mt8173/include/soc/pinmux.h index 07c53a8..21f6ce8 100644 --- a/src/soc/mediatek/mt8173/include/soc/pinmux.h +++ b/src/soc/mediatek/mt8173/include/soc/pinmux.h @@ -26,141 +26,141 @@ PAD_##name##_FUNC_##func7 = 7 enum { - PINMUX_CONSTANTS(0, EINT0, IRDA_PDN, I2S1_WS, AUD_SPDIF, UTXD0, RES5, RES6, DBG_MON_A_20), - PINMUX_CONSTANTS(1, EINT1, IRDA_RXD, I2S1_BCK, SDA5, URXD0, RES5, RES6, DBG_MON_A_21), - PINMUX_CONSTANTS(2, EINT2, IRDA_TXD, I2S1_MCK, SCL5, UTXD3, RES5, RES6, DBG_MON_A_22), - PINMUX_CONSTANTS(3, EINT3, DSI1_TE, I2S1_DO_1, SDA3, URXD3, RES5, RES6, DBG_MON_A_23), - PINMUX_CONSTANTS(4, EINT4, DISP_PWM1, I2S1_DO_2, SCL3, UCTS3, RES5, SFWP_B, RES7), - PINMUX_CONSTANTS(5, EINT5, PCM1_CLK, I2S2_WS, SPI_CK_3, URTS3, AP_MD32_JTAG_TMS, SFOUT, RES7), - PINMUX_CONSTANTS(6, EINT6, PCM1_SYNC, I2S2_BCK, SPI_MI_3, RES4, AP_MD32_JTAG_TCK, SFCS0, RES7), - PINMUX_CONSTANTS(7, EINT7, PCM1_DI, I2S2_DI_1, SPI_MO_3, RES4, AP_MD32_JTAG_TDI, SFHOLD, RES7), - PINMUX_CONSTANTS(8, EINT8, PCM1_DO, I2S2_DI_2, SPI_CS_3, AUD_SPDIF, AP_MD32_JTAG_TDO, SFIN, RES7), - PINMUX_CONSTANTS(9, EINT9, USB_DRVVBUS_P0, I2S2_MCK, RES3, USB_DRVVBUS_P1, AP_MD32_JTAG_TRST, SFCK, RES7), - PINMUX_CONSTANTS(10, EINT10, CLKM0, DSI1_TE, DISP_PWM1, PWM4, IRDA_RXD, RES6, RES7), - PINMUX_CONSTANTS(11, EINT11, CLKM1, I2S3_WS, USB_DRVVBUS_P0, PWM5, IRDA_TXD, USB_DRVVBUS_P1, DBG_MON_B_30), - PINMUX_CONSTANTS(12, EINT12, CLKM2, I2S3_BCK, SRCLKENA0, RES4, I2S2_WS, RES6, DBG_MON_B_32), - PINMUX_CONSTANTS(13, EINT13, CLKM3, I2S3_MCK, SRCLKENA0, RES4, I2S2_BCK, RES6, DBG_MON_A_32), - PINMUX_CONSTANTS(14, EINT14, CMDAT0, CMCSD0, RES3, CLKM2, RES5, RES6, DBG_MON_B_6), - PINMUX_CONSTANTS(15, EINT15, CMDAT1, CMCSD1, CMFLASH, CLKM3, RES5, RES6, DBG_MON_B_29), - PINMUX_CONSTANTS(16, IDDIG, IDDIG, CMFLASH, RES3, PWM5, RES5, RES6, RES7), - PINMUX_CONSTANTS(17, WATCHDOG, WATCHDOG_AO, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(18, CEC, CEC, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(19, HDMISCK, HDMISCK, HDCP_SCL, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(20, HDMISD, HDMISD, HDCP_SDA, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(21, HTPLG, HTPLG, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(22, MSDC3_DAT0, MSDC3_DAT0, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(23, MSDC3_DAT1, MSDC3_DAT1, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(24, MSDC3_DAT2, MSDC3_DAT2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(25, MSDC3_DAT3, MSDC3_DAT3, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(26, MSDC3_CLK, MSDC3_CLK, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(27, MSDC3_CMD, MSDC3_CMD, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(28, MSDC3_DSL, MSDC3_DSL, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(29, UCTS2, UCTS2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(30, URTS2, URTS2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(31, URXD2, URXD2, UTXD2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(32, UTXD2, UTXD2, URXD2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(33, DAICLK, MRG_CLK, PCM0_CLK, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(34, DAIPCMIN, MRG_DI, PCM0_DI, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(35, DAIPCMOUT, MRG_DO, PCM0_DO, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(36, DAISYNC, MRG_SYNC, PCM0_SYNC, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(37, EINT16, USB_DRVVBUS_P0, USB_DRVVBUS_P1, PWM0, PWM1, PWM2, CLKM0, RES7), - PINMUX_CONSTANTS(38, CONN_RST, USB_DRVVBUS_P0, USB_DRVVBUS_P1, RES3, RES4, RES5, CLKM1, RES7), - PINMUX_CONSTANTS(39, CM2MCLK, CM2MCLK, CMCSD0, RES3, RES4, RES5, RES6, DBG_MON_A_17), - PINMUX_CONSTANTS(40, CMPCLK, CMPCLK, CMCSK, CMCSD2, RES4, RES5, RES6, DBG_MON_A_18), - PINMUX_CONSTANTS(41, CMMCLK, CMMCLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_19), - PINMUX_CONSTANTS(42, DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(43, SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(44, SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(45, SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(46, SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(47, RDN0_A, CMDAT2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(48, RDP0_A, CMDAT3, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(49, RDN1_A, CMDAT4, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(50, RDP1_A, CMDAT5, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(51, RCN_A, CMDAT6, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(52, RCP_A, CMDAT7, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(53, RDN2_A, CMDAT8, CMCSD3, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(54, RDP2_A, CMDAT9, CMCSD2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(55, RDN3_A, CMHSYNC, CMCSD1, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(56, RDP3_A, CMVSYNC, CMCSD0, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(57, MSDC0_DAT0, MSDC0_DAT0, I2S1_WS, RES3, RES4, RES5, RES6, DBG_MON_B_7), - PINMUX_CONSTANTS(58, MSDC0_DAT1, MSDC0_DAT1, I2S1_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_8), - PINMUX_CONSTANTS(59, MSDC0_DAT2, MSDC0_DAT2, I2S1_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_9), - PINMUX_CONSTANTS(60, MSDC0_DAT3, MSDC0_DAT3, I2S1_DO_1, RES3, RES4, RES5, RES6, DBG_MON_B_10), - PINMUX_CONSTANTS(61, MSDC0_DAT4, MSDC0_DAT4, I2S1_DO_2, RES3, RES4, RES5, RES6, DBG_MON_B_11), - PINMUX_CONSTANTS(62, MSDC0_DAT5, MSDC0_DAT5, I2S2_WS, RES3, RES4, RES5, RES6, DBG_MON_B_12), - PINMUX_CONSTANTS(63, MSDC0_DAT6, MSDC0_DAT6, I2S2_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_13), - PINMUX_CONSTANTS(64, MSDC0_DAT7, MSDC0_DAT7, I2S2_DI_1, RES3, RES4, RES5, RES6, DBG_MON_B_14), - PINMUX_CONSTANTS(65, MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_16), - PINMUX_CONSTANTS(66, MSDC0_CMD, MSDC0_CMD, I2S2_DI_2, RES3, RES4, RES5, RES6, DBG_MON_B_15), - PINMUX_CONSTANTS(67, MSDC0_DSL, MSDC0_DSL, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_17), - PINMUX_CONSTANTS(68, MSDC0_RST, MSDC0_RSTB, I2S2_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_18), - PINMUX_CONSTANTS(69, SPI_CK, SPI_CK_0, I2S3_DO_1, PWM0, PWM5, I2S2_MCK, RES6, DBG_MON_B_19), - PINMUX_CONSTANTS(70, SPI_MI, SPI_MI_0, I2S3_DO_2, PWM1, SPI_MO_0, I2S2_DI_1, DSI1_TE, DBG_MON_B_20), - PINMUX_CONSTANTS(71, SPI_MO, SPI_MO_0, I2S3_DO_3, PWM2, SPI_MI_0, I2S2_DI_2, RES6, DBG_MON_B_21), - PINMUX_CONSTANTS(72, SPI_CS, SPI_CS_0, I2S3_DO_4, PWM3, PWM6, DISP_PWM1, RES6, DBG_MON_B_22), - PINMUX_CONSTANTS(73, MSDC1_DAT0, MSDC1_DAT0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_24), - PINMUX_CONSTANTS(74, MSDC1_DAT1, MSDC1_DAT1, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_25), - PINMUX_CONSTANTS(75, MSDC1_DAT2, MSDC1_DAT2, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_26), - PINMUX_CONSTANTS(76, MSDC1_DAT3, MSDC1_DAT3, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_27), - PINMUX_CONSTANTS(77, MSDC1_CLK, MSDC1_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_28), - PINMUX_CONSTANTS(78, MSDC1_CMD, MSDC1_CMD, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_23), - PINMUX_CONSTANTS(79, PWRAP_SPI0_MI, PWRAP_SPIMI, PWRAP_SPIMO, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(80, PWRAP_SPI0_MO, PWRAP_SPIMO, PWRAP_SPIMI, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(81, PWRAP_SPI0_CK, PWRAP_SPICK, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(82, PWRAP_SPI0_CSN, PWRAP_SPICS, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(83, AUD_CLK_MOSI, AUD_CLK_MOSI, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(84, AUD_DAT_MISO, AUD_DAT_MISO, AUD_DAT_MOSI, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(85, AUD_DAT_MOSI, AUD_DAT_MOSI, AUD_DAT_MISO, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(86, RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(87, DISP_PWM0, DISP_PWM0, DISP_PWM1, RES3, RES4, RES5, RES6, DBG_MON_B_31), - PINMUX_CONSTANTS(88, SRCLKENAI, SRCLKENAI, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(89, SRCLKENAI2, SRCLKENAI2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(90, SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(91, SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(92, PCM_CLK, PCM1_CLK, I2S0_BCK, RES3, RES4, RES5, RES6, DBG_MON_A_24), - PINMUX_CONSTANTS(93, PCM_SYNC, PCM1_SYNC, I2S0_WS, RES3, RES4, RES5, RES6, DBG_MON_A_25), - PINMUX_CONSTANTS(94, PCM_RX, PCM1_DI, I2S0_DI, RES3, RES4, RES5, RES6, DBG_MON_A_26), - PINMUX_CONSTANTS(95, PCM_TX, PCM1_DO, I2S0_DO, RES3, RES4, RES5, RES6, DBG_MON_A_27), - PINMUX_CONSTANTS(96, URXD1, URXD1, UTXD1, RES3, RES4, RES5, RES6, DBG_MON_A_28), - PINMUX_CONSTANTS(97, UTXD1, UTXD1, URXD1, RES3, RES4, RES5, RES6, DBG_MON_A_29), - PINMUX_CONSTANTS(98, URTS1, URTS1, UCTS1, RES3, RES4, RES5, RES6, DBG_MON_A_30), - PINMUX_CONSTANTS(99, UCTS1, UCTS1, URTS1, RES3, RES4, RES5, RES6, DBG_MON_A_31), - PINMUX_CONSTANTS(100, MSDC2_DAT0, MSDC2_DAT0, RES2, USB_DRVVBUS_P0, SDA5, USB_DRVVBUS_P1, RES6, DBG_MON_B_0), - PINMUX_CONSTANTS(101, MSDC2_DAT1, MSDC2_DAT1, RES2, AUD_SPDIF, SCL5, RES5, RES6, DBG_MON_B_1), - PINMUX_CONSTANTS(102, MSDC2_DAT2, MSDC2_DAT2, RES2, UTXD0, RES4, PWM0, SPI_CK_1, DBG_MON_B_2), - PINMUX_CONSTANTS(103, MSDC2_DAT3, MSDC2_DAT3, RES2, URXD0, RES4, PWM1, SPI_MI_1, DBG_MON_B_3), - PINMUX_CONSTANTS(104, MSDC2_CLK, MSDC2_CLK, RES2, UTXD3, SDA3, PWM2, SPI_MO_1, DBG_MON_B_4), - PINMUX_CONSTANTS(105, MSDC2_CMD, MSDC2_CMD, RES2, URXD3, SCL3, PWM3, SPI_CS_1, DBG_MON_B_5), - PINMUX_CONSTANTS(106, SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(107, SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(108, JTMS, JTMS, MFG_JTAG_TMS, RES3, RES4, AP_MD32_JTAG_TMS, DFD_TMS, RES7), - PINMUX_CONSTANTS(109, JTCK, JTCK, MFG_JTAG_TCK, RES3, RES4, AP_MD32_JTAG_TCK, DFD_TCK, RES7), - PINMUX_CONSTANTS(110, JTDI, JTDI, MFG_JTAG_TDI, RES3, RES4, AP_MD32_JTAG_TDI, DFD_TDI, RES7), - PINMUX_CONSTANTS(111, JTDO, JTDO, MFG_JTAG_TDO, RES3, RES4, AP_MD32_JTAG_TDO, DFD_TDO, RES7), - PINMUX_CONSTANTS(112, JTRST_B, JTRST_B, MFG_JTAG_TRSTN, RES3, RES4, AP_MD32_JTAG_TRST, DFD_NTRST, RES7), - PINMUX_CONSTANTS(113, URXD0, URXD0, UTXD0, RES3, RES4, RES5, I2S2_WS, DBG_MON_A_0), - PINMUX_CONSTANTS(114, UTXD0, UTXD0, URXD0, RES3, RES4, RES5, I2S2_BCK, DBG_MON_A_1), - PINMUX_CONSTANTS(115, URTS0, URTS0, UCTS0, RES3, RES4, RES5, I2S2_MCK, DBG_MON_A_2), - PINMUX_CONSTANTS(116, UCTS0, UCTS0, URTS0, RES3, RES4, RES5, I2S2_DI_1, DBG_MON_A_3), - PINMUX_CONSTANTS(117, URXD3, URXD3, UTXD3, RES3, RES4, RES5, RES6, DBG_MON_A_9), - PINMUX_CONSTANTS(118, UTXD3, UTXD3, URXD3, RES3, RES4, RES5, RES6, DBG_MON_A_10), - PINMUX_CONSTANTS(119, KPROW0, KROW0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_11), - PINMUX_CONSTANTS(120, KPROW1, KROW1, RES2, PWM6, RES4, RES5, RES6, DBG_MON_A_12), - PINMUX_CONSTANTS(121, KPROW2, KROW2, IRDA_PDN, USB_DRVVBUS_P0, PWM4, USB_DRVVBUS_P1, RES6, DBG_MON_A_13), - PINMUX_CONSTANTS(122, KPCOL0, KCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_14), - PINMUX_CONSTANTS(123, KPCOL1, KCOL1, IRDA_RXD, PWM5, RES4, RES5, RES6, DBG_MON_A_15), - PINMUX_CONSTANTS(124, KPCOL2, KCOL2, IRDA_TXD, USB_DRVVBUS_P0, PWM3, USB_DRVVBUS_P1, RES6, DBG_MON_A_16), - PINMUX_CONSTANTS(125, SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(126, SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(127, LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(128, I2S0_LRCK, I2S0_WS, I2S1_WS, I2S2_WS, RES4, SPI_CK_2, RES6, DBG_MON_A_4), - PINMUX_CONSTANTS(129, I2S0_BCK, I2S0_BCK, I2S1_BCK, I2S2_BCK, RES4, SPI_MI_2, RES6, DBG_MON_A_5), - PINMUX_CONSTANTS(130, I2S0_MCK, I2S0_MCK, I2S1_MCK, I2S2_MCK, RES4, SPI_MO_2, RES6, DBG_MON_A_6), - PINMUX_CONSTANTS(131, I2S0_DATA0, I2S0_DO, I2S1_DO_1, I2S2_DI_1, RES4, SPI_CS_2, RES6, DBG_MON_A_7), - PINMUX_CONSTANTS(132, I2S0_DATA1, I2S0_DI, I2S1_DO_2, I2S2_DI_2, RES4, RES5, RES6, DBG_MON_A_8), - PINMUX_CONSTANTS(133, SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(134, SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_0, EINT0, IRDA_PDN, I2S1_WS, AUD_SPDIF, UTXD0, RES5, RES6, DBG_MON_A_20), + PINMUX_CONSTANTS(GPIO_PAD_1, EINT1, IRDA_RXD, I2S1_BCK, SDA5, URXD0, RES5, RES6, DBG_MON_A_21), + PINMUX_CONSTANTS(GPIO_PAD_2, EINT2, IRDA_TXD, I2S1_MCK, SCL5, UTXD3, RES5, RES6, DBG_MON_A_22), + PINMUX_CONSTANTS(GPIO_PAD_3, EINT3, DSI1_TE, I2S1_DO_1, SDA3, URXD3, RES5, RES6, DBG_MON_A_23), + PINMUX_CONSTANTS(GPIO_PAD_4, EINT4, DISP_PWM1, I2S1_DO_2, SCL3, UCTS3, RES5, SFWP_B, RES7), + PINMUX_CONSTANTS(GPIO_PAD_5, EINT5, PCM1_CLK, I2S2_WS, SPI_CK_3, URTS3, AP_MD32_JTAG_TMS, SFOUT, RES7), + PINMUX_CONSTANTS(GPIO_PAD_6, EINT6, PCM1_SYNC, I2S2_BCK, SPI_MI_3, RES4, AP_MD32_JTAG_TCK, SFCS0, RES7), + PINMUX_CONSTANTS(GPIO_PAD_7, EINT7, PCM1_DI, I2S2_DI_1, SPI_MO_3, RES4, AP_MD32_JTAG_TDI, SFHOLD, RES7), + PINMUX_CONSTANTS(GPIO_PAD_8, EINT8, PCM1_DO, I2S2_DI_2, SPI_CS_3, AUD_SPDIF, AP_MD32_JTAG_TDO, SFIN, RES7), + PINMUX_CONSTANTS(GPIO_PAD_9, EINT9, USB_DRVVBUS_P0, I2S2_MCK, RES3, USB_DRVVBUS_P1, AP_MD32_JTAG_TRST, SFCK, RES7), + PINMUX_CONSTANTS(GPIO_PAD_10, EINT10, CLKM0, DSI1_TE, DISP_PWM1, PWM4, IRDA_RXD, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_11, EINT11, CLKM1, I2S3_WS, USB_DRVVBUS_P0, PWM5, IRDA_TXD, USB_DRVVBUS_P1, DBG_MON_B_30), + PINMUX_CONSTANTS(GPIO_PAD_12, EINT12, CLKM2, I2S3_BCK, SRCLKENA0, RES4, I2S2_WS, RES6, DBG_MON_B_32), + PINMUX_CONSTANTS(GPIO_PAD_13, EINT13, CLKM3, I2S3_MCK, SRCLKENA0, RES4, I2S2_BCK, RES6, DBG_MON_A_32), + PINMUX_CONSTANTS(GPIO_PAD_14, EINT14, CMDAT0, CMCSD0, RES3, CLKM2, RES5, RES6, DBG_MON_B_6), + PINMUX_CONSTANTS(GPIO_PAD_15, EINT15, CMDAT1, CMCSD1, CMFLASH, CLKM3, RES5, RES6, DBG_MON_B_29), + PINMUX_CONSTANTS(GPIO_PAD_16, IDDIG, IDDIG, CMFLASH, RES3, PWM5, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_17, WATCHDOG, WATCHDOG_AO, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_18, CEC, CEC, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_19, HDMISCK, HDMISCK, HDCP_SCL, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_20, HDMISD, HDMISD, HDCP_SDA, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_21, HTPLG, HTPLG, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_22, MSDC3_DAT0, MSDC3_DAT0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_23, MSDC3_DAT1, MSDC3_DAT1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_24, MSDC3_DAT2, MSDC3_DAT2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_25, MSDC3_DAT3, MSDC3_DAT3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_26, MSDC3_CLK, MSDC3_CLK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_27, MSDC3_CMD, MSDC3_CMD, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_28, MSDC3_DSL, MSDC3_DSL, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_29, UCTS2, UCTS2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_30, URTS2, URTS2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_31, URXD2, URXD2, UTXD2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_32, UTXD2, UTXD2, URXD2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_33, DAICLK, MRG_CLK, PCM0_CLK, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_34, DAIPCMIN, MRG_DI, PCM0_DI, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_35, DAIPCMOUT, MRG_DO, PCM0_DO, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_36, DAISYNC, MRG_SYNC, PCM0_SYNC, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_37, EINT16, USB_DRVVBUS_P0, USB_DRVVBUS_P1, PWM0, PWM1, PWM2, CLKM0, RES7), + PINMUX_CONSTANTS(GPIO_PAD_38, CONN_RST, USB_DRVVBUS_P0, USB_DRVVBUS_P1, RES3, RES4, RES5, CLKM1, RES7), + PINMUX_CONSTANTS(GPIO_PAD_39, CM2MCLK, CM2MCLK, CMCSD0, RES3, RES4, RES5, RES6, DBG_MON_A_17), + PINMUX_CONSTANTS(GPIO_PAD_40, CMPCLK, CMPCLK, CMCSK, CMCSD2, RES4, RES5, RES6, DBG_MON_A_18), + PINMUX_CONSTANTS(GPIO_PAD_41, CMMCLK, CMMCLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_19), + PINMUX_CONSTANTS(GPIO_PAD_42, DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_43, SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_44, SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_45, SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_46, SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_47, RDN0_A, CMDAT2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_48, RDP0_A, CMDAT3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_49, RDN1_A, CMDAT4, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_50, RDP1_A, CMDAT5, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_51, RCN_A, CMDAT6, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_52, RCP_A, CMDAT7, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_53, RDN2_A, CMDAT8, CMCSD3, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_54, RDP2_A, CMDAT9, CMCSD2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_55, RDN3_A, CMHSYNC, CMCSD1, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_56, RDP3_A, CMVSYNC, CMCSD0, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_57, MSDC0_DAT0, MSDC0_DAT0, I2S1_WS, RES3, RES4, RES5, RES6, DBG_MON_B_7), + PINMUX_CONSTANTS(GPIO_PAD_58, MSDC0_DAT1, MSDC0_DAT1, I2S1_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_8), + PINMUX_CONSTANTS(GPIO_PAD_59, MSDC0_DAT2, MSDC0_DAT2, I2S1_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_9), + PINMUX_CONSTANTS(GPIO_PAD_60, MSDC0_DAT3, MSDC0_DAT3, I2S1_DO_1, RES3, RES4, RES5, RES6, DBG_MON_B_10), + PINMUX_CONSTANTS(GPIO_PAD_61, MSDC0_DAT4, MSDC0_DAT4, I2S1_DO_2, RES3, RES4, RES5, RES6, DBG_MON_B_11), + PINMUX_CONSTANTS(GPIO_PAD_62, MSDC0_DAT5, MSDC0_DAT5, I2S2_WS, RES3, RES4, RES5, RES6, DBG_MON_B_12), + PINMUX_CONSTANTS(GPIO_PAD_63, MSDC0_DAT6, MSDC0_DAT6, I2S2_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_13), + PINMUX_CONSTANTS(GPIO_PAD_64, MSDC0_DAT7, MSDC0_DAT7, I2S2_DI_1, RES3, RES4, RES5, RES6, DBG_MON_B_14), + PINMUX_CONSTANTS(GPIO_PAD_65, MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_16), + PINMUX_CONSTANTS(GPIO_PAD_66, MSDC0_CMD, MSDC0_CMD, I2S2_DI_2, RES3, RES4, RES5, RES6, DBG_MON_B_15), + PINMUX_CONSTANTS(GPIO_PAD_67, MSDC0_DSL, MSDC0_DSL, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_17), + PINMUX_CONSTANTS(GPIO_PAD_68, MSDC0_RST, MSDC0_RSTB, I2S2_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_18), + PINMUX_CONSTANTS(GPIO_PAD_69, SPI_CK, SPI_CK_0, I2S3_DO_1, PWM0, PWM5, I2S2_MCK, RES6, DBG_MON_B_19), + PINMUX_CONSTANTS(GPIO_PAD_70, SPI_MI, SPI_MI_0, I2S3_DO_2, PWM1, SPI_MO_0, I2S2_DI_1, DSI1_TE, DBG_MON_B_20), + PINMUX_CONSTANTS(GPIO_PAD_71, SPI_MO, SPI_MO_0, I2S3_DO_3, PWM2, SPI_MI_0, I2S2_DI_2, RES6, DBG_MON_B_21), + PINMUX_CONSTANTS(GPIO_PAD_72, SPI_CS, SPI_CS_0, I2S3_DO_4, PWM3, PWM6, DISP_PWM1, RES6, DBG_MON_B_22), + PINMUX_CONSTANTS(GPIO_PAD_73, MSDC1_DAT0, MSDC1_DAT0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_24), + PINMUX_CONSTANTS(GPIO_PAD_74, MSDC1_DAT1, MSDC1_DAT1, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_25), + PINMUX_CONSTANTS(GPIO_PAD_75, MSDC1_DAT2, MSDC1_DAT2, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_26), + PINMUX_CONSTANTS(GPIO_PAD_76, MSDC1_DAT3, MSDC1_DAT3, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_27), + PINMUX_CONSTANTS(GPIO_PAD_77, MSDC1_CLK, MSDC1_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_28), + PINMUX_CONSTANTS(GPIO_PAD_78, MSDC1_CMD, MSDC1_CMD, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_23), + PINMUX_CONSTANTS(GPIO_PAD_79, PWRAP_SPI0_MI, PWRAP_SPIMI, PWRAP_SPIMO, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_80, PWRAP_SPI0_MO, PWRAP_SPIMO, PWRAP_SPIMI, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_81, PWRAP_SPI0_CK, PWRAP_SPICK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_82, PWRAP_SPI0_CSN, PWRAP_SPICS, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_83, AUD_CLK_MOSI, AUD_CLK_MOSI, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_84, AUD_DAT_MISO, AUD_DAT_MISO, AUD_DAT_MOSI, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_85, AUD_DAT_MOSI, AUD_DAT_MOSI, AUD_DAT_MISO, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_86, RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_87, DISP_PWM0, DISP_PWM0, DISP_PWM1, RES3, RES4, RES5, RES6, DBG_MON_B_31), + PINMUX_CONSTANTS(GPIO_PAD_88, SRCLKENAI, SRCLKENAI, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_89, SRCLKENAI2, SRCLKENAI2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_90, SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_91, SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_92, PCM_CLK, PCM1_CLK, I2S0_BCK, RES3, RES4, RES5, RES6, DBG_MON_A_24), + PINMUX_CONSTANTS(GPIO_PAD_93, PCM_SYNC, PCM1_SYNC, I2S0_WS, RES3, RES4, RES5, RES6, DBG_MON_A_25), + PINMUX_CONSTANTS(GPIO_PAD_94, PCM_RX, PCM1_DI, I2S0_DI, RES3, RES4, RES5, RES6, DBG_MON_A_26), + PINMUX_CONSTANTS(GPIO_PAD_95, PCM_TX, PCM1_DO, I2S0_DO, RES3, RES4, RES5, RES6, DBG_MON_A_27), + PINMUX_CONSTANTS(GPIO_PAD_96, URXD1, URXD1, UTXD1, RES3, RES4, RES5, RES6, DBG_MON_A_28), + PINMUX_CONSTANTS(GPIO_PAD_97, UTXD1, UTXD1, URXD1, RES3, RES4, RES5, RES6, DBG_MON_A_29), + PINMUX_CONSTANTS(GPIO_PAD_98, URTS1, URTS1, UCTS1, RES3, RES4, RES5, RES6, DBG_MON_A_30), + PINMUX_CONSTANTS(GPIO_PAD_99, UCTS1, UCTS1, URTS1, RES3, RES4, RES5, RES6, DBG_MON_A_31), + PINMUX_CONSTANTS(GPIO_PAD_100, MSDC2_DAT0, MSDC2_DAT0, RES2, USB_DRVVBUS_P0, SDA5, USB_DRVVBUS_P1, RES6, DBG_MON_B_0), + PINMUX_CONSTANTS(GPIO_PAD_101, MSDC2_DAT1, MSDC2_DAT1, RES2, AUD_SPDIF, SCL5, RES5, RES6, DBG_MON_B_1), + PINMUX_CONSTANTS(GPIO_PAD_102, MSDC2_DAT2, MSDC2_DAT2, RES2, UTXD0, RES4, PWM0, SPI_CK_1, DBG_MON_B_2), + PINMUX_CONSTANTS(GPIO_PAD_103, MSDC2_DAT3, MSDC2_DAT3, RES2, URXD0, RES4, PWM1, SPI_MI_1, DBG_MON_B_3), + PINMUX_CONSTANTS(GPIO_PAD_104, MSDC2_CLK, MSDC2_CLK, RES2, UTXD3, SDA3, PWM2, SPI_MO_1, DBG_MON_B_4), + PINMUX_CONSTANTS(GPIO_PAD_105, MSDC2_CMD, MSDC2_CMD, RES2, URXD3, SCL3, PWM3, SPI_CS_1, DBG_MON_B_5), + PINMUX_CONSTANTS(GPIO_PAD_106, SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_107, SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_108, JTMS, JTMS, MFG_JTAG_TMS, RES3, RES4, AP_MD32_JTAG_TMS, DFD_TMS, RES7), + PINMUX_CONSTANTS(GPIO_PAD_109, JTCK, JTCK, MFG_JTAG_TCK, RES3, RES4, AP_MD32_JTAG_TCK, DFD_TCK, RES7), + PINMUX_CONSTANTS(GPIO_PAD_110, JTDI, JTDI, MFG_JTAG_TDI, RES3, RES4, AP_MD32_JTAG_TDI, DFD_TDI, RES7), + PINMUX_CONSTANTS(GPIO_PAD_111, JTDO, JTDO, MFG_JTAG_TDO, RES3, RES4, AP_MD32_JTAG_TDO, DFD_TDO, RES7), + PINMUX_CONSTANTS(GPIO_PAD_112, JTRST_B, JTRST_B, MFG_JTAG_TRSTN, RES3, RES4, AP_MD32_JTAG_TRST, DFD_NTRST, RES7), + PINMUX_CONSTANTS(GPIO_PAD_113, URXD0, URXD0, UTXD0, RES3, RES4, RES5, I2S2_WS, DBG_MON_A_0), + PINMUX_CONSTANTS(GPIO_PAD_114, UTXD0, UTXD0, URXD0, RES3, RES4, RES5, I2S2_BCK, DBG_MON_A_1), + PINMUX_CONSTANTS(GPIO_PAD_115, URTS0, URTS0, UCTS0, RES3, RES4, RES5, I2S2_MCK, DBG_MON_A_2), + PINMUX_CONSTANTS(GPIO_PAD_116, UCTS0, UCTS0, URTS0, RES3, RES4, RES5, I2S2_DI_1, DBG_MON_A_3), + PINMUX_CONSTANTS(GPIO_PAD_117, URXD3, URXD3, UTXD3, RES3, RES4, RES5, RES6, DBG_MON_A_9), + PINMUX_CONSTANTS(GPIO_PAD_118, UTXD3, UTXD3, URXD3, RES3, RES4, RES5, RES6, DBG_MON_A_10), + PINMUX_CONSTANTS(GPIO_PAD_119, KPROW0, KROW0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_11), + PINMUX_CONSTANTS(GPIO_PAD_120, KPROW1, KROW1, RES2, PWM6, RES4, RES5, RES6, DBG_MON_A_12), + PINMUX_CONSTANTS(GPIO_PAD_121, KPROW2, KROW2, IRDA_PDN, USB_DRVVBUS_P0, PWM4, USB_DRVVBUS_P1, RES6, DBG_MON_A_13), + PINMUX_CONSTANTS(GPIO_PAD_122, KPCOL0, KCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_14), + PINMUX_CONSTANTS(GPIO_PAD_123, KPCOL1, KCOL1, IRDA_RXD, PWM5, RES4, RES5, RES6, DBG_MON_A_15), + PINMUX_CONSTANTS(GPIO_PAD_124, KPCOL2, KCOL2, IRDA_TXD, USB_DRVVBUS_P0, PWM3, USB_DRVVBUS_P1, RES6, DBG_MON_A_16), + PINMUX_CONSTANTS(GPIO_PAD_125, SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_126, SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_127, LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_128, I2S0_LRCK, I2S0_WS, I2S1_WS, I2S2_WS, RES4, SPI_CK_2, RES6, DBG_MON_A_4), + PINMUX_CONSTANTS(GPIO_PAD_129, I2S0_BCK, I2S0_BCK, I2S1_BCK, I2S2_BCK, RES4, SPI_MI_2, RES6, DBG_MON_A_5), + PINMUX_CONSTANTS(GPIO_PAD_130, I2S0_MCK, I2S0_MCK, I2S1_MCK, I2S2_MCK, RES4, SPI_MO_2, RES6, DBG_MON_A_6), + PINMUX_CONSTANTS(GPIO_PAD_131, I2S0_DATA0, I2S0_DO, I2S1_DO_1, I2S2_DI_1, RES4, SPI_CS_2, RES6, DBG_MON_A_7), + PINMUX_CONSTANTS(GPIO_PAD_132, I2S0_DATA1, I2S0_DI, I2S1_DO_2, I2S2_DI_2, RES4, RES5, RES6, DBG_MON_A_8), + PINMUX_CONSTANTS(GPIO_PAD_133, SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(GPIO_PAD_134, SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7), }; #endif /* SOC_MEDIATEK_MT8173_PINMUX_H */ -- To view, visit https://review.coreboot.org/27416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Gerrit-Change-Number: 27416 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: soc/intel/braswell/acpi/dptf/thermal.asl: Thermal event
by Frans Hendriks (Code Review) 09 Jul '18

09 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27415 to look at the new patch set (#2). Change subject: soc/intel/braswell/acpi/dptf/thermal.asl: Thermal event ...................................................................... soc/intel/braswell/acpi/dptf/thermal.asl: Thermal event The thermal event support can not be disabled. Define and depend code are placed in same file. Move HAVE_THERM_EVENT_HANDLER to mainboard file. Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/acpi/dptf.asl M src/soc/intel/braswell/acpi/dptf/thermal.asl 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/27415/2 -- To view, visit https://review.coreboot.org/27415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Gerrit-Change-Number: 27415 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/braswell/acpi/dptf/thermal.asl: Thermal event
by build bot (Jenkins) (Code Review) 09 Jul '18

09 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27415 ) Change subject: soc/intel/braswell/acpi/dptf/thermal.asl: Thermal event ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/27415/1/src/soc/intel/braswell/acpi/dptf/th… File src/soc/intel/braswell/acpi/dptf/thermal.asl: https://review.coreboot.org/#/c/27415/1/src/soc/intel/braswell/acpi/dptf/th… PS1, Line 5: trailing whitespace -- To view, visit https://review.coreboot.org/27415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Gerrit-Change-Number: 27415 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Jul 2018 10:30:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/braswell/acpi/dptf/thermal.asl: Thermal event
by Frans Hendriks (Code Review) 09 Jul '18

09 Jul '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/27415 Change subject: soc/intel/braswell/acpi/dptf/thermal.asl: Thermal event ...................................................................... soc/intel/braswell/acpi/dptf/thermal.asl: Thermal event The thermal event support can not be disabled. Define and depend code are placed in same file. Move HAVE_THERM_EVENT_HANDLER to mainboard file. Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/acpi/dptf.asl M src/soc/intel/braswell/acpi/dptf/thermal.asl 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/27415/1 diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 3ecb040..dd6bb68 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2012 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,6 +15,8 @@ * GNU General Public License for more details. */ +#define HAVE_THERM_EVENT_HANDLER + /* Include Variant DPTF */ #include <variant/acpi/dptf.asl> diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index e104756..ec17411 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2018 Eltan B.V. + * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of @@ -13,7 +15,7 @@ */ /* Thermal Threshold Event Handler */ -#define HAVE_THERM_EVENT_HANDLER +#ifdef HAVE_THERM_EVENT_HANDLER Method (TEVT, 1, NotSerialized) { Store (ToInteger (Arg0), Local0) @@ -34,6 +36,7 @@ } #endif } +#endif /* Thermal device initialization - Disable Aux Trip Points */ Method (TINI) -- To view, visit https://review.coreboot.org/27415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Gerrit-Change-Number: 27415 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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