Anonymous Coward (1001664) has uploaded this change for review. ( https://review.coreboot.org/27356
Change subject: riscv: add spin lock support ......................................................................
riscv: add spin lock support
Add spin lock support for riscv.
Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Signed-off-by: Xiang Wang wxjstz@126.com --- M src/arch/riscv/include/arch/smp/atomic.h M src/arch/riscv/include/arch/smp/spinlock.h 2 files changed, 26 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/27356/1
diff --git a/src/arch/riscv/include/arch/smp/atomic.h b/src/arch/riscv/include/arch/smp/atomic.h index 15702e4..f1d8e45 100644 --- a/src/arch/riscv/include/arch/smp/atomic.h +++ b/src/arch/riscv/include/arch/smp/atomic.h @@ -33,9 +33,6 @@ #define disable_irqsave() clear_csr(mstatus, MSTATUS_MIE) #define enable_irqrestore(flags) set_csr(mstatus, (flags) & MSTATUS_MIE)
-typedef struct { int lock; } spinlock_t; -#define SPINLOCK_INIT {0} - #define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val) #define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h index bdf8ec4..089ab9f 100644 --- a/src/arch/riscv/include/arch/smp/spinlock.h +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -10,3 +10,29 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#ifndef _SPINLOCK_H_ +#define _SPINLOCK_H_ + +#include <arch/encoding.h> +#include <arch/smp/atomic.h> + +#define barrier() { asm volatile ("fence" ::: "memory"); } + +typedef struct { + volatile unsigned int lock; +} spinlock_t; + +static inline void spinlock_lock(spinlock_t *lock) +{ + do { + } while (atomic_cas(&lock->lock, 0, -1)); + barrier(); +} + +static inline void spinlock_unlock(spinlock_t *lock) +{ + barrier(); + atomic_set(&lock->lock, 0); +} + +#endif //_SPINLOCK_H_