coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mediatek/mt8183: Add MMU operation support
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27303 ) Change subject: mediatek/mt8183: Add MMU operation support ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75661/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/29715/ : SUCCESS -- To view, visit https://review.coreboot.org/27303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32 Gerrit-Change-Number: 27303 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ting Shen <phoenixshen(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 16:29:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Makefile.inc: Rewrite $(files-in-dir)
by Nico Huber (Code Review) 02 Jul '18

02 Jul '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/27324 Change subject: Makefile.inc: Rewrite $(files-in-dir) ...................................................................... Makefile.inc: Rewrite $(files-in-dir) The $(files-in-dir) macro is supposed to return all files (out of a given set) that reside directly (non-recursive) in a given directory. While the current solution worked splendidly, we can achieve the same without recursive macros that look at each parent dir individually. This also fixes a future make error, as make doesn't like the variable name ` ` anymore ;) Change-Id: Iac0eacdf91b8b5098592ad301c1f3fdb632454e9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile.inc 1 file changed, 8 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/27324/1 diff --git a/Makefile.inc b/Makefile.inc index 446e321..67ddb63 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -155,29 +155,19 @@ # Helper functions for ramstage postprocess spc := spc += -$(spc) := -$(spc) += comma := , -# files-in-dir-recursive,dir,files -files-in-dir-recursive=$(filter $(1)%,$(2)) +# Returns all files and dirs below `dir` (recursively). +# files-below-dir,dir,files +files-below-dir=$(filter $(1)%,$(2)) -# parent-dir,dir/ -parent-dir=$(dir $(if $(patsubst /%,,$(1)),,/)$(subst $( ),/,$(strip $(subst /, ,$(1))))) +# Returns all dirs below `dir` (recursively). +# dirs-below-dir,dir,files +dirs-below-dir=$(filter-out $(1),$(sort $(dir $(call files-below-dir,$(1),$(2))))) -# filters out exactly the directory specified -# filter-out-dir,dir_to_keep,dirs -filter-out-dir=$(filter-out $(1),$(2)) - -# filters out dir_to_keep and all its parents -# filter-out-dirs,dir_to_keep,dirs -filter-out-dirs=$(if $(filter-out ./ /,$(1)),$(call filter-out-dirs,$(call parent-dir,$(1)),$(call filter-out-dir,$(1),$(2))),$(call filter-out-dir,$(1),$(2))) - -# dir-wildcards,dirs -dir-wildcards=$(addsuffix %,$(1)) - +# Returns all files directly in `dir` (non-recursively). # files-in-dir,dir,files -files-in-dir=$(filter-out $(call dir-wildcards,$(call filter-out-dirs,$(1),$(sort $(dir $(2))))),$(call files-in-dir-recursive,$(1),$(2))) +files-in-dir=$(filter-out $(addsuffix %,$(call dirs-below-dir,$(1),$(2))),$(call files-below-dir,$(1),$(2))) ####################################################################### # reduce command line length by linking the objects of each -- To view, visit https://review.coreboot.org/27324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iac0eacdf91b8b5098592ad301c1f3fdb632454e9 Gerrit-Change-Number: 27324 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: google/kukui: Update MMU table in romstage and ramstage
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27304 ) Change subject: google/kukui: Update MMU table in romstage and ramstage ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75660/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/29714/ : SUCCESS -- To view, visit https://review.coreboot.org/27304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c Gerrit-Change-Number: 27304 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ting Shen <phoenixshen(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 16:24:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: correct GPIO emission error in ACPI
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27306 ) Change subject: soc/amd/stoneyridge: correct GPIO emission error in ACPI ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/75658/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/29712/ : SUCCESS -- To view, visit https://review.coreboot.org/27306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Gerrit-Change-Number: 27306 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Jul 2018 16:18:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/i945: Add macro for device 0:01.0
by Elyes HAOUAS (Code Review) 02 Jul '18

02 Jul '18

Hello Arthur Heymans, Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27307 to look at the new patch set (#2). Change subject: nb/intel/i945: Add macro for device 0:01.0 ...................................................................... nb/intel/i945: Add macro for device 0:01.0 Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h 2 files changed, 21 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/27307/2 -- To view, visit https://review.coreboot.org/27307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5 Gerrit-Change-Number: 27307 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: nb/intel/i945: Add macro for device 0:01.0
by Elyes HAOUAS (Code Review) 02 Jul '18

02 Jul '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27307 Change subject: nb/intel/i945: Add macro for device 0:01.0 ...................................................................... nb/intel/i945: Add macro for device 0:01.0 Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h 2 files changed, 20 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/27307/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7de2c73..c741e51 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -575,25 +575,25 @@ */ /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); if (!(reg16 & 0x48)) goto disable_pciexpress_x16_link; reg16 |= (1 << 4) | (1 << 0); - pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), SLOTSTS, reg16); - pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00); - pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00); - pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a); - pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a); + pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x00); + pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x00); + pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x0a); + pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x0a); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); reg32 &= ~(1 << 8); @@ -639,12 +639,12 @@ reg32 |= 1; pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 |= (1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); reg16 &= ~(1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; @@ -700,17 +700,17 @@ /* Enable GPEs */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec); reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32); /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114); reg32 &= 0xffffff01; - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32); /* Extended VC count */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x104); reg32 &= ~(7 << 0); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32); /* Active State Power Management ASPM */ diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index cc5f087..b5e7440 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -84,6 +84,10 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ #define BCTRL1 0x3e /* 16bit */ +#define SBUSN1 0x19 /* 8bit */ +#define SUBUSN1 0x1a /* 8bit */ +#define SLOTSTS 0xba /* 16bit */ +#define VC0RCTL 0x114 /* 32bit */ #define PEGSTS 0x214 /* 32bit */ -- To view, visit https://review.coreboot.org/27307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5 Gerrit-Change-Number: 27307 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/amd/stoneyridge: correct GPIO emission error in ACPI
by Kevin Chiu (Code Review) 02 Jul '18

02 Jul '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/27306 Change subject: soc/amd/stoneyridge: correct GPIO emission error in ACPI ...................................................................... soc/amd/stoneyridge: correct GPIO emission error in ACPI It can not emit byte data without BytePrefix. BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot extract SSDT then check ACPI syntax is correct Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/soc/amd/stoneyridge/acpi.c 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/27306/1 diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 8130b79..5f9e792 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -357,14 +357,19 @@ } uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); + /* Store (0x40, Local0) */ + acpigen_write_store(); + acpigen_write_integer(GPIO_PIN_OUT); + acpigen_emit_byte(LOCAL0_OP); + acpigen_soc_get_gpio_in_local5(addr); if (val) { /* Or (Local5, GPIO_PIN_OUT, Local5) */ - acpigen_write_or(LOCAL5_OP, GPIO_PIN_OUT, LOCAL5_OP); + acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); } else { /* Not (GPIO_PIN_OUT, Local6) */ - acpigen_write_not(GPIO_PIN_OUT, LOCAL6_OP); + acpigen_write_not(LOCAL0_OP, LOCAL6_OP); /* And (Local5, Local6, Local5) */ acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); -- To view, visit https://review.coreboot.org/27306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Gerrit-Change-Number: 27306 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: mediatek: Share PLL code among similar SOCs
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27305 ) Change subject: mediatek: Share PLL code among similar SOCs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29707/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75653/ : SUCCESS -- To view, visit https://review.coreboot.org/27305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c Gerrit-Change-Number: 27305 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 09:48:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek/mt8183: Add MMU operation support
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27303 ) Change subject: mediatek/mt8183: Add MMU operation support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29705/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75652/ : SUCCESS -- To view, visit https://review.coreboot.org/27303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32 Gerrit-Change-Number: 27303 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 09:42:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek/mt8183: add PLL and clock init support
by build bot (Jenkins) (Code Review) 02 Jul '18

02 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27031 ) Change subject: mediatek/mt8183: add PLL and clock init support ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/29706/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/75651/ : SUCCESS -- To view, visit https://review.coreboot.org/27031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c Gerrit-Change-Number: 27031 Gerrit-PatchSet: 11 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Jul 2018 09:42:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit July 2018