coreboot-gerrit July 2018

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Change in coreboot[master]: cavium/bdk: Read DDR freq from memory controller
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27451 Change subject: cavium/bdk: Read DDR freq from memory controller ...................................................................... cavium/bdk: Read DDR freq from memory controller The BDK config subsystem can't store values in romstage. Read frequency from DDR memory controller instead from BDK config. Fixes memory info showing always 0 MT/s. Change-Id: Iaee33e57e27ca182f41be923cf950868f66d3638 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-config.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/27451/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-config.c b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-config.c index 5c10423..2ec7a1a 100644 --- a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-config.c +++ b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-config.c @@ -106,7 +106,7 @@ snprintf(info_string, INFO_STRING_LEN, " %ld MB, %ld MT/s, %s %s", bdk_dram_get_size_mbytes(node), - bdk_config_get_int(BDK_CONFIG_DDR_SPEED, node), + libdram_get_freq_from_pll(node, 0) / 1000000, (__bdk_dram_is_ddr4(node, 0)) ? "DDR4" : "DDR3", (__bdk_dram_is_rdimm(node, 0)) ? "RDIMM" : "UDIMM"); -- To view, visit https://review.coreboot.org/27451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaee33e57e27ca182f41be923cf950868f66d3638 Gerrit-Change-Number: 27451 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: Coverity: Fix CID1393974
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27450 Change subject: Coverity: Fix CID1393974 ...................................................................... Coverity: Fix CID1393974 Fix OVERFLOW_BEFORE_WIDEN. Change-Id: I39caea8a248d2f1debfca307f6fb7a2fe3e431b1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/gpio.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27450/1 diff --git a/src/soc/cavium/cn81xx/gpio.c b/src/soc/cavium/cn81xx/gpio.c index 340ac1b..84e36d1 100644 --- a/src/soc/cavium/cn81xx/gpio.c +++ b/src/soc/cavium/cn81xx/gpio.c @@ -103,9 +103,9 @@ printk(BIOS_SPEW, "GPIO(%u): level: %u\n", gpio, !!value); if (value) - write64(&regs->tx_set, 1 << gpio); + write64(&regs->tx_set, 1ULL << gpio); else - write64(&regs->tx_clr, 1 << gpio); + write64(&regs->tx_clr, 1ULL << gpio); } /* Set GPIO direction to OUTPUT with level */ @@ -153,9 +153,10 @@ return 0; const u64 reg = read64(&regs->rx_dat); - printk(BIOS_SPEW, "GPIO(%u): input: %u\n", gpio, !!(reg & (1 << gpio))); + printk(BIOS_SPEW, "GPIO(%u): input: %u\n", gpio, + !!(reg & (1ULL << gpio))); - return !!(reg & (1 << gpio)); + return !!(reg & (1ULL << gpio)); } /* Read GPIO STRAP level sampled at cold boot */ @@ -167,9 +168,10 @@ return 0; const u64 reg = read64(&regs->strap); - printk(BIOS_SPEW, "GPIO(%u): strap: %u\n", gpio, !!(reg & (1 << gpio))); + printk(BIOS_SPEW, "GPIO(%u): strap: %u\n", gpio, + !!(reg & (1ULL << gpio))); - return !!(reg & (1 << gpio)); + return !!(reg & (1ULL << gpio)); } /* FIXME: Parse devicetree ? */ -- To view, visit https://review.coreboot.org/27450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I39caea8a248d2f1debfca307f6fb7a2fe3e431b1 Gerrit-Change-Number: 27450 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: Coverity: Fix CID1393975
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27449 Change subject: Coverity: Fix CID1393975 ...................................................................... Coverity: Fix CID1393975 Fix possible buffer overrun. Change-Id: I275cabf55fba464be7bd4c21dfe5826ea554ac84 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27449/1 diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c index 1c98808..192a8a9 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c @@ -2312,7 +2312,7 @@ seq_ctl.s.seq_sel = sequence; VB_PRT(VBL_SEQ, "N%d.LMC%d: Performing LMC sequence=%x: rank_mask=0x%02x, %s\n", - node, ddr_interface_num, sequence, rank_mask, sequence_str[sequence]); + node, ddr_interface_num, sequence, rank_mask, sequence < 12 ? sequence_str[sequence] : ""); if ((s = lookup_env_parameter("ddr_trigger_sequence%d", sequence)) != NULL) { /* FIXME(dhendrix): this appears to be meant for the eval board */ -- To view, visit https://review.coreboot.org/27449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I275cabf55fba464be7bd4c21dfe5826ea554ac84 Gerrit-Change-Number: 27449 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: bdk: Use Kconfig options instead of getenv()
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27448 Change subject: bdk: Use Kconfig options instead of getenv() ...................................................................... bdk: Use Kconfig options instead of getenv() * Use Kconfig options instead of unusable getenv * Select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS on CN81XX * Fix Coverity CID 1393976 (DEADCODE) Tested on Cavium's cn8100_sff_evb. Change-Id: Ia16c0161b0e9cf5d06418e46556c0fb45532a5b1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/Kconfig M src/vendorcode/cavium/Kconfig M src/vendorcode/cavium/bdk/libdram/libdram.c 3 files changed, 26 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/27448/1 diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index ca8fbd0..9cc7b48 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -11,6 +11,7 @@ select HAVE_MONOTONIC_TIMER select UART_OVERRIDE_REFCLK select SOC_CAVIUM_COMMON + select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS if SOC_CAVIUM_CN81XX diff --git a/src/vendorcode/cavium/Kconfig b/src/vendorcode/cavium/Kconfig index 8037762..37d22c3 100644 --- a/src/vendorcode/cavium/Kconfig +++ b/src/vendorcode/cavium/Kconfig @@ -65,6 +65,27 @@ depends on CAVIUM_BDK help Build Cavium's BDK with verbose PHY code. + +config CAVIUM_BDK_DDR_TUNE_HW_OFFSETS + bool "Hardware assisted DLL read offset tuning" + default n + depends on CAVIUM_BDK + + help + Automatically tune the data byte DLL read offsets. + Always done by default, but allow use of HW-assist. + NOTE: HW-assist will also tune the ECC byte + +config CAVIUM_BDK_DDR_TUNE_WRITE_OFFSETS + bool "Automatically tune thw data byte DLL write offsets" + default n + depends on CAVIUM_BDK + +config CAVIUM_BDK_DDR_TUNE_ECC_ENABLE + bool "Automatically tune the ECC byte DLL read offsets" + default n + depends on CAVIUM_BDK + endmenu endif diff --git a/src/vendorcode/cavium/bdk/libdram/libdram.c b/src/vendorcode/cavium/bdk/libdram/libdram.c index 551ba24..bebd520 100644 --- a/src/vendorcode/cavium/bdk/libdram/libdram.c +++ b/src/vendorcode/cavium/bdk/libdram/libdram.c @@ -149,23 +149,16 @@ static int bdk_libdram_tune_node(int node) { int errs, tot_errs; - int do_dllro_hw = 0; // default to NO - int do_dllwo = 0; // default to NO - int do_eccdll = 0; // default to NO - const char *str; + int do_dllro_hw = IS_ENABLED(CONFIG_CAVIUM_BDK_DDR_TUNE_HW_OFFSETS); + int do_dllwo = IS_ENABLED(CONFIG_CAVIUM_BDK_DDR_TUNE_WRITE_OFFSETS); + int do_eccdll = IS_ENABLED(CONFIG_CAVIUM_BDK_DDR_TUNE_ECC_ENABLE); BDK_CSR_INIT(lmc_config, node, BDK_LMCX_CONFIG(0)); // FIXME: probe LMC0 do_eccdll = (lmc_config.s.ecc_ena != 0); // change to ON if ECC enabled - // FIXME!!! make 81xx always use HW-assist tuning - if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) - do_dllro_hw = 1; - // Automatically tune the data byte DLL read offsets // always done by default, but allow use of HW-assist // NOTE: HW-assist will also tune the ECC byte - str = getenv("ddr_tune_hw_offsets"); - if (str) - do_dllro_hw = !!strtoul(str, NULL, 0); + BDK_TRACE(DRAM, "N%d: Starting DLL Read Offset Tuning for LMCs\n", node); if (!do_dllro_hw || (lmc_config.s.mode32b != 0)) { errs = perform_dll_offset_tuning(node, 2, /* tune */1); @@ -179,10 +172,6 @@ // disabled by default for now, does not seem to be needed? // Automatically tune the data byte DLL write offsets // allow override of default setting - str = getenv("ddr_tune_write_offsets"); - str = NULL; - if (str) - do_dllwo = !!strtoul(str, NULL, 0); if (do_dllwo) { BDK_TRACE(DRAM, "N%d: Starting DLL Write Offset Tuning for LMCs\n", node); errs = perform_dll_offset_tuning(node, /* write */1, /* tune */1); @@ -195,9 +184,6 @@ // Automatically tune the ECC byte DLL read offsets // FIXME? allow override of the filtering // FIXME? allow programmatic override, not via envvar? - str = getenv("ddr_tune_ecc_enable"); - if (str) - do_eccdll = !!strtoul(str, NULL, 10); if (do_eccdll && !do_dllro_hw && (lmc_config.s.mode32b == 0)) { // do not do HW-assist twice for ECC BDK_TRACE(DRAM, "N%d: Starting ECC DLL Read Offset Tuning for LMCs\n", node); errs = perform_HW_dll_offset_tuning(node, 2, 8/* ECC bytelane */); -- To view, visit https://review.coreboot.org/27448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia16c0161b0e9cf5d06418e46556c0fb45532a5b1 Gerrit-Change-Number: 27448 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: Coverity: Fix CID1393976
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27447 Change subject: Coverity: Fix CID1393976 ...................................................................... Coverity: Fix CID1393976 Cast to u64 to prevent possible integer overflow. Change-Id: I5c7d25278db54523242314cba6c85ac2f7a6c1f3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/cavium/cn81xx/clock.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/27447/1 diff --git a/src/soc/cavium/cn81xx/clock.c b/src/soc/cavium/cn81xx/clock.c index bd6514c..02f152f 100644 --- a/src/soc/cavium/cn81xx/clock.c +++ b/src/soc/cavium/cn81xx/clock.c @@ -63,7 +63,7 @@ rst_boot.u = read64((void *)RST_PF_BAR0); - return rst_boot.s.pnr_mul * PLL_REF_CLK; + return ((u64)rst_boot.s.pnr_mul) * PLL_REF_CLK; } /** @@ -75,5 +75,5 @@ rst_boot.u = read64((void *)RST_PF_BAR0); - return rst_boot.s.c_mul * PLL_REF_CLK; + return ((u64)rst_boot.s.c_mul) * PLL_REF_CLK; } -- To view, visit https://review.coreboot.org/27447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5c7d25278db54523242314cba6c85ac2f7a6c1f3 Gerrit-Change-Number: 27447 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: Coverity: Fix CID1393978
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27446 Change subject: Coverity: Fix CID1393978 ...................................................................... Coverity: Fix CID1393978 Fix a typo. Only memcpy into target buffer if pointer is not NULL. Change-Id: I1aa4b2ce1843e53ab6ed2224eaa928fc79ea3b83 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/27446/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c index a8e65f0..0df70eb 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c @@ -519,7 +519,7 @@ { int grow = device_list_max + DEVICE_GROW; bdk_device_t *tmp = malloc(grow * sizeof(bdk_device_t)); - if (!tmp) + if (tmp) memcpy(tmp, device_list, device_list_max * sizeof(bdk_device_t)); free(device_list); if (tmp == NULL) -- To view, visit https://review.coreboot.org/27446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1aa4b2ce1843e53ab6ed2224eaa928fc79ea3b83 Gerrit-Change-Number: 27446 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: Coverity: Fix CID1393979
by Patrick Rudolph (Code Review) 12 Jul '18

12 Jul '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27445 Change subject: Coverity: Fix CID1393979 ...................................................................... Coverity: Fix CID1393979 Fix resource leak in dt_set_bin_prop_by_path(). Change-Id: I1c4d7e01b25847a2091ad90d2d70711beae55905 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/lib/device_tree.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/27445/1 diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 3d44f39..00b36fd 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -944,6 +944,7 @@ prop_name = strrchr(path_copy, '/'); if (!prop_name) { + free(path_copy); printk(BIOS_ERR, "Path %s does not include '/'\n", path); return 1; } @@ -956,10 +957,12 @@ if (!dt_node) { printk(BIOS_ERR, "Failed to %s %s in the device tree\n", create ? "create" : "find", path_copy); + free(path_copy); return 1; } dt_add_bin_prop(dt_node, prop_name, data, data_size); + free(path_copy); return 0; } -- To view, visit https://review.coreboot.org/27445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1c4d7e01b25847a2091ad90d2d70711beae55905 Gerrit-Change-Number: 27445 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: riscv: add support for modifying compiler options
by Xiang Wang (Code Review) 12 Jul '18

12 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27442 to look at the new patch set (#3). Change subject: riscv: add support for modifying compiler options ...................................................................... riscv: add support for modifying compiler options Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/soc/lowrisc/lowrisc/Kconfig M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 5 files changed, 50 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27442/3 -- To view, visit https://review.coreboot.org/27442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Gerrit-Change-Number: 27442 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add support for modifying compiler options
by Xiang Wang (Code Review) 12 Jul '18

12 Jul '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/27442 to look at the new patch set (#2). Change subject: riscv: add support for modifying compiler options ...................................................................... riscv: add support for modifying compiler options Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 4 files changed, 38 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27442/2 -- To view, visit https://review.coreboot.org/27442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Gerrit-Change-Number: 27442 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add support for modifying compiler options
by Xiang Wang (Code Review) 12 Jul '18

12 Jul '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27442 Change subject: riscv: add support for modifying compiler options ...................................................................... riscv: add support for modifying compiler options Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 4 files changed, 34 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27442/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 2513c50..b060ba34 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -2,12 +2,14 @@ bool default n -config ARCH_RISCV_COMPRESSED - bool - default n - help - Enable this option if your RISC-V processor supports compressed - instructions (RVC). Currently, this enables RVC for all stages. +config RISCV_ARCH + string + +config RISCV_ABI + string + +config RISCV_CMODEL + string config ARCH_BOOTBLOCK_RISCV bool diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 4b2ff03..e6e0d42 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -23,15 +23,9 @@ check-ramstage-overlap-regions += stack endif -riscv_arch = rv64imafd +riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y) - riscv_arch := $(riscv_arch)c -endif - -riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch) - -riscv_asm_flags = -march=$(riscv_arch) +riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) ################################################################################ ## bootblock diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index d247c28..b589fab 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -23,4 +23,16 @@ if SOC_SIFIVE_FU540 +config RISCV_ARCH + string + default "rv64imac" + +config RISCV_ABI + string + default "lp64" + +config RISCV_CMODEL + string + default "medany" + endif diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index ff50f6f..4b0cdb7 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -10,4 +10,16 @@ if SOC_UCB_RISCV +config RISCV_ARCH + string + default "rv64imafd" + +config RISCV_ABI + string + default "lp64" + +config RISCV_CMODEL + string + default "medany" + endif -- To view, visit https://review.coreboot.org/27442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Gerrit-Change-Number: 27442 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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coreboot-gerrit July 2018