coreboot-gerrit July 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??.
by Frans Hendriks (Code Review) 13 Jul '18

13 Jul '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/27471 Change subject: soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??. ...................................................................... soc/intel/braswell/ramstage.c: SoC D-1 revision reported as stepping ??. No support for SoC D-1 stepping is available. According to Intel doc #332095-015 stepping C-0 has revision id 0x21 and D-1 revision ID 0x35. Also correct the RID_C_STEPPING_START value for C-0. BUG=none TEST=Built, Intel Cherry Hill Rev F. Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/include/soc/lpc.h M src/soc/intel/braswell/ramstage.c 2 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/27471/1 diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h index d842274..7b1e3424 100644 --- a/src/soc/intel/braswell/include/soc/lpc.h +++ b/src/soc/intel/braswell/include/soc/lpc.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,7 +37,8 @@ #define RID_A_STEPPING_START 1 #define RID_B_STEPPING_START 5 -#define RID_C_STEPPING_START 0xe +#define RID_C_STEPPING_START 0x21 +#define RID_D_STEPPING_START 0x35 enum soc_stepping { STEP_A0, STEP_A1, @@ -45,6 +47,7 @@ STEP_B2, STEP_B3, STEP_C0, + STEP_D1, }; /* Registers behind the RCBA_BASE_ADDRESS bar. */ diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 4559739..20c09d5 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -73,7 +74,7 @@ } static const char *const stepping_str[] = { - "A0", "A1", "B0", "B1", "B2", "B3", "C0" + "A0", "A1", "B0", "B1", "B2", "B3", "C0", "D1" }; static void fill_in_pattrs(void) @@ -86,7 +87,10 @@ dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); attrs->revid = pci_read_config8(dev, REVID); /* The revision to stepping IDs have two values per metal stepping. */ - if (attrs->revid >= RID_C_STEPPING_START) { + if (attrs->revid >= RID_D_STEPPING_START) { + attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2; + attrs->stepping += STEP_D1; + } else if (attrs->revid >= RID_C_STEPPING_START) { attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; attrs->stepping += STEP_C0; } else if (attrs->revid >= RID_B_STEPPING_START) { -- To view, visit https://review.coreboot.org/27471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4 Gerrit-Change-Number: 27471 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: util/docker: Update coreboot-jenkins-node dockerfile
by Patrick Georgi (Code Review) 13 Jul '18

13 Jul '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/27470 ) Change subject: util/docker: Update coreboot-jenkins-node dockerfile ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/27470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I21fd2c4395d7ffb9428172f035991338658cd907 Gerrit-Change-Number: 27470 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Jul 2018 07:36:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/cavium: Enable DRAM test
by build bot (Jenkins) (Code Review) 13 Jul '18

13 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27103 ) Change subject: soc/cavium: Enable DRAM test ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/#/c/27103/6/src/soc/cavium/cn81xx/sdram.c File src/soc/cavium/cn81xx/sdram.c: https://review.coreboot.org/#/c/27103/6/src/soc/cavium/cn81xx/sdram.c@93 PS6, Line 93: if (0 != bdk_numa_master()) Comparisons should place the constant on the right side of the test https://review.coreboot.org/#/c/27103/6/src/soc/cavium/cn81xx/sdram.c@97 PS6, Line 97: if (0 == bdk_numa_master()) Comparisons should place the constant on the right side of the test -- To view, visit https://review.coreboot.org/27103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf Gerrit-Change-Number: 27103 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Jul 2018 06:41:04 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium: Apply additional devicetree fixups
by build bot (Jenkins) (Code Review) 13 Jul '18

13 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25382 ) Change subject: soc/cavium: Apply additional devicetree fixups ...................................................................... Patch Set 39: (4 comments) https://review.coreboot.org/#/c/25382/39/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/25382/39/src/soc/cavium/cn81xx/soc.c@82 PS39, Line 82: Remove 'phy-handle' if this option is not availble */ 'availble' may be misspelled - perhaps 'available'? https://review.coreboot.org/#/c/25382/39/src/soc/cavium/cn81xx/soc.c@140 PS39, Line 140: /* Extract our MAC address info so we can assign them in the device tree */ line over 80 characters https://review.coreboot.org/#/c/25382/39/src/soc/cavium/cn81xx/soc.c@172 PS39, Line 172: if (!strcmp(name, prop->prop.name)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25382/39/src/soc/cavium/cn81xx/soc.c@268 PS39, Line 268: BDK_BGXX_CMRX_RX_DMAC_CTL(bgx_interface, bgx_index)); line over 80 characters -- To view, visit https://review.coreboot.org/25382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Gerrit-Change-Number: 25382 Gerrit-PatchSet: 39 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Jul 2018 06:39:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [HACK]cavium/arm-trusted-firmware: Use 9elements ATF
by build bot (Jenkins) (Code Review) 13 Jul '18

13 Jul '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25751 ) Change subject: [HACK]cavium/arm-trusted-firmware: Use 9elements ATF ...................................................................... Patch Set 28: (2 comments) https://review.coreboot.org/#/c/25751/28/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/25751/28/src/soc/cavium/cn81xx/soc.c@73 PS28, Line 73: void *ptr = cbfs_boot_map_with_leak("sff8104-linux.dtb", CBFS_TYPE_RAW, &size); line over 80 characters https://review.coreboot.org/#/c/25751/28/src/soc/cavium/common/include/soc/… File src/soc/cavium/common/include/soc/bl31_plat_params.h: https://review.coreboot.org/#/c/25751/28/src/soc/cavium/common/include/soc/… PS28, Line 21: #include <soc/cavium/common/arm-trusted-firmware/plat/cavium/common/include/plat_params.h> line over 80 characters -- To view, visit https://review.coreboot.org/25751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Gerrit-Change-Number: 25751 Gerrit-PatchSet: 28 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Jul 2018 06:39:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/docker: Update coreboot-jenkins-node dockerfile
by Martin Roth (Code Review) 13 Jul '18

13 Jul '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/27470 Change subject: util/docker: Update coreboot-jenkins-node dockerfile ...................................................................... util/docker: Update coreboot-jenkins-node dockerfile Because earlier versions of debian set /dev as a standard tmpfs filesystem, that was a simple place to build. Now, this has been changed and /dev isn't a standard tmpfs that will grow to 50% of memory. It's a fixed, very small size, and can no longer even be resized. Because of this, create a new directory to build in and add it to /etc/fstab. Mount it when the container is started. As long as we're at it, make the other build directories tmpfs as well. The builders we're using now have plenty of memory, so don't write any of the files to disk. Change-Id: I21fd2c4395d7ffb9428172f035991338658cd907 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M util/docker/coreboot-jenkins-node/Dockerfile 1 file changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/27470/1 diff --git a/util/docker/coreboot-jenkins-node/Dockerfile b/util/docker/coreboot-jenkins-node/Dockerfile index 230842c..763d473 100644 --- a/util/docker/coreboot-jenkins-node/Dockerfile +++ b/util/docker/coreboot-jenkins-node/Dockerfile @@ -17,9 +17,6 @@ MAINTAINER Martin Roth <martin(a)coreboot.org> USER root -# Check to make sure /dev is a tmpfs file system -RUN mount | grep "on /dev type tmpfs" > /dev/null || exit 1 - RUN apt-get -y update && \ apt-get -y install \ lua5.3 liblua5.3-dev openjdk-8-jre-headless openssh-server && \ @@ -37,6 +34,17 @@ chmod 0755 /var/run/sshd && \ /usr/bin/ssh-keygen -A +# Create /cb-build as a tmpfs directory to build in +RUN mkdir /cb-build && \ + chown coreboot:coreboot /cb-build && \ + echo "tmpfs /cb-build tmpfs rw,mode=1777 0 0" > /etc/fstab && \ + mkdir -p /home/coreboot/slave-root/workspace && \ + chown -R coreboot:coreboot /home/coreboot/slave-root && \ + echo "tmpfs /home/coreboot/slave-root/workspace tmpfs rw,mode=1777 0 0" >> /etc/fstab && \ + mkdir /home/coreboot/.ccache_tmpfs && \ + chown coreboot:coreboot /home/coreboot/.ccache_tmpfs && \ + echo "tmpfs /home/coreboot/.ccache_tmpfs tmpfs rw,mode=1777 0 0" >> /etc/fstab + # Build encapsulate tool ADD https://raw.githubusercontent.com/pgeorgi/encapsulate/master/encapsulate.c /tmp/encapsulate.c RUN gcc -o /usr/sbin/encapsulate /tmp/encapsulate.c && \ @@ -44,6 +52,9 @@ chmod +s /usr/sbin/encapsulate VOLUME /data/cache -ENTRYPOINT mkdir /dev/cb-build && chown coreboot /dev/cb-build && /usr/sbin/sshd -p 49151 -D +ENTRYPOINT mount /cb-build && \ + mount /home/coreboot/slave-root/workspace && \ + mount /home/coreboot/.ccache_tmpfs && \ + /usr/sbin/sshd -p 49151 -D EXPOSE 49151 ENV PATH $PATH:/usr/sbin -- To view, visit https://review.coreboot.org/27470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I21fd2c4395d7ffb9428172f035991338658cd907 Gerrit-Change-Number: 27470 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: google/grunt: fix thermal zone CPU temperature report
by Kevin Chiu (Code Review) 13 Jul '18

13 Jul '18

Hello chris wang, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27469 to look at the new patch set (#3). Change subject: google/grunt: fix thermal zone CPU temperature report ...................................................................... google/grunt: fix thermal zone CPU temperature report there are 3 thermal sensors and index is: 0: 1 Charger 1: 1 SOC 2: 0 CPU it needs to adjust sensor to index 2 to have correct CPU temperature. BUG=b:111284412 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h M src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27469/3 -- To view, visit https://review.coreboot.org/27469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Gerrit-Change-Number: 27469 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com>

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Change in coreboot[master]: google/grunt: fix thermal zone CPU temperature report
by Kevin Chiu (Code Review) 13 Jul '18

13 Jul '18

Hello chris wang, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/27469 to look at the new patch set (#2). Change subject: google/grunt: fix thermal zone CPU temperature report ...................................................................... google/grunt: fix thermal zone CPU temperature report there are 3 thermal sensors and index is: 0: 1 Charger 1: 1 SOC 2: 0 CPU it needs to adjust sensor to index 2 to have correct CPU temperature. BUG=b:111284412 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h M src/mainboard/google/kahlee/variants/grunt/include/variant/thermal.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27469/2 -- To view, visit https://review.coreboot.org/27469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Gerrit-Change-Number: 27469 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com>

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Change in coreboot[master]: google/grunt: fix thermal zone CPU temperature report
by Kevin Chiu (Code Review) 13 Jul '18

13 Jul '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/27469 Change subject: google/grunt: fix thermal zone CPU temperature report ...................................................................... google/grunt: fix thermal zone CPU temperature report there are 3 thermal sensors and index is: 0: 1 Charger 1: 1 SOC 2: 0 CPU it needs to adjust sensor to index 2 to have correct CPU temperature. BUG=b:111284412 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27469/1 diff --git a/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h index 2c983bb..fb67b73 100644 --- a/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h +++ b/src/mainboard/google/kahlee/variants/careena/include/variant/thermal.h @@ -27,7 +27,7 @@ */ /* Control TDP Settings */ -#define CTL_TDP_SENSOR_ID 0 /* EC TIN0 */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN0 */ /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 94 -- To view, visit https://review.coreboot.org/27469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Gerrit-Change-Number: 27469 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: soc/intel/coffeelake: Add initial coffeelake support
by Lijian Zhao (Code Review) 12 Jul '18

12 Jul '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/27468 Change subject: soc/intel/coffeelake: Add initial coffeelake support ...................................................................... soc/intel/coffeelake: Add initial coffeelake support Add coffeelake config and include path to coffeelake fsp header files. BUG=N/A TEST=Using private mainboard file can boot up on coffeelake rvp platform. Change-Id: Ide180de32a9d1896bed85b9e093963721c3d6041 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27468/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 101d71e..fea6bb3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -3,6 +3,13 @@ help Intel Cannonlake support +config SOC_INTEL_COFFEELAKE + bool + default n + select SOC_INTEL_CANNONLAKE + help + Intel Coffeelake support + if SOC_INTEL_CANNONLAKE config CPU_SPECIFIC_OPTIONS @@ -71,6 +78,7 @@ select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO + config UART_FOR_CONSOLE int "Index for LPSS UART port to use for console" default 2 if DRIVERS_UART_8250MEM_32 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index f8f9198..0a09eb6 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -73,8 +73,11 @@ verstage-y += spi.c verstage-$(CONFIG_UART_DEBUG) += uart.c -CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20 +ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y) +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/coffeelake +else CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake +endif CPPFLAGS_common += -I$(src)/soc/intel/cannonlake CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include -- To view, visit https://review.coreboot.org/27468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide180de32a9d1896bed85b9e093963721c3d6041 Gerrit-Change-Number: 27468 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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coreboot-gerrit July 2018